microcontroller based rapid prototyping systemmicrocontroller based rapid prototyping system...

Microcontroller based Rapid Prototyping SystemSPYDERTM - VIRTEX - X2E

User’s Manual

- Version 1.11.1 / Dec. 17, 2001 -

2 of 73 User Manual SPYDER-VIRTEX-X2E Rev. 1.11.1

University of Tübingen, Department of Technical Computer Science

and

Sales Organization X2E Design Group

E-Mail: [email protected]

[email protected]

[email protected]

WWW: http://www.x2e.de

All rights reserved

SPYDERTM: Trademark of X2E

Copyright 2001, X2E Designer Group

Disclaimer

The ’SpyderTM System’ is a product of research at the university. It is sold by the University ofTübingen, Germany and therfore the ’general rules and conditions’ of the University of Tübingenmust be followed. It is prohibited under any circumstances to use ’SpyderTM’ in or with systemswhich could harm peoples health or life in any way.Particularly the following security advice have to be followed:

• It is prohibited to install ’SpyderTM’ in any System which contains importand Data of any kind or which contains hardware components other than standard peripheral components (graphics controller, ethernet etc.). The University of Tübingen disclames any liability for lost Data or damaged components.

• A seperate PC, which is not allowed to be connected to an intranet or the internet, has to be provided to run ’SpyderTM’.

• Only trained staff are allowed to use ’SpyderTM’.

• The University of Tübingen disclaims all liability for emulation results aquired through ’SpyderTM’.

University Tübingen

Technische InformatikProf. Dr. W. RosenstielSand 1372076 TübingenGermany

X2E

Brehmstraße 7176870 KandelGermany

User Manual SPYDER-VIRTEX-X2 Rev. 1.11 3 of 73

Table of Contents

1 Introduction 71.1 About This Manual ............................................................................ 71.2 Key Features ...................................................................................... 71.3 Customized Configuration Options ................................................... 71.4 Revision History ................................................................................ 81.5 Terminology and Conventions........................................................... 81.6 Documentation and References ......................................................... 8

2 Hardware Description 92.1 Objectives .......................................................................................... 92.2 Functionality and Structure.............................................................. 102.3 Power Supply ................................................................................... 122.4 Special Purpose Signals ................................................................... 14

2.4.1 FPGA Reset ................................................................................... 142.4.2 Local Bus Arbiter Reset ................................................................ 152.4.3 Clock Signals................................................................................. 15

2.5 PCI Interface .................................................................................... 162.5.1 Initialization of PCI Bus Adapter PCI9080................................... 172.5.2 Address Spaces for PCI Accesses ................................................. 182.5.3 Board Local Bus ............................................................................ 192.5.4 Re-configuration of the XC95144XL CPLD ................................ 212.5.5 DMA and Data Parity Lines of PCI9080 ...................................... 22

2.6 Board Memory Facilities ................................................................. 232.7 Stand-Alone Operation Mode .......................................................... 292.8 Hardware Expansion Facilities ........................................................ 29

3 Test and Design Validation Facilities 353.1 LED Indication of Board Operating ................................................ 353.2 Front-Bracket with LEDs, Buttons and BNC Connector................. 363.3 Voltage Measurement Test Points ................................................... 363.4 Trigger Input .................................................................................... 383.5 Power Consumption Measurement Test Point................................. 383.6 Logic Analyzer Connectors ............................................................. 38

4 Configuration of the Virtex FPGA 444.1 Configuration through PCI Bus ....................................................... 444.2 Configuration through FPGA JTAG Interface ................................ 454.3 Configuration from the parallel PROMs XC18V0x ....................... 46

5 Board Service Software 47

6 Board Installation 51

4 of 73 User Manual SPYDER-VIRTEX-X2 Rev. 1.11

7 Demonstration Designs of Board Operating 527.1 Blinker.............................................................................................. 527.2 SSRAM Test .................................................................................... 537.3 Multiplier ......................................................................................... 547.4 FPGA Power Consumption Test...................................................... 54

Appendix A Blinker Demo Source Code ............................................. 56

Appendix B SSRAM Test Demo Source Code Files ........................... 57

Appendix C Multiplier Demonstration Program.................................. 65

Appendix D Power Test Source Code Files ......................................... 69


Figures

Figure 1: Block Diagram of the Spyder-Virtex-X2 Board............. 9

Figure 2: Layout of the Board ........................................................ 11

Figure 3: Power Supply Components on the Board..................... 13

Figure 4: Jumpers X8-X15.............................................................. 13

Figure 5: Reset Control Scheme..................................................... 14

Figure 6: Clock Signals Scheme ..................................................... 15

Figure 7: Board Local Bus.............................................................. 20

Figure 8: CPLD Re-Configuration Connector ............................. 22

Figure 9: DMA and Data Parity Signals Connector .................... 22

Figure 10: Memory (SSRAM and SDRAM) Organization ......... 23

Figure 11: Enabling of SSRAM1 and SSRAM2 ........................... 24

Figure 12: Layout and Pin Arrangement of the Extension Headers X1 and X2 ...................................................................... 29

Figure 13: LEDs on the Board........................................................ 35

Figure 14: Front-Bracket with LEDs and Buttons....................... 36

Figure 15: Connector X16............................................................... 36

Figure 16: Power Measurement Test Points ................................. 37

Figure 17: Pin Allocation Diagram of the Mictor Connectors .... 38

Figure 18: FPGA JTAG Connector ............................................... 45

Figure 19: PROM JTAG Connector.............................................. 46


Tables

Table 1: Virtex FPGA Dedicated Clock Inputs ................................ 16

Table 2: PCI9080 Serial EEROM Load Registers Values............... 17

Table 3: Configuration of Space 0...................................................... 18

Table 4: Configuration of Space 1...................................................... 18

Table 5: Local Bus FPGA Pin Arrangement .................................... 21

Table 6: Pin Allocation of X28............................................................ 22


Table 8: Pin Arrangement of the RAM Bus 1 Data Signals ............ 25

Table 9: Pin Arrangement of the RAM Bus 1 Address and Control Signals...................................................................................... 26

Table 10: Pin Arrangement of the RAM Bus 2 Data Signals .......... 27

Table 11: Pin Arrangement of the RAM Bus 2 Address and Control Signals...................................................................................... 28

Table 12: Pin Arrangement of the Extension Bus Header X1......... 29

Table 13: Pin Arrangement of the Extension Bus Header X2......... 32

Table 14: Pin Allocation of X16.......................................................... 36

Table 15: Mictor Connector U11 ....................................................... 39










Table 25: Pin Allocation of X27.......................................................... 46


1 Introduction

1.1 About This ManualThis manual provides detailed design information on the SPYDER-VIRTEX-X2 Board and itsusage for development and validation of hardware applications. Please refer to our WWW-sitehttp://www.fzi.de/sim/spyder.html to check for the updates and product modifications. We willbe obliged for any feed-back.The SPYDER-VIRTEX-X2 Board is conceptualized for rapid cost-effective development of digitalhardware in a PCI based environment and stand-alone applications. Emulation of the digitalhardware for ASIC-design, fast prototyping of the embedded systems, development of PC add-in cards with reconfigurable hardware resources are its main application areas. The Board hasbeen optimized for high performance and high utilization of the Xilinx Virtex FPGA resources.Easy to use, it supports the innovative hardware-development approaches, based on the usage ofmodern design tools. This allows the designer to develop, modify and test new products in shorttime frame, achieving their high-quality characteristics.

1.2 Key FeaturesThe SPYDER-VIRTEX-X2 Board has the following features:

• Fully PCI Ver. 2.1 compliant 32 bit, 33 MHz PCI Bus interface (with PLX PCI9080 PCI Accelerator)

• Xilinx Virtex-Series FPGA devices: XCV300 or XCV800• System gate range: 300.000 or 800.000 equivalent logic gates• System clock up to 40Mhz• 32 bit address / 32 bit data local bus, controlled by an arbiter implemented in Xilinx

CPLD XC95144XL• 2 separate up to 8Mbit (256k x 32 each) Synchronous burst SRAMs (Note: the Board can

be supplied with the devices, as described in following section; please check the actual RAM device on the Board)

• 2 separate Synchronous DRAM Banks (4MB x 32 each) (Note: the Board can be supplied with the devices, as described in following section; please check the actual RAM device on the Board)

• Functionality Modes:• PCI based (as add-in card in PCI slot)• Stand-alone mode for autonomous applications

• FPGA configuration capabilities:• PC based (via PCI Bus)• Through external FPGA JTAG interface• Internally from the in-system programmable cascaded FPGA configuration PROMs XC18V0x (capacity up to 2 x 4 Mbit)

• 172 external I/Os for system hardware expansion via two VG96 headers• Compartible with the SPYDER-CORE-P2/SH3 Microprocessor Board via the Back-Plane• IEEE 1149.1-compartible boundary scan (JTAG) test support• Power supply:

• From PCI Bus (12V, 5V)• Through external connecter (12V, 5V)

• Power-on reset generation• LEDs for test and configuration indication• 9 logic analyzer connectors (of Mictor type) for examination of the Board internal signals• External trigger signal input for design validation• Software support under Windows NT 4.0

1.3 Customized Configuration OptionsThe following features of the SPYDER-VIRTEX-X2 Board are directly customised by the user:

• Xilinx Virtex-Series FPGA devices:• XCV300 (300.000 equivalent logic gates)• XCV800 (800.000 equivalent logic gates)


• Synchronous burst SRAM devices of:• Micron:

• MT58LC32K32 (32k x 32)• MT58LC64K32 (64k x 32)• MT58L128L32F (128k x 32)• MT58L256L32F (256k x 32)

• Synchronous DRAM (SDRAM) devices of:• Micron:

• MT48LC4M16A2TG-16E (4Mx16)• Siemens:

• HYB39S64160BT (4M x 16)• SPYDER-CORE-P2/SH3 Microprocessor Board (Hitachi SH7709A or 7729-DSP)• Back-Plane for connection with the SPYDER-CORE-P2/SH3 Board

1.4 Revision History• December 24, 1999: Version 1.1• July 31, 2000: Version 1.11 :

• Board re-design:• Board clock scheme has been modified;• Board reset control schema has been modified;• FPGA configuration facility over FPGA JTAG interface has been added;• FPGA configuration facility over parallel port has been removed;• Extension headers have been modified;• SRAM/SDRAMs have been modified;• Micor connectors have been modified;

1.5 Terminology and ConventionsIn this User’s Manual we will use the short term Board instead of the long name SPYDER-VIRTEX-X2 Board.References to Windows NT assume Windows NT 4.0 or higher.The term PCI will denotate the PCI Local Bus specified by the Revision 2.1.We will use the bold style in text to describe the most important information and the actionsthat must or can be executed by the customer during the installation and operation of theBoard.

1.6 Documentation and References• SPYDER-VIRTEX-X2 Board Data Sheets and User‘s Manual, WWW-site: http://

www.fzi.de/sim/spyder.html• XILINX Virtex FPGAs Data Sheets, WWW-site: http://www.xilinx.com/partinfo/data-

book.htm#virtex• Xilinx development tools: Alliance Series, WWW-site: http://www.xilinx.com/products/

alliance.htm• Xilinx development tools: Foundation Series, WWW-site: http://www.xilinx.com/prod-

ucts/found.htm • PCI Local Bus Specification 2.1, PCI Special Interest Group• PLX PCI9080 Data Book, WWW-site: http://www.plxtech.com/• PLX PCI SDK, User’s Manual, WWW-site: http://www.plxtech.com/• SPYDER-CORE-P2 Board Data Sheets and User‘s Manual, WWW-site: http://www.fzi.de/

sim/spyder.html• Micron SSRAM and SDRAM Data Sheets, WWW-Site: http://www.micron.com/mti/

msp/html/datasheet.html• Siemens SDRAM Data Sheet, WWW-Site: http://www.infineon.com/products/memory/

syndram/313r.htm


2 Hardware Description

2.1 ObjectivesSPYDER-VIRTEX-X2 is a prototyping board for the wider class of hardware applications based onthe usage of the programmable resources of the Virtex FPGA devices of Xilinx. It was originallyconceptualized as one of two basic parts of the Integrated Design Environment for EmbeddedSystems mainly used in the areas of industrial automation and communication. The second partof the Design Environment, the microcontroller-based SPYDER-CORE-P2/SH3 board, addressesthe development of the embedded software. Refer the SPYDER-CORE-P2/SH3 Data Sheets andUser’s Manual for its detailed description.The main objective of the development of the SPYDER-VIRTEX-X2 Board was the creation of thebest conditions for electrical engineers for rapid design and prototyping of the wider class ofadvanced digital systems. This aim comprises the following purposes:

• the Board must produce the comfortable and complete frame for a system under develop-ment, support the entire design process, release the engineer in large extend from expen-sive and time consuming electrical design and manufacturing, helping to focus her attention on the elaboration of the key design features;

• the Board must enable the optimal usage of the configurable resources of the Virtex FPGA;

• its architecture must be flexible enough, making it an universal tool for system develop-ment;

• the Board must have efficient communication facilities, enabling on the one hand easy extendability of its hardware resources and on the other - an efficient support of the data exchange with the microcontroller- and PC-based environment;

• the Board must enable easy and rapid design and configuration of its programmable resources;

• it must support the easy and reliable validation of the hardware under development, assist-ing in electrical measurements and evaluation of the achieved parameters and characteris-tics of the design.

PCI Bus

PCI 9080

CPLD

XC95144 FPGA

Bus Arbiter

SSRAM 2256k x 32

Ext

ensi

on

Arbiter

PCI Bus Local Bus

Virtex

Hea

der

X2

Ext

ensi

on

Hea

der

X1

PC

IC

on

nec

tor

Power Supply

3.3V / 2A

2.5V / 10A

Clock

Control

Configuration

Facilities

FPGA

32-Bit Address / 32-Bit Data

ControlSignals

Extension

Bus EH2

SSRAM 1256k x 32

SDRAM Bank 24M x 32

SDRAM Bank 14M x 32

RA

M B

us

1

RA

M B

us

2

ExtensionBus EH1

(BG 432)

XCV300-XCV800

Figure 1: Block Diagram of the SPYDER-VIRTEX-X2 Board


2.2 Functionality and StructureDeveloped mainly for the embedded system design and validation, the Board can operate in twoprincipally different modes:

• as an add-in PCI Bus-based computer card;• as an stand-alone hardware module.

To take full advantage of the Board features it is recommended to use it in Windows NT basedPC environment, at least during development and debugging process. This will allow to followa smooth design flow in conjunction with Xilinx development tools, using the service anddevelopment software supplied with the Board. In this manner developers can quickly andcomfortably validate and modify their designs, significantly reducing product development time.After finishing debugging the design in PC-based environment the Board can be efficiently usedin stand-alone operation mode for embedded applications.The simplified block diagram of the Board is represented in Figure 1. Its physical layout isdepicted in Figure 2. Every time when you want to know the exact location of the device in


question on the Board, you will be able to find it by means of the supplied schematical diagramand the device label given in brackets in the text.

The core component of the Board is a Xilinx FPGA device from the Virtex family. The physicalBoard design enables the usage of any Virtex FPGA with the package type BG432. The four suchdevices (XCV300, XCV400, XCV600, and XCV800) are available now with the speed grades -6 (fastest), -5 and -4 (slowest), ranging in the density from 300.000 up to 800.000 system gates.The design of the Board allows usage of 303 configurable FPGA I/O pins.

Figure 2: Layout of the Board


Virtex is a static RAM based FPGA device. It can be fast and easy configurated but loses itscontents as far as the power supply is turned off.Please refer to the technical documentation of the Xilinx Virtex family for more information.The Board enables various alternatives for the FPGA configuration which are mostly supportedby the supplied software utilities:

• through the PCI interface;• from the on-board parallel PROMs;• through the FPGA JTAG interface, using the Xilinx Download Cable.

This allows the engineer to choose the most suitable configuration mode in each concrete case.The Board contains two synchronous static RAMs (SSRAM) with the organisation up to 256k x32 each and two synchronous DRAMs (SDRAM) banks (4M x 32 each) that can be accessedthrough the two separate RAM busses (18-bit address/32-bit data).Two 96-pins connectors (Extension Headers X1 and X2) enable expansion of the hardware underemulation on the Board through two 86 lines wide busses. One of them is connected to the RAMBus 2, making the corresponding RAM devices accessible from the external hardware.The Board has separate 32-bit address and data lines Local Bus. The Xilinx XC95144XL CPLDoperates as a Local Bus Arbiter, controlling its functionality. The PCI Bus Adapter PCI9080performs data transfer between the PCI Bus and the Board Local Bus, supporting thecommunication modes in accordance with the PCI Specification 2.1.The customer can choose among various power supply schemes and clock generation modes,enabling synchronous or/and asynchronous design functionality relating PCI bus clock signal.The Board provides rich test and design validation facilities, including on-board indicationLEDs, internal test points, logic analyzer connectors, trigger signal input.See the following sections for details about the design and functionality of the Board.

2.3 Power SupplyThe Board is designed to operate in 5V signalling environment (PCI Bus as well as Local Bus).For the customer it is not visible, that it contains complex electronic devices compliant withvarious power supply norms (5V, 3.3V and 2.5V). The voltage levels of 2.5V and 3.3V aregenerated internally on the Board by the voltage converters MMC5030 (U9) and LT1085CT/T0220 (J4) respectively.To enable a wider application field and to optimize operational characteristics of the Board, aflexible and easy to change power supply scheme has been developed.As an add-in PCI card the Board is implicitly connected to the PCI power supply lines.In the stand-alone mode it is necessary to provide the external power supply 5V and 12Vthrough the connector PSW5 (U19). You must also manually change the position of thejumper X3 according to the diagram in Figure 3. This jumper ensures, that the PCI andexternal power supply sources can not be connected to the Board simultaneously.The fuse SI1 (maximal value: 5 Ampere) is provided to protect the Board and the externalhardware components from occasional damaging.To ensure the correct power supply for all devices on the Board the customer should also checkthe presence of the jumpers X24 and X25 (they must be set) which are needed to enable the


measurements of the Board power consumption. This issue is discussed in detail in the section3.3.

When connecting external hardware through the extension headers X1 or X2, you must take careto avoid applying voltage simultaneously on the both sides of the connectors power supply pins.If you intend to implement the separate power supply for the external hardware (for all or someof the voltages 12V, 5V, 3.3V and 2.5V), you should remove the correspondent jumpers X8,X9, X10, X11 for the extension header X1 and the X12, X13, X14, X15 for the extensionheader X2 (see Fig. 4). These jumpers are initially not present on the Board (their contacts aredisconnected). If you want to supply the external hardware from the voltage sources of the Board,the corresponding jumpers must be inserted.

External

Power Supply

123

though PCI

Power Supply

123

Jumper X3

Fuse SI1 (5 Ampere)

Power Supply Connector PSW5

Jumper X24 for Current Measurement (3.3V)

Jumper X25 for Current Measurement (2.5V)

3.3V Voltage Converter LT1085CT/T0220

2.5V Voltage Converter MMC5030

Figure 3: Power Supply Components on the Board

Figure 4: Jumpers X8-X15

X12X13X11X10X9 X8 X15 X14

with jumper without jumper


2.4 Special Purpose SignalsThis section describes the reset and clock signals on the Board, which enable easy and flexiblecontrol of the design under emulation in stand-alone mode as well through the PCI interface.

2.4.1 FPGA ResetFigure 5 represents the reset control scheme of the Board. The reset mode for the design under

emulation on the Board is activated and propagated through the low active signalGNET2_GRESET_0. This signal is generated by the CPLD device (D3) and activated in one ofthe following ways:

• on power-on. The line HARDRESET_0 is set low from the MAX821 (U29) until VCC (+3.3V) voltage on the Board reached the threshold (3.08V) and remains low for 1ms after VCC rises above this level;

• on power-down. The line is de-asserted, when VCC falls below the threshold, and stays low before VCC drops below 1V. This guarantees the correct hardware behaviour, when the Board is shut down;

• when Reset button (U2) is pushed on the Board. The switch is effectively debounced, the MAX821 (U28) is generating a minimum 1ms long reset pulse;

• when utility reset.exe is executed, setting bit 0 (GNET2) of Local Bus Arbiter XC95144XL Command/Status Register (Local address: 7);

• when the GNET1 external reset signal (A2 pin of the Expansion Headers X1 and X2) is asserted low;

• when the local reset out signal LRESETo_0 is asserted from the PCI Bus Arbiter PLX9080.

As you can see above, the reset condition on the Board can be also programmable activated bythe host computer, setting GNET2 bit of the Board Command/Status Register high. When set,GNET2 bit asserts XC95144XL output signal GNET2_GRESET_0 low.GNET2_GRESET_0 is connected to the FPGA pin D6, so enabling initialization of the FPGAdesign and propagated though the Expansion Headers X1 and X2 to the external hardware.FPGA Reset LED (U40-B) (Fig. 13) reflects the current state of the signal GNET2_GRESET_0.Button Reset LED (J3) reflects the current state of the signal BUTTON_RESET_0.Power-on Reset LED (U38-B) reflects the current state of the signal HARDRESET_0.

Figure 5: Reset Control Scheme

Virtex

CPLD

XC95144

Arbiter

HARDRESET_0

GNET1_0

ButtonReset

Local Bus

GNET2_GRESET_0

ResetGenerator

Ext

ensi

on

Hea

der

X1

A2

FPGA

PCI-Bus

PLX9080

ArbiterReset

Command

MAX821

(reset.exe)GNET2

Ext

ensi

on

Hea

der

X2

A2

B2

B2

D6

Power-on

MAX821

Reset

GNET1_0

GNET2

HARDRESET_0

GNET1_0

BUTTON_RESET_0

LRESETO_0

LRESETo_0


2.4.2 Local Bus Arbiter ResetGNET2_GRESET_0 signal causes only the reset mode in the FPGA design, but it is not intendedto issue reset of the Local Bus Arbiter and the PCI Bus Adapter. On the other hand, the Local BusArbiter CPLD (and the PCI Bus Adapter PCI9080) can be initialized without activating Resetstate in the FPGA design.The Local Bus is inialized, when the output signal LRESETo_0 of the PCI Bus Adapter PCI9080is activated. This occurs in one of the following ways:

• when PCI Bus Reset (low active signal RST_0) is activated. This causes all PCI bus out-puts to float, resets the entire PCI9080 device and issues the local reset signal (LRESETo_0);

• by setting PCI Adapter Software Reset Bit of Init Control Register (CNTRL[30]). This action resets the PCI9080 Local Configuration and Local DMA registers, but does not reset its PCI Configuration and Shared Runtime registers. PCI9080 continues to respond to PCI accesses in this state. The Local Bus remains reset until this bit is cleared from PCI host;

• when LRESETi_0 is asserted by the Local Bus Arbiter CPLD. (Note: This is not imple-mented in the current version of the Board)

LED_0 output of the Local Bus Arbiter XC95144XL is activated, causing burning of the CPLDLED 0 (J15), when one of the reset signals HARDRESET_0, GNET2 or LRESETo_0 is active.FPGA Reset LED (U40-B), on the other hand, indicates only the current state of the signalGNET2_GRESET_0.

2.4.3 Clock SignalsFigure 6 represents the clock signals generation and propagation scheme.

When using as the add-in card, the Board Local Bus operates asynchronously relating to the PCIclock signal. The internal quartz oscillator signal SYS_CLK is used as Local Bus clock. Youmust check the presence of the quartz oscillator device (G1) in the socket on the Board and itsnominal frequency. The Board is normally supplied with the 33MHz quartz oscillator device.You can easily change it up to 40MHz, if necessary.The Virtex FPGA contains four special input pins which are connected to the dedicated globaldistribution nets, enabling high-fanout clock propagation in the device with minimal skew. All

Figure 6: Clock Signals Scheme

PCI-Bus

PLX9080 VirtexCPLD

XC95144

Arbiter

RAM1_CLK

WDCLK

SYS_CLK

Local Bus

Arbiter

FPGA

Ext

ensi

on

Hea

der

X1

B30

AL16

A16

D17

AK16

A4

SDRAM Bank 14M x 32

SDRAM Bank 24M x 32

SSRAM 1256k x 32

SSRAM 2256k x 32

RAM1_CLK

SYS_CLKQuartz

OscillatorG1

AJ30RAM2_CLK

RAM1_CLK

RAM2_CLK

RAM2_CLK

QuartzOscillator

Q1

USER_CLK

74125U4

S1-8

USER_CLK_OE_


these high-speed clock inputs (GCLK0, GCLK1, GCLK2, GCLK3) are connected to the mainclock sources of the Board, providing the best performance characteristics of the design underimplementation, if these clock signals will be used. The designer can use any subset of thededicated clock signals in their design. Table 1 represents the necessary information for theirusage the Board environment.

The SYS_CLK signal or the USER_CLK signal are the main clock sources for the FPGA design.To secure the minimal skew of the Board system clock, when using memory on the Board or theextention hardware, the RAM1_CLK signal and the RAM2_CLK signals are provided. Theymust be generated by the FPGA design and they are connected to the clock inputs of the memorydevices and to the dedicated FPGA inputs AK16 and A16.The optional hardware can generate its own clock signal. It can be transmitted to the Boardthrough the Extension Heades X1 and used in the FPGA design (WDCLK).

2.5 PCI InterfaceThis section describes the realization and functionality of the Board control and data transferthrough its PCI Interface. This is performed on the Board by the PCI9080 PCI Bus Adapter whichsupports the communication modes in accordance with the PCI Specification 2.1. Refer to thePCI9080 device documentation and the PCI Specification to get the detailed information on thefunctionality of the PCI Adapter and communication through the PCI Bus.Note: The functionality of the PCI9080 PCI Bus Adapter is limited by the current configurationto the modes described in this section. Please refer to the FZI WWW-site to receive up-to-dateinformation on the Board design.The functional features of the Board PCI Bus communication are mainly defined by the designof the Local Bus Arbiter CPLD. The PCI9080 is inialized in accordance with the currentconfiguration of the CPLD and enables flexible program tuning of its functionality. The Local Bus Arbiter XC95144XL defines the C type (32-bit nonmultiplexed address/data) ofthe Board Local Bus. Section 2.5.3 describes the functionality of the Board Local Bus. Refer tothe PCI9080 documentation for more information.The Board currently supports only Direct Slave Operation (accesses to Local Bus from the PCIBus) of the PCI9080 PCI Adapter:

• I/O-Mapped Transfer;• Single Memory-Mapped Transfer.

Two address spaces, Space 0 and Space1, are defined for the Board PCI communication. TheLocal Bus Arbiter control registers lay in Space 0. The customer can normally communicate withthem only by using the supplied software. Through Space1 the accesses to the Virtex FPGA canbe implemented. Section 2.5.2 gives information on the configuration and usage of these addressspaces. Section 3.5.3 represent the Virtex FPGA pin allocation of the Local Bus signals.

Table 1: Virtex FPGA Dedicated Clock Inputs

FPGA (BG432)Pin Name

FPGA (BG432)Pin Number

Signal Name (SPYDER-VIRTEX-X2) Clock Source

GCLK0 AL16 USER_CLK/WDCLK Board User Clock Signal, generated by the Quartz Oscillater Q1 or

WDCLK Clock Siganl from SPY-DER-CORE-P2 Board

GCLK1 AK16 RAM1_CLK Clock Siganl for the SSRAM/SDRAM Bank 1, generated by the

FPGA Pin A4

GCLK2 A16 RAM2_CLK Clock Signal for the SSRAM/SDRAM Bank 2, generated by the

FPGA Pin AJ30

GCLK3 D17 SYS_CLK Board System Clock Signal, gener-ated by the Quartz Osciallator G1


2.5.1 Initialization of PCI Bus Adapter PCI9080 The PCI host or Local Processor can control the PCI9080 operating through its internalConfiguration Registers. The PCI9080 Configuration Registers can be programmed in one of thefollowing ways:

• by the serial EEPROM NM93CS46 (D2). The PCI9080 tries to read the serial EEPROM after PCI reset (This always occurs after power-on of the PCI host.), or when Reload Configuration Registers bit of the Init Control Register (CNTRL[29]) is changed to 1.

• by the Local processor. (Note: this option is not implemented in this version of the Board. The NB_0 PCI9080 input is hard-wired low by the Local Bus Arbiter CPLD.)

The Board makes use of the Extra Long Load Mode for programming PCI9080. Table 2represents the PCI9080 Configuration Registers values that are stored in the EEPROM on theBoard. The EEPROM is organized in 16-bit words. During the initialization phase of its 32-bitConfiguration Registers, the PCI9080 first loads MSW (Most Significant Word; bits [31:16]) andthen LSW (Least Significant Word (LSW; bits [15:0]). In this way the PCI9080 loads 44 16-bitwords sequentially during its configuration process.

Table 2: PCI9080 Serial EEROM Load Registers Values

EEPROM Offset

EEPROM Value Description

0 9080 Device ID

2 10b5 Vendor ID

4 0680 Class Code

6 0003 Class Code, Revision

8 0000 Maximum Latency, Minimum Grant

A 0100 Interrupt Pin, Interrupt Line Routing

C 0000 MSW of Mailbox 0

E 0000 LSW of Mailbox 0

10 0000 MSW of Mailbox 1

12 0000 LSW of Mailbox 1

14 ffff MSW of Range for PCI-to-Local Address Space 0

16 f000 LSW of Range for PCI-to-Local Address Space 0

18 f800 MSW of Local Base Address (Remap) for PCI-to-Local Address Space 0

1A 0001 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 0

1C 0020 MSW of Local Arbitration Register

1E 0000 LSW of Local Arbitration Register

20 0000 MSW of Local Bus Big/Little Endian Descriptor Register

22 0000 MSW of Local Bus Big/Little Endian Descriptor Register

24 0000 MSW of Range for PCI-to-Local Expansion ROM

26 0000 LSW of Range for PCI-to-Local Expansion ROM

28 0000 MSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM

2A 0000 LSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM

2C 4200 MSW of Bus Region Descriptors for PCI-to-Local Accesses

2E 0140 LSW of Bus Region Descriptors for PCI-to-Local Accesses

30 0000 MSW of range for Direct Master to PCI

32 0000 LSW of range for Direct Master to PCI

34 0000 MSW of Local Base Address for Direct Master to PCI Memory

36 0000 LSW of Local Base Address for Direct Master to PCI Memory

38 0000 MSW of Local Bus Address for Direct Master to PCI IO/CFG

3A 0000 LSW of Local Bus Address for Direct Master to PCI IO/CFG


The values of the PCI9080 Configuration Registers that are loaded from the serial EEPROM afterPCI reset can be subsequently changed locally or by the PCI host.Refer to the PCI9080 documentation for more information on its configuration.

2.5.2 Address Spaces for PCI AccessesTwo address spaces, Space 0 and Space1, are defined for the Board PCI communication. Each ofthese address spaces is defined by the following PCI9080 internal Configuration registers:

• Local Address Range;• Local Base Address;• PCI Base Address;• Bus Region Descriptor for PCI-to-Local Accesses.

They are loaded from the serial EEPROM after PCI reset and can be subsequently changedlocally or by the PCI host. Tables 3 and 4 show the current settings of these registers after theinitialization from the serial EEPROM.

The settings in Table 3 define PCI address Space 0 as:• memory-mapped (LAS0RR[0] = 0)• can be located anywhere in the 32-bit PCI address space (LAS0RR[2:1] = 00)

3C 0000 MSW of PCI Base Address (Remap) for Direct Master to PCI

3E 0000 LSW of PCI Base Address (Remap) for Direct Master to PCI

40 0000 MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG

42 0000 LSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG

44 9080 Subsystem ID

46 10b5 Subsystem Vendor ID

48 ffe0 MSW of Range for PCI-to-Local Address Space 1

4A 0000 LSW of Range for PCI-to-Local Address Space 1

4C 0800 MSW of Local Base Address (Remap) for PCI-to-Local Address Space 1

4E 0001 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 1

50 0000 MSW of Bus Region Descriptors (Space 1) for PCI-to-Local accesses

52 0243 LSW of Bus Region Descriptors (Space 1) for PCI-to-Local accesses

54 0000 MSW of PCI Base Address for Local Expansion ROM

56 0040 LSW of PCI Base Address for Local Expansion ROM

EEPROM Offset

EEPROM Value Description

Table 3: Configuration of Space 0

PCI9080 Configuration

Register

Register Setting

EEPROM Offset

PCI Address(Offset form Base

Address)

Address Range (LAS0RR)

FFFFF000h 14h-16h 00h

Local Base Address (Remap)

(LAS0BA)

F8000001h 18h-1Ah 04h

Bus Region Descriptor(LBRD0)

02000000h 2Ch-2Eh 18h

Table 4: Configuration of Space 1

PCI9080 Configuration

Register

Register Setting

EEPROM Offset

PCI Address(Offset form Base

Address)

Address Range (LAS1RR)

FFE00000h 48h-4ah F0h

Local Base Address (Remap)

(LAS1BA)

08000001h 4Ch-4Eh F4h

Bus Region Descriptor(LBRD1)

00000003h 50h-52h F8h


• address range is 4KB (LAS0RR[31:4] = FFFFF00h)• local base address is F8000000h (LAS0BA[31:4] = F800000h)• Local Bus width is 8 bits (LBRD0[1:0] = 00)

Space 1 is defined by Table 4 as:• memory-mapped (LAS1RR[0] = 0)• can be located anywhere in the 32-bit PCI address space (LAS1RR[2:1] = 00)• address range is 2MB (LAS1RR[31:4] = FFE0000h)• local base address is 08000000h (LAS1BA[31:4] = 0800000h)• Local Bus width is 32 bits (LBRD1[1:0] = 11)

Bits LAS0BA[0] = 1 and LAS1BA[1] enable decoding of the PCI address for Direct Slave accessto the spaces 0 and 1 respectively.During the “Plug-and-Play” initialization of the Board by the PCI BIOS software, the PCI9080PCI Base Address Registers PCIBAR2 (PCI address: 18h) and PCIBAR3 (PCI address: 1Ch) areset to define PCI base address for Spaces 0 and 1 respectively.Address Space 0 is reserved for the control registers of the Local Bus Arbiter XC95144XL. Theyare used by the supplied Board service programs that are described in the section 5. Thecustomer’s software is not normally allowed to access Address Space 0.Address Space 1 can be used by the customer’s software for communication with the hardwareimplemented in the Virtex FPGA. Six local address bus lines (LA[31:27]) are used by the LocalBus Arbiter CPLD for decoding PCI accesses to the Virtex FPGA. The FPGA write (FWR_0),read (FRD_0) and FIO_CS_0 control signals are activated by the Local Bus Arbiter during PCIaccesses to the Board if LA(31:27) = 00001. This means that the range for Address Space 1 ofthe Board can be set (by setting PCI9080 register LAS1RR) up to 128M large.

2.5.3 Board Local BusThe Local Bus Arbiter is realized on the base of the Xilinx XC95144XL CPLD. Its design definesthe Local Bus functionality as well as many other basic functionality features of the Board andcan be easy modified in software-like manner. The Local Bus Arbiter is preprogrammed but canbe re-configurated by the customer with the new version of its design, upgrading in such a waythe Board functionality. The up-to-date Local Bus Arbiter CPLD configuration file can bedownloaded from the FZI WWW-site. The configuration of the XC95144XL CPLD is performedthrough its JTAG interface, using the Xilinx development software. Section 2.5.4 describes theXC95144XL CPLD configuration flow.


The block diagram of the Board Local Bus is represented by Figure 7. The XC95144XL Local

Bus Arbiter defines the C type (32-bit nonmultiplexed address/data) of the Local Busfunctionality which supported by the PLX9080 PCI Bus Arbiter. Section 2.5 describes the BoardPCI interface. The Local Bus address and data lines are directly connected to the FPGA device. The Local BusArbiter XC95144XL generates the FPGA access control signals (FIO_CS_0, FRD_0, FWR_0)based the PCI9080 PCI Bus Adapter Local Bus control signals during PCI accesses to theAddress Space 1 (see Section 2.5.2). The FWR_0 (write) signal is issued by the Local BusArbiter when the data are transmitted to the FPGA from the PCI Bus Arbiter. FRD_0 (read)activate data transmittion from the FPGA to to the PCI host. FIO_CS_0 is activated when at leastone of FWR_0 or FRD_0 is active. The transmitted data are sampled with the active front edgeof the SYS_CLK clock signal (see Section 2.4.3).FWAIT_0, F_INT_0 signals can be issued by the Local Bus Arbiter XC95144XL to contol LocalBus FPGA accesses.

Figure 7: Board Local Bus

PC

I Bu

s

Virtex

LD<31:0>

Control Signals

F_INT_0

LA<31:2>, LBE_0<3:0>U13

Logic AnalyzerConnectors

U12

U11

FPGA

PCI-Bus

PLX9080

Arbiter

CPLDXC95144

ArbiterLocal Bus

FWAIT_0

FRD_0

FIO_CS_0

FWR_0


Table 5 represents the FPGA pin allocation for the Local Bus signals.

2.5.4 Re-configuration of the XC95144XL CPLDThe in-system configuration of the XC95144XL CPLD device through the JTAG interface issupported by Xilinx Foundation or Alliance Series Software. Hereby you can use either theXChecker Cable or the Parallel Download Cable of Xilinx. The XChecker Cable can beconnected to the serial port of both workstations and PCs, while the Parallel Download Cablesupports the configuration process only through the PC’s parallel printer port. See XilinxSoftware documentation for more information on configuration of the CPLD devices through theJTAG interface.

Table 5: Local Bus FPGA Pin Arrangement

Data Bus

Local Bus

Signal

FPGA Pin

(BG432)

Mictor Connector

(U12) Pin Name

LD00 B29 ODD_0

LD01 A28 ODD_1

LD02 B28 ODD_2

LD03 C28 ODD_3

LD04 A27 ODD_4

LD05 B27 ODD_5

LD06 C27 ODD_6

LD07 D27 ODD_7

LD08 A26 ODD_8

LD09 C26 ODD_9

LD10 D26 ODD_10

LD11 B25 ODD_11

LD12 C25 ODD_12

LD13 D25 ODD_13

LD14 A24 ODD_14

LD15 B24 ODD_15

LD16 C24 EVEN_0

LD17 D24 EVEN_1

LD18 C23 EVEN_2

LD19 D23 EVEN_3

LD20 A22 EVEN_4

LD21 B22 EVEN_5

LD22 C22 EVEN_6

LD23 D22 EVEN_7

LD24 B21 EVEN_8

LD25 C21 EVEN_9

LD26 A20 EVEN_10

LD27 B20 EVEN_11

LD28 C20 EVEN_12

LD29 D20 EVEN_13

LD30 A19 EVEN_14

LD31 B19 EVEN_15

Address Bus

Local Bus

Signal

FPGA Pin

(BG432)

Mictor Connector

(U13) Pin Name

LA02 D8 ODD_0

LA03 C8 ODD_1

LA04 B8 ODD_2

LA05 A8 ODD_3

LA06 D9 ODD_4

LA07 C9 ODD_5

LA08 B9 ODD_6

LA09 D10 ODD_7

LA10 C10 ODD_8

LA11 B10 ODD_9

LA12 C11 ODD_10

LA13 B11 ODD_11

LA14 D12 ODD_12

LA15 C12 ODD_13

LA16 B12 ODD_14

LA17 A12 ODD_15

LA18 D13 EVEN_0

LA19 C13 EVEN_1

LA20 B13 EVEN_2

LA21 A13 EVEN_3

LA22 D14 EVEN_4

LA23 B14 EVEN_5

LA24 D15 EVEN_6

LA25 C15 EVEN_7

LA26 B15 EVEN_8

LA27 A15 EVEN_9

LA28 C16 EVEN_10

LA29 B16 EVEN_11

LA30 C17 EVEN_12

LA31 B17 EVEN_13

Control Signals

Local BusSignal Name

FPGA Pin (BG432)

Mictor ConnectorPin Name

FIO_CS_0 B7 EVEN_6 (U22)

FWR_0 C6 EVEN_7 (U22)

FRD_0 B6 EVEN_8 (U22)

FWAIT_0 A6 EVEN_9 (U22)

F_INT_0 D7 EVEN_10 (U22)

LBE0_0 D19 EVEN_15 (U13)

LBE1_0 B18 EVEN_14 (U13)

LBE2_0 C18 ODD_12 (U11)

LBE3_0 D18 ODD_13 (U11)


You must have the Board installed either in PCI based or stand-alone mode, as described insection 6, before you can start with this way of configuration.For configuration of the XC95144XL Arbiter you must proceed as follows:

• download the up-to-date version of the Local Bus Arbiter in JEDEC format (pcicpld.jed) from the FZI WWW-site;

• prepare the Xilinx Software and Download Cable for configuration of the XC95144XL;• connect the XChecker or Parallel Download Cable to JTAG connector X28. Figure 8 and

Table 6 show the position of the connector X28 on the Board and its pin allocation. It is recommended to use 5V voltage (pin 7) for XC95144XL configuration;

• execute the configuration process of the CPLD device, using Xilinx software tools. Dur-ing configuration process all LEDs on the Board are switched out. After finishing the configuration, the Xilinx configuration tool informs you, if downloading have been suc-cessful, and the Test LED (J16) on the Board starts burning.

Now XC95144XL device contains the new design version of the Local Bus Arbiter. It isrecommended for fully correct behaviour of the Local Bus Arbiter to turn off the power supplyof the Board and perform its initialization, before using it after CPLD device configuration.

2.5.5 DMA and Data Parity Lines of PCI9080The usage of the PCI9080 DMA and data parity lines by the customer is supported in the Boarddesign by propagation its corresponding signals (DP0-DP3, DREQ0_, DACK0_, DREQ1_,DACK1_) through the connector X17. The location of this connector on the Board and its pinallocation is shown in Figure 9.

Figure 8: CPLD Re-Configuration Connector

1

2

7

8X28

Table 6: Pin Allocation of X28

Signal Name Pin

TCK 1

TDI 2

TDO 3

TMS 4

- 5

GND 6

+5V 7

+3.3V 8

Figure 9: DMA and Data Parity Signals Connector

1

2

7

8

X17


Signal Name Pin

DP0 1

DP1 2

DP2 3

DP3 4

DREQ0_ 5

DREQ1_ 6

DACK0_ 7

DACK1_ 8


2.6 Board Memory FacilitiesA lot of real-life applications need large RAM arrays for their realization. Although Virtex FPGAdevices can efficiently implement relatively large memories (f.e. up to 114,688 bit for XCV800device), it may be not enough for some designs. Realization of larger RAM in the FPGA leads toinefficient usage of its internal resources. For such applications the use of external memorydevices is recommended.The Board contains two types of the memory devices: synchronous static RAMs (SSRAMs) withorganization up to 256k x 32 (for MT58LC256K32) each and two SDRAM banks (4M x 32each). They can be accessed through the separate RAM Busses 1 and 2 (Figure 1). RAM Bus 2is additionally connected to the Extension Header 1. Figure 10 shows a fragment of the BoardBlock Diagram which addresses the functionality of these SSRAMs and SDRAMs.

SSRAM U7 (SSRAM 1) and SDRAM Bank 1 (SDRAM 1) consisting of two SDRAM devices(U23 and U24) with organization 4M x 16 share the RAM Bus 1. RAM Bus 1 has data bus

Virtex FPGA

Exp

ansi

on

Hea

der

1

SSRAM 1 (U7)

256k x 32

XC95144

Arbiter

RA

M1_

A<1

9:02

>R

AM

2_A

<19:

02>

SRAM_EN1

SRAM_EN2

CS95_1

EH1<33:02>

EH1<51:34>

CS95_2

Local Bus

S1-5

S1-6

Co

ntr

ol S

ign

als

Control Signals

SDRAM 1 (U23)

4M x 16RAM1_D<15:0>

RAM1_D<31:16>

Control Signals

BWE1_0<3:2>

BW

E1_

0<3:

0>

BWE1_0<1:0>

SDRAM 1

SDRAM 1 (U24)

4M x 16

RA

M1_

D<3

1:0>

SS

RA

M 1

SDRAM 2

SSRAM 2 (U10)

256k x 32

BW

E2_

0<3:

0>

RA

M2_

D<3

1:0>

SDRAM 2 (U25)

4M x 16

SDRAM 2 (U26)

4M x 16

RAM2_D<15:0>

BWE2_0<1:0>

RAM2_D<31:16>

BWE2_0<3:2>

Co

ntr

ol S

ign

als

SS

RA

M 2

SSCS1

SSCS2SDRAMCS2

SDRAMCS1

EH1<64:61>

EH1<60:52>

EH1<66>

EH1<65>

EH1<75:67>

SS

CS

1

Figure 10: Memory (SSRAM and SDRAM) Organization


RAM1_D<31:0> and address bus RAM1_A<19:2>. It can only be accessed from the VirtexFPGA.SSRAM U10 (SSRAM 2) and the SDRAM Bank 2 (SDRAM 2) consisting of two SDRAMdevices (U25 and U26) with organization 4M x 16 lay on the RAM Bus 2. RAM Bus 2 sharescommon lines with Expansion Bus 1 signals (see Section 2.8). The customer can use thisextension facility for increasing the memory capacity of his design.The RAM devices of the the RAM Bus 1 are controlled by the clock signal RAM1_CLK, theRAM devices of the RAM Bus 2 are controlled by the clock signal RAM2_CLK. Both signalsmust be generated by the Virtex FPGA design. The memory accesses occure synchronously withits rising edge.The separate for the both RAM busses control signals BWE1_0<3:0> and BWE2_0<3:0> (lowactive) generate write enable conditions for the corresponding bytes.The application implemented in the Virtex FPGA must enable the access to the SSRAM1,SSRAM2, SDRAM Bank 1 and SDRAM Bank 2 by asserting signals SSCS1_0, SSCS2_0,SDRAMCS1_0 and SDRAMCS2_0 (all low active) respectively.Before accessing the SSRAMs, they must be additionally enabled by the customer by providingboth of the following requirements. First, the customer must turn on the DIP Switches on theBoard (S1-5 for SSRAM1 and S1-6 for SSRAM2), as showed in Figure 11. Second, the SSRAMsmust be activated from the PCI host computer by executing the supplied utilities sram1en.exe andsram2en.exe. (The SSRAMs devices can be dis-activated by the utilities sram1de.exe andsram2de.exe.) If one of these requirements is not provided, the corresponding SSRAM isdisabled, setting all its outputs in the high impedance state.

The address and data bus as well as the RAM control signals are generated by the Virtex FPGA,leaving the customer free choice for implementation of the memory access algorithm. The

Figure 11: Enabling of SSRAM1 and SSRAM2

8 7 6 5 4 3 2 1

on

S1


connectivity relation between the Virtex FPGA and RAM pins is represented in Tables 8 through11. Table 8(10) describes the data signals pin allocation for RAM Bus 1(2).

Table 8: Pin Arrangement of the RAM Bus 1 Data Signals

Signal Name Virtex FPGA(BG432)

SSRAM 1 (U7)(MT58LC512K32)

SDRAM 1 (U23)(HYB39S64160)

SDRAM 1 (U24)(HYB39S64160)

RAM1_D<00> U3 DQ1 DQ0 -

RAM1_D<01> U1 DQ2 DQ1 -

RAM1_D<02> T3 DQ3 DQ2 -

RAM1_D<03> R3 DQ4 DQ3 -

RAM1_D<04> R1 DQ5 DQ4 -

RAM1_D<05> P2 DQ6 DQ5 -

RAM1_D<06> N3 DQ7 DQ6 -

RAM1_D<07> M4 DQ8 DQ7 -

RAM1_D<08> M2 DQ9 DQ8 -

RAM1_D<09> L3 DQ10 DQ9 -

RAM1_D<10> K1 DQ11 DQ10 -

RAM1_D<11> J3 DQ12 DQ11 -

RAM1_D<12> H4 DQ13 DQ12 -

RAM1_D<13> H2 DQ14 DQ13 -

RAM1_D<14> G4 DQ15 DQ14 -

RAM1_D<15> G2 DQ16 DQ15 -

RAM1_D<16> G3 DQ17 - DQ0

RAM1_D<17> H1 DQ18 - DQ1

RAM1_D<18> H3 DQ19 - DQ2

RAM1_D<19> J2 DQ20 - DQ3

RAM1_D<20> J4 DQ21 - DQ4

RAM1_D<21> L2 DQ22 - DQ5

RAM1_D<22> M1 DQ23 - DQ6

RAM1_D<23> M3 DQ24 - DQ7

RAM1_D<24> N1 DQ25 - DQ8

RAM1_D<25> N4 DQ26 - DQ9

RAM1_D<26> P3 DQ27 - DQ10

RAM1_D<27> R2 DQ28 - DQ11

RAM1_D<28> R4 DQ29 - DQ12

RAM1_D<29> T2 DQ30 - DQ13

RAM1_D<30> U2 DQ31 - DQ14

RAM1_D<31> U4 DQ32 - DQ15


Table 9(11) contains pin connectivity of address and control signals for RAM Bus 1(2).

Table 9: Pin Arrangement of the RAM Bus 1 Address and Control Signals


SSRAM 1 (U7)MT58LC512K32

SDRAM 1 (U23) HYB39S64160

SDRAM 1 (U24)HYB39S64160

Expansion Bus EH1

Signal Name

RAM1_A<02> Y4 A0 A0 A0 -

RAM1_A<03> AA2 A1 A1 A1 -

RAM1_A<04> AA3 A2 A2 A2 -

RAM1_A<05> AB4 A3 A3 A3 -

RAM1_A<06> AC2 A4 A4 A4 -

RAM1_A<07> AC3 A5 A5 A5 -

RAM1_A<08> F4 A6 A6 A6 -

RAM1_A<09> F3 A7 A7 A7 -

RAM1_A<10> E1 A8 A8 A8 -

RAM1_A<11> D2 A9 A9 A9 -

RAM1_A<12> Y3 A10 A10 A10 -

RAM1_A<13> Y2 A11 A11 A11 -

RAM1_A<14> Y1 A12 BA0 BA0 -

RAM1_A<15> W4 A13 BA1 BA1 -

RAM1_A<16> / RASL_0 W3 A14 RAS RAS -

RAM1_A<17> / RDWR_0 W1 A15 WE WE -

RAM1_A<18> / CASLL_0 V3 A16 CAS CAS -

RAM1_A<19> / CKE V2 A17 CKE CKE -

RAM1_CLK A4 / AK16 CLK CLK CLK -

BWE1_0<0> E2 BW1_0 LDQM - -

BWE1_0<1> E3 BW2_0 UDQM - -

BWE1_0<2> E4 BW3_0 - LDQM -

BWE1_0<3> F2 BW4_0 - UDQM -

GW1_0 C30 GW_0 - - EH1_75

SSBWE1_ 0 D30 SSBWE_0 - - EH1_74

ADSP1_ 0 D31 ADSP_0 - - EH1_73

ADSC1_0 E28 ADSC_0 - - EH1_72

SSCE1 E29 CE3 - - EH1_71

SS_SNOOZ1 E30 ZZ - - EH1_70

SSOE1_0 E31 OE_0 - - EH1_69

ADV1_0 F28 ADV_0 - - EH1_68

SSMODE1 F29 MODE - - EH1_67

SDRAMCS1_0 AC4 - CS CS -

SSCS1_0 C5 CE1_0 - - -

CS95_1_0 - CE2_0 - - -


Tables 10 and 11 shows additionally how RAM Bus 2 merges with the EH1 lines, enabling the

extension of the RAM capacity through Extension Header X1.

Table 10: Pin Arrangement of the RAM Bus 2 Data Signals





Expansion Bus EH1

Signal Name

RAM2_D<00> AG28 DQ1 DQ0 - EH1_02

RAM2_D<01> AF31 DQ2 DQ1 - EH1_03

RAM2_D<02> AF30 DQ3 DQ2 - EH1_04

RAM2_D<03> AF29 DQ4 DQ3 - EH1_05

RAM2_D<04> AF28 DQ5 DQ4 - EH1_06

RAM2_D<05> AE30 DQ6 DQ5 - EH1_07

RAM2_D<06> AE28 DQ7 DQ6 - EH1_08

RAM2_D<07> AD31 DQ8 DQ7 - EH1_09

RAM2_D<08> AD30 DQ9 DQ8 - EH1_10

RAM2_D<09> AD29 DQ10 DQ9 - EH1_11

RAM2_D<10> AD28 DQ11 DQ10 - EH1_12

RAM2_D<11> AC30 DQ12 DQ11 - EH1_13

RAM2_D<12> AC29 DQ13 DQ12 - EH1_14

RAM2_D<13> AC28 DQ14 DQ13 - EH1_15

RAM2_D<14> AB31 DQ15 DQ14 - EH1_16

RAM2_D<15> AB29 DQ16 DQ15 - EH1_17

RAM2_D<16> AB28 DQ17 - DQ0 EH1_18

RAM2_D<17> AA30 DQ18 - DQ1 EH1_19

RAM2_D<18> AA29 DQ19 - DQ2 EH1_20

RAM2_D<19> Y31 DQ20 - DQ3 EH1_21

RAM2_D<20> Y30 DQ21 - DQ4 EH1_22

RAM2_D<21> Y29 DQ22 - DQ5 EH1_23

RAM2_D<22> Y28 DQ23 - DQ6 EH1_24

RAM2_D<23> W30 DQ24 - DQ7 EH1_25

RAM2_D<24> W29 DQ25 - DQ8 EH1_26

RAM2_D<25> W28 DQ26 - DQ9 EH1_27

RAM2_D<26> V30 DQ27 - DQ10 EH1_28

RAM2_D<27> V29 DQ28 - DQ11 EH1_29

RAM2_D<28> V28 DQ29 - DQ12 EH1_30

RAM2_D<29> U31 DQ30 - DQ13 EH1_31

RAM2_D<30> U30 DQ31 - DQ14 EH1_32

RAM2_D<31> U29 DQ32 - DQ15 EH1_33


Table 11: Pin Arrangement of the RAM Bus 2 Address and Control Signals



SDRAM 1 (U23) HYB39S64160


Expansion Bus EH1

Signal Name

RAM2_A<02> U28 A0 A0 A0 EH1_34

RAM2_A<03> T30 A1 A1 A1 EH1_35

RAM2_A<04> T31 A2 A2 A2 EH1_36

RAM2_A<05> R31 A3 A3 A3 EH1_37

RAM2_A<06> R30 A4 A4 A4 EH1_38

RAM2_A<07> R29 A5 A5 A5 EH1_39

RAM2_A<08> R28 A6 A6 A6 EH1_40

RAM2_A<09> P30 A7 A7 A7 EH1_41

RAM2_A<10> P29 A8 A8 A8 EH1_42

RAM2_A<11> P28 A9 A9 A9 EH1_43

RAM2_A<12> N31 A10 A10 A10 EH1_44

RAM2_A<13> N30 A11 A11 A11 EH1_45

RAM2_A<14> N28 A12 BA0 BA0 EH1_46

RAM2_A<15> M31 A13 BA1 BA1 EH1_47

RAM2_A<16> / RASL_0 M30 A14 RAS RAS EH1_48

RAM2_A<17> / RDWR_0 M29 A15 WE WE EH1_49

RAM2_A<18> / CASLL_0 M28 A16 CAS CAS EH1_50

RAM2_A<19> / CKE L30 A17 CKE CKE EH1_51

RAM2_CLK AJ30 / A16 CLK CLK CLK -

BWE2<0> H29 BW1_0 LDQM - EH1_61

BWE2<1> H28 BW2_0 UDQM - EH1_62

BWE2<2> G30 BW3_0 - LDQM EH1_63

BWE2<3> G29 BW4_0 - UDQM EH1_64

GW2_0 H30 GW_0 - - EH1_60

SSBWE2_0 H31 SSBWE_0 - - EH1_59

ADSP2_0 J28 ADSP_0 - - EH1_58

ADSC2_0 J29 ADSC_0 - - EH1_57

SSCE2 J30 CE3 - - EH1_56

SS_SNOOZ2 K28 ZZ - - EH1_55

SSOE2_0 K30 OE1_0 - - EH1_54

ADV2_0 K31 ADV_0 - - EH1_53

SSMODE2 L29 MODE - - EH1_52

SDRAMCS2_0 F31 - CS CS EH1_66

SSCS2_0 G28 CE1_0 - EH1_65

CS95_2_ - CE2_0 - - -


2.7 Stand-Alone Operation ModeThe board detects automatically, if it is placed in the PCI-Slot or not. If not, it disables the PCI9080 Adapter, bringing its I/Os in the high-impedance state.In the stand-alone mode it is necessary to provide the external power supply 5V and 12Vthrough the connector PSW5 (U19). You must also manually change the position of thejumper X3 according to the diagram in Figure 3.

2.8 Hardware Expansion FacilitiesIn some cases the hardware resources on the Board can be insufficient to meet offered designrequirements. Some applications may need specific HW resources (f.e. analog parts, etc.) that arenot contained on the Board.For such designs the Board provides design expansion facilities that consist of two ExtensionHeaders X1 (for Extension Bus EH1) and X2 (for Extension Bus EH2) of type VG-96. Their pinarrangement is represented schematically in Figure 12. Composed of 96 electrical contacts, eachof them contains 86 informational lines (EH1<86:1> or EH2<86:1>), 4 ground (GND) pins, 4power supply pins (12V, 5V, 3.3V and 2.5V) and 2 reset signals (GNET1 andGNET2_GRESET_0).

Table 12 and Table 13 show how these extension headers are connected to the internal signals onthe Board. The both tables contain the Board signal names and the pin numbers of the VirtexFPGA, Mictor Connectors to which they are connected. Extension Bus EH1 merges additionallywith the RAM Bus 2, making it accessible from the external hardware.The connection over the Back Plain to the SPYDER-CORE-P2 Board will produce the completeIntegrated Design Environment for Embedded Systems. The signals of the extension busses willreceive a special meaning in this case. One of the columns in the tables contains the names of theSPYDER-CORE-P2 Board signals to which the corresponding lines of the Board are connected.One line at the extension bus 1 (EH1<82>) may be used as clock signal (WDCLK).

Table 12: Pin Arrangement of the Extension Bus Header X1

Pin Number

Extension Bus 1Signal Name

RAM Bus 2Signal Name

Pin Number Virtex/BG432

Pin Number (Mictor Connector)

Signal Name(SPYDER-CORE-P2/

SH3)

A1 GND - - - GND

A2 GNET1_0 - - EVEN_8 (U16) GNET1_0

A3 EH1_02 RAM2_D<00> AG28 ODD_1 (U14) AP00

A4 EH1_05 RAM2_D<03> AF29 ODD_4 (U14) AP01

A5 EH1_08 RAM2_D<06> AE28 ODD_7 (U14) AP02

A6 EH1_11 RAM2_D<09> AD29 ODD_10 (U14) AP03

Figure 12: Layout and Pin Arrangement of the Extension Headers X1 and X2

C32B32A32

TOP VIEW

C1B1A1

C1B1A1

C32B32A32

SIDE VIEW Board

X1 X2


A7 EH1_14 RAM2_D<12> AC29 ODD_13 (U14) AP04

A8 EH1_17 RAM2_D<15> AB29 EVEN_0 (U14) AP05

A9 EH1_20 RAM2_D<18> AA29 EVEN_3 (U14) AP06

A10 EH1_23 RAM2_D<21> Y29 EVEN_6 (U14) AP07

A11 GND - - - GND

A12 EH1_28 RAM2_D<26> V30 EVEN_11 (U14) AP08

A13 EH1_31 RAM2_D<29> U31 EVEN_14 (U14) AP09

A14 EH1_34 RAM2_A<02> U28 ODD_1 (U15) AP10

A15 EH1_37 RAM2_A<05> R31 ODD_4 (U15) AP11

A16 EH1_40 RAM2_A<08> R28 ODD_7 (U15) AP12

A17 EH1_43 RAM2_A<11> P28 ODD_10 (U15) AP13

A18 EH1_46 RAM2_A<14> N28 ODD_13 (U15) AP14

A19 EH1_49 RAM2_A<17>/ RDWR_0

M29 EVEN_0 (U15) AP15

A20 EH1_52 SSMODE2 L29 EVEN_3 (U15) AP16

A21 EH1_55 SS_SNOOZ2 K28 EVEN_6 (U15) AP17

A22 GND - - - GND

A23 EH1_60 GW2_0 H30 EVEN_11 (U15) AP18

A24 EH1_63 BWE2_0<2> G30 EVEN_14 (U15) AP19

A25 EH1_66 SDRAMCS2_0 F31 ODD_1 (U16) AP20

A26 EH1_69 SSOE1_0 (RAM 1) E31 ODD_4 (U16) AP21

A27 EH1_72 ADSC1_0 (RAM 1) E28 ODD_7 (U16) AP22

A28 EH1_75 GW1_0 (RAM 1) C30 ODD_10 (U16) AP23

A29 EH1_78 - AH30 ODD_13 (U16) AP24

A30 EH1_81 - AL28 EVEN_0 (U16) AP25

A31 EH1_84 - AK27 EVEN_2 (U16) DP31

A32 GND - - - GND

B1 +12VF1 - - - +12VF1

B2 GNET2_ GRESET_0

- D6 EVEN_9 (U16) GNET2_ GRESET_0

B3 EH1_03 RAM2_D<01> AF31 ODD_2 (U14) BACK_

B4 EH1_06 RAM2_D<04> AF28 ODD_5 (U14) BREQ_

B5 EH1_09 RAM2_D<07> AD31 ODD_8 (U14) WE0P_

B6 EH1_12 RAM2_D<10> AD28 ODD_11 (U14) WE1P_

B7 EH1_15 RAM2_D<13> AC28 ODD_14 (U14) WE2P_

B8 EH1_18 RAM2_D<16> AB28 EVEN_1 (U14) WE3P_

B9 EH1_21 RAM2_D<19> Y31 EVEN_4 (U14) RDP_

B10 EH1_24 RAM2_D<22> Y28 EVEN_7 (U14) RDWRP_

B11 EH1_26 RAM2_D<24> W29 EVEN_9 (U14) FPGACS_

B12 EH1_29 RAM2_D<27> V29 EVEN_12 (U14) FPGAWAIT_

B13 EH1_32 RAM2_D<30> U30 EVEN_15 (U14) IRQ0

B14 EH1_35 RAM2_A<03> T30 ODD_2 (U15) IRQ1

B15 EH1_38 RAM2_A<06> R30 ODD_5 (U15) CS4_

B16 EH1_41 RAM2_A<09> P30 ODD_8 (U15) CS6_

Pin Number






SH3)


B17 EH1_44 RAM2_A<12> N31 ODD_11 (U15) DREQ0

B18 EH1_47 RAM2_A<15> M31 ODD_14 (U15) DACK0

B19 EH1_50 RAM2_A<18> / CASLL_0

M28 EVEN_1 (U15) DRAK0

B20 EH1_53 ADV2_0 K31 EVEN_4 (U15) DREQ1

B21 EH1_56 SSCE2 J30 EVEN_7 (U15) DACK1

B22 EH1_58 ADSP2_0 J28 EVEN_9 (U15) DRAK1

B23 EH1_61 BWE2_0<0> H29 EVEN_12 (U15) TCLK

B24 EH1_64 BWE2_0<3> G29 EVEN_15 (U15) HEADBUS_A00

B25 EH1_67 SSMODE1 (RAM 1) F29 ODD_2 (U16) HEADBUS_A01

B26 EH1_70 SS_SNOOZ1 (RAM 1) E30 ODD_5 (U16) HEADBUS_A02

B27 EH1_73 ADSP1_0 (RAM 1) D31 ODD_8 (U16) HEADBUS_A03

B28 EH1_76 - AG30 ODD_11 (U16) HEADBUS_A04

B29 EH1_79 - AH31 ODD_14 (U16) CS5P_

B30 USER_CLK/ WDCLK

- AL16 CLK_K (U16) WDCLK1

B31 EH1_85 - AL27 EVEN_3 (U16) DP30

B32 +2.5VF1 - - -- +1.8VF1

C1 +5VF1 - - - +5VF1

C2 EH1_01 - AG29 ODD_0 (U14) DP00

C3 EH1_04 RAM2_D<02> AF30 ODD_3 (U14) DP01

C4 EH1_07 RAM2_D<05> AE30 ODD_6 (U14) DP02

C5 EH1_10 RAM2_D<08> AD30 ODD_9 (U14) DP03

C6 EH1_13 RAM2_D<11> AC30 ODD_12 (U14) DP04

C7 EH1_16 RAM2_D<14> AB31 ODD_15 (U14) DP05

C8 EH1_19 RAM2_D<17> AA30 EVEN_2 (U14) DP06

C9 EH1_22 RAM2_D<20> Y30 EVEN_5 (U14) DP07

C10 EH1_25 RAM2_D<23> W30 EVEN_8 (U14) DP08

C11 EH1_27 RAM2_D<25> W28 EVEN_10 (U14) DP09

C12 EH1_30 RAM2_D<28> V28 EVEN_13 (U14) DP10

C13 EH1_33 RAM2_D<31> U29 ODD_0 (U15) DP11

C14 EH1_36 RAM2_A<04> T31 ODD_3 (U15) DP12

C15 EH1_39 RAM2_A<07> R29 ODD_6 (U15) DP13

C16 EH1_42 RAM2_A<10> P29 ODD_9 (U15) DP14

C17 EH1_45 RAM2_A<13> N30 ODD_12 (U15) DP15

C18 EH1_48 RAM2_A<16> / RASL_0

M30 ODD_15 (U15) DP16

C19 EH1_51 RAM2_A<19> / CKE L30 EVEN_2 (U15) DP17

C20 EH1_54 SSOE2_0 K30 EVEN_5 (U15) DP18

C21 EH1_57 ADSC2_0 J29 EVEN_8 (U15) DP19

C22 EH1_59 SSBWE2_0 H31 EVEN_10 (U15) DP20

C23 EH1_62 BWE2_0<1> H28 EVEN_13 (U15) DP21

Pin Number






SH3)


Table 13: Pin Arrangement of the Extension Bus Header X2

C24 EH1_65 SSCS2_0 G28 ODD_0 (U16) DP22

C25 EH1_68 ADV1 (RAM 1) F28 ODD_3 (U16) DP23

C26 EH1_71 SSCE1 (RAM 1) E29 ODD_6 (U16) DP24

C27 EH1_74 SSBWE1_0 D30 ODD_9 (U16) DP25

C28 EH1_77 - AG31 ODD_12 (U16) DP26

C29 EH1_80 - AK28 ODD_15 (U16) DP27

C30 EH1_83 - AJ27 EVEN_1 (U16) DP28

C31 EH1_86 - AH26 EVEN_4 (U16) DP29

C32 +3.3VF1 - - - +3.3VF1

Pin Number Signal Name


Signal Name(Mictor Connectors)

Signal Name(SPYDER-CORE-P2/SH3)

A1 GND - - GND

A2 GNET1_0 - EVEN_11 (U22) GNET1_0

A3 EH2_02 AK26 ODD_1 (U17) STATUS0/PTJ6

A4 EH2_05 AJ25 ODD_4 (U17) STATUS1/PTJ7

A5 EH2_08 AK24 ODD_7 (U17) CA

A6 EH2_11 AJ23 ODD_10 (U17) IRQ2

A7 EH2_14 AJ22 ODD_13 (U17) IRQ3

A8 EH2_17 AK21 EVEN_0 (U17) IRQ4

A9 EH2_20 AK20 EVEN_3 (U17) IRQOUT

A10 EH2_23 AJ19 EVEN_6 (U17) NMI

A11 GND - - GND

A12 EH2_28 AH17 EVEN_11 (U17) IO00

A13 EH2_31 AL17 EVEN_14 (U17) IO01

A14 EH2_34 AK15 ODD_1 (U18) IO02

A15 EH2_37 AJ14 ODD_4 (U18) IO03

A16 EH2_40 AJ13 ODD_7 (U18) IO04

A17 EH2_43 AJ12 ODD_10 (U18) IO05

A18 EH2_46 AJ11 ODD_13 (U18) IO06

A19 EH2_49 AK10 EVEN_0 (U18) IO07

A20 EH2_52 AJ9 EVEN_3 (U18) IO08

A21 EH2_55 AK8 EVEN_6 (U18) IO09

A22 GND - - GND

A23 EH2_60 AH6 EVEN_11 (U18) CE2B

A24 EH2_63 AL6 EVEN_14 (U18) CE2A

A25 EH2_66 AK5 ODD_1 (U22) IOIS16

A26 EH2_69 AK4 ODD_4 (U22) RESETOUT

A27 EH2_72 AH2 ODD_7 (U22) WAKEUP

A28 EH2_75 AG2 ODD_10 (U22) ADTRG

Pin Number






SH3)


A29 EH2_78 AF3 ODD_13 (U22) BS_0

A30 EH2_81 AE3 EVEN_0 (U22) WAIT_0

A31 EH2_84 AD3 EVEN_3 (U22) RAS3L_0

A32 GND - - GND

B1 +12VF2 - - +12VF1

B2 GNET2_GRESET_0 D6 EVEN_12 (U22) GNET2_GRESET_

B3 EH2_03 AL26 ODD_2 (U17) RXD0

B4 EH2_06 AK25 ODD_5 (U17) TXD0

B5 EH2_09 AL24 ODD_8 (U17) SCK0

B6 EH2_12 AK23 ODD_11 (U17) RXD1

B7 EH2_15 AL22 ODD_14 (U17) TXD1

B8 EH2_18 AH20 EVEN_1 (U17) SCK1

B9 EH2_21 AL20 EVEN_4 (U17) CS3_0

B10 EH2_24 AL19 EVEN_7 (U17) -

B11 EH2_26 AJ18 EVEN_9 (U17) -

B12 EH2_29 AJ17 EVEN_12 (U17) -

B13 EH2_32 AH15 EVEN_15 (U17) -

B14 EH2_35 AL15 ODD_2 (U18) -

B15 EH2_38 AK14 ODD_5 (U18) -

B16 EH2_41 AL13 ODD_8 (U18) -

B17 EH2_44 AK12 ODD_11 (U18) -

B18 EH2_47 AK11 ODD_14 (U18) -

B19 EH2_50 AL10 EVEN_1 (U18) -

B20 EH2_53 AK9 EVEN_4 (U18) -

B21 EH2_56 AL8 EVEN_7 (U18) -

B22 EH2_58 AJ7 EVEN_9 (U18) -

B23 EH2_61 AJ6 EVEN_12 (U18) CASHH_0

B24 EH2_64 AH5 EVEN_15 (U18) CASHL_0

B25 EH2_67 AL5 ODD_2 (U22) CASLH_0

B26 EH2_70 AL4 ODD_5 (U22) CAS2H_0

B27 EH2_73 AH1 ODD_8 (U22) RAS3U_0

B28 EH2_76 AG1 ODD_11 (U22) RAS2U_0

B29 EH2_79 AF2 ODD_14 (U22) CAS2L_0

B30 EH2_82 AE2 EVEN_1 (U22) WDCLK

B31 EH2_85 AD2 EVEN_4 (U22) RAS3U_0

B32 +2.5VF2 - - +1.8VF1

C1 +5VF2 - - +5VF1

C2 EH2_01 AJ26 ODD_0 (U17) -

C3 EH2_04 AH25 ODD_3 (U17) -

C4 EH2_07 AJ24 ODD_6 (U17) -

C5 EH2_10 AH23 ODD_9 (U17) -

C6 EH2_13 AH22 ODD_12 (U17) -

C7 EH2_16 AJ21 ODD_15 (U17) -






When connecting the external hardware through the extension headers X1 or X2, you must takecare to avoid simultaneously applying the voltages on the both sides of the connectors. If you arewilling to implement the separate power supply for the external hardware (for all or some of thevoltages 12V, 5V, 3.3V and 2.5V), you should remove the correspondent jumpers X8, X9,X10, X11 (for the extension header X1) and the X12, X13, X14, X15 (for the extensionheader X2). See Figure 3 to find their location on the Board. These jumpers are initially notplaced on the Board (their contacts are disconnected). If you intend to supply the externalhardware from the voltage sources of the Board, the corresponding jumpers must be inserted.

C8 EH2_19 AJ20 EVEN_2 (U17) -

C9 EH2_22 AH19 EVEN_5 (U17) -

C10 EH2_25 AH18 EVEN_8 (U17) -

C11 EH2_27 AK18 EVEN_10 (U17) -

C12 EH2_30 AK17 EVEN_13 (U17) -

C13 EH2_33 AJ15 ODD_0 (U18) -

C14 EH2_36 AH14 ODD_3 (U18) -

C15 EH2_39 AH13 ODD_6 (U18) -

C16 EH2_42 AH12 ODD_9 (U18) -

C17 EH2_45 AL12 ODD_12 (U18) -

C18 EH2_48 AH10 ODD_15 (U18) -

C19 EH2_51 AH9 EVEN_2 (U18) -

C20 EH2_54 AJ8 EVEN_5 (U18) -

C21 EH2_57 AH7 EVEN_8 (U18) -

C22 EH2_59 AK7 EVEN_10 (U18) -

C23 EH2_62 AK6 EVEN_13 (U18) AN07

C24 EH2_65 AJ5 ODD_0 (U22) AN06

C25 EH2_68 AJ4 ODD_3 (U22) AN05

C26 EH2_71 AK3 ODD_6 (U22) AN04

C27 EH2_74 AG3 ODD_9 (U22) AN03

C28 EH2_77 AF4 ODD_12 (U22) AN02

C29 EH2_80 AE4 ODD_15 (U22) AN01

C30 EH2_83 AD4 EVEN_2 (U22) AN00

C31 EH2_86 AD1 EVEN_5 (U22) AVCC

C32 +3.3VF2 - - +3.3VF1






3 Test and Design Validation FacilitiesThe Board has at customer’s disposal various means to perform testing of the Board hardwareresources as well as to validate the design under prototyping:

• Board status LEDs;• voltage measurement test points;• trigger input;• logic analyzer connectors.

The following sections describe these facilities.

3.1 LED Indication of Board OperatingThe Board status LEDs represent a simple, but very helpful facility for indication of the Boardoperating. Their location is depicted by Figure 13.

The green power LED (J5) turned on indicates that the power is applied to the Board. This is thefirst visual sign of the Board correct behaviour. Green Test LEDs (J16 and U40-A) turned onindicate that the Board is in the PCI based mode and Local Bus Arbiter XC95144XL operatesnormally.Four red LEDs, button reset LED (J3), power-up reset LED (U38-B), CPLD LED0 (J15) andboard reset LED (U40-B) indicate the reset status of the Board. The board reset LED (U40-B) isturned on, when the GNET2_GRESET_ signal is active. When the board reset button is pushedthe button reset LED (J3) is turned on. Red CPLD LED0 indicates additionally the activation ofthe signal LRESETo_0 by the PCI Bus Adapter PCI9080 and the activation of the GNET2 sig-nal.The red turned on Done LEDs (J19 and U39-B) indicate the running FPGA Configurationprocess. After the completion of the FPGA configuration, the Done LEDs are turned off.Yellow/green FPGA LEDs (J18 and U39-A) and green FPGA LEDs (J7 and U38-A) can be usedby the customer to indicate status of the design under development. To turn them on the

CPLD LED0 (J15, Red)

CPLD LED1 (J17, Green)

FPGA LED0 (J18, Yellow)Button-Reset LED (J3, Red)Done LED (J19, Red)

Test LED (J16, Green)

Power LED (J5, Green)

FPGA LED1 (J7, Red)

Figure 13: LEDs on the Board


application must assert (by the low active level) FPGA_LED_0 (J18 and U39-A) orFPGA_LED_1 (J7 and U38-A) output of the Virtex FPGA.Many LED activation signals can be propagated from the Board through the connector X16,enabling to the customer a simple LEDs relocation in any place. Table 14 and Figure 14 showthe pin allocation of the connector X16 and its position on the Board.

3.2 Front-Bracket with LEDs, Buttons and BNC Connector

3.3 Voltage Measurement Test PointsSix test pins schematically represented in Figure 16 enable on the one hand simple and safemeasurement of all voltage levels on the Board (5V, 3.3V, 2.5V, 12V). On the other two of them,

1

2

9

10

X16

Figure 14: Connector X16


LED (Signal) Name Pin

Ground 1

FPGA LED1 2

GNET2_GRESET_ 3

DONE LED 4

FPGA LED0 5

TEST LED 6

Button reset LED 7

Power-on reset LED 8

+3.3V 9

+5V 10

Figure 15: Front-Bracket with LEDs and Buttons

FPGA LED0 (U39-A, Green)

FPGA LED1 (U38-A, Green)Test LED (U40-A, Green)

Power-up Reset (U38-B, Red)

DONE LED (U39-B, Red)

GNET2_GRESET_ (U40-B, Red)

BNC Connector (U20)

Reset Button(U2)PROG Button (U1)


the GND test pins, located in the opposite sides on the Board can serve as comfortable catchpoints for oscilloscope GND input.

J14(+12V)J12(GND)

J11(+2.5V)

J10(+3.3V)

J9(+5V)

J13(GND)

Figure 16: Power Measurement Test Points


3.4 Trigger Input(Note: This feature is under implementation now.)A BNC connector (U20) can be used by the customer as a trigger signal to stop the user clock(USER_CLK).

3.5 Power Consumption Measurement Test PointThe Board offers two jumper connectors X24 and X25 for performing power supplymeasurements for the voltage level 3.3V and 2.5V separately. To run the measurements thecustomer must remove the corresponding jumper (X24 for 3.3V and X25 for 2.5V) and switchon the current measurement device between their pins 1 and 2. After finishing the measurementsthe correspondent jumper must be returned on their locations. The measurements can beperformed either for only one of the voltage levels (3.3V or 2.5V), leaving the other jumper onthe Board, or for the both voltage levels simultaneously.

3.6 Logic Analyzer ConnectorsThe usage of the Board for prototyping of digital hardware leads to the important requirement toenable test of the design under development. The current board manufacturing technology makesit extremely difficult to access necessary measurement points on the Board. Therefore the Boardhas been equipped with special connectors, enabling fast, easy and very comfortable access topractically its all internal lines. These are the Hewlett Packard Mictor-38G connectors thatappeared to become the de-facto standard accepted by many producers of digital measurementsequipment. Figure 17 represents pin allocation of the Mictor connector..

Figure 7 shows location of the Mictor connectors on the block diagram. Refer to the layoutdiagram (Fig. 2) to find their physical location on the Board. Tables 15 though 23 describe howthe pins of the Mictor connectors are connected to the internal signals on the Board.

Odd

Even

Figure 17: Pin Allocation Diagram of the Mictor Connectors


Table 15: Mictor Connector U11

Connector Pin Name

Pin Number

Signal Name

FPGA Pin Number

ODD_0 38 LHOLDA -

ODD_1 36 LHOLD -

ODD_2 34 BLAST_ -

ODD_3 32 ADS_ -

ODD_4 30 LINTO_ -

ODD_5 28 LINTI_ -

ODD_6 26 LRESETI_ -

ODD_7 24 WAITO_ -

ODD_8 22 READYO_ -

ODD_9 20 READYI_ -

ODD_10 18 BTERM_ -

ODD_11 16 DEN_ -

ODD_12 14 LBE2_ C18

ODD_13 12 LBE3_ D18

ODD_14 10 DT/R_ -

ODD_15 8 LW/R_ -

CLK_K 6 SYS_CLK D17

Connector Pin Name

Pin Number

Signal Name

EVEN_0 37 LDHOLD

EVEN_1 35 BREQ

EVEN_2 33 WAITI_

EVEN_3 31 LLOCKO_

EVEN_4 29 LRESETO_

EVEN_5 27 S2

EVEN_6 25 S1

EVEN_7 23 S0

EVEN_8 21 ADMODE

EVEN_9 19 BREQ

EVEN_10 17 LSERR_

EVEN_11 15 NB_

EVEN_12 13 USERO

EVEN_13 11 BTERMO_

EVEN_14 9 USERI

EVEN_15 7 BIGEND_

CLK_J 5 -


Connector Pin Name

Pin Number

Signal Name

FPGA Pin Number

ODD_0 38 LD00 B29

ODD_1 36 LD01 A28

ODD_2 34 LD02 B28

ODD_3 32 LD03 C28

ODD_4 30 LD04 A27

ODD_5 28 LD05 B27

ODD_6 26 LD06 C27

ODD_7 24 LD07 D27

ODD_8 22 LD08 A26

ODD_9 20 LD09 C26

ODD_10 18 LD10 D26

ODD_11 16 LD11 B25

ODD_12 14 LD12 C25

ODD_13 12 LD13 D25

ODD_14 10 LD14 A24

ODD_15 8 LD15 B24

CLK_K 6 - -

Connector Pin Name

Pin Number

Signal Name

FPGA Pin Number

EVEN_0 37 LD16 C24

EVEN_1 35 LD17 D24

EVEN_2 33 LD18 C23

EVEN_3 31 LD19 D23

EVEN_4 29 LD20 A22

EVEN_5 27 LD21 B22

EVEN_6 25 LD22 C22

EVEN_7 23 LD23 D22

EVEN_8 21 LD24 B21

EVEN_9 19 LD25 C21

EVEN_10 17 LD26 A20

EVEN_11 15 LD27 B20

EVEN_12 13 LD28 C20

EVEN_13 11 LD29 D20

EVEN_14 9 LD30 A19

EVEN_15 7 LD31 B19

CLK_J 5 - -



Connector Pin Name

Pin Number

Signal Name

FPGA Pin Number

ODD_0 38 LA02 D8

ODD_1 36 LA03 C8

ODD_2 34 LA04 B8

ODD_3 32 LA05 A8

ODD_4 30 LA06 D9

ODD_5 28 LA07 C9

ODD_6 26 LA08 B9

ODD_7 24 LA09 D10

ODD_8 22 LA10 C10

ODD_9 20 LA11 B10

ODD_10 18 LA12 C11

ODD_11 16 LA13 B11

ODD_12 14 LA14 D12

ODD_13 12 LA15 C12

ODD_14 10 LA16 B12

ODD_15 8 LA17 A12

CLK_K 6 - -

Connector Pin Name

Pin Number

Signal Name

FPGA Pin Number

EVEN_0 37 LA18 D13

EVEN_1 35 LA19 C13

EVEN_2 33 LA20 B13

EVEN_3 31 LA21 A13

EVEN_4 29 LA22 D14

EVEN_5 27 LA23 B14

EVEN_6 25 LA24 D15

EVEN_7 23 LA25 C15

EVEN_8 21 LA26 B15

EVEN_9 19 LA27 A15

EVEN_10 17 LA28 C16

EVEN_11 15 LA29 B16

EVEN_12 13 LA30 C17

EVEN_13 11 LA31 B17

EVEN_14 9 LBE1_ B18

EVEN_15 7 LBE0_ D19

CLK_J 5 - -


Connector Pin Name

Pin Num.

Signal Name

FPGA Pin Number

X1 Ext. Header

Pin Num.

ODD_0 38 EH1_01 AG29 C2

ODD_1 36 EH1_02 AG28 A3

ODD_2 34 EH1_03 AF31 B3

ODD_3 32 EH1_04 AF30 C3

ODD_4 30 EH1_05 AF29 A4

ODD_5 28 EH1_06 AF28 B4

ODD_6 26 EH1_07 AE30 C4

ODD_7 24 EH1_08 AE28 A5

ODD_8 22 EH1_09 AD31 B5

ODD_9 20 EH1_10 AD30 C5

ODD_10 18 EH1_11 AD29 A6

ODD_11 16 EH1_12 AD28 B6

ODD_12 14 EH1_13 AC30 C6

ODD_13 12 EH1_14 AC29 A7

ODD_14 10 EH1_15 AC28 B7

ODD_15 8 EH1_16 AB31 C7

CLK_K 6 RAM2_CLK AJ30 / A16 -

Connector Pin Name

Pin Num.

Signal Name

FPGA Pin Number

X1 Ext. Header

Pin Num.

EVEN_0 37 EH1_17 AB29 A8

EVEN_1 35 EH1_18 AB28 B8

EVEN_2 33 EH1_19 AA30 C8

EVEN_3 31 EH1_20 AA29 A9

EVEN_4 29 EH1_21 Y31 B9

EVEN_5 27 EH1_22 Y30 C9

EVEN_6 25 EH1_23 Y29 A10

EVEN_7 23 EH1_24 Y28 B10

EVEN_8 21 EH1_25 W30 C10

EVEN_9 19 EH1_26 W29 B11

EVEN_10 17 EH1_27 W28 C11

EVEN_11 15 EH1_28 V30 A12

EVEN_12 13 EH1_29 V29 B12

EVEN_13 11 EH1_30 V28 C12

EVEN_14 9 EH1_31 U31 A13

EVEN_15 7 EH1_32 U30 B13

CLK_J 5 - - -



Connector Pin Name

Pin Num.

Signal Name

FPGA Pin

Number

X1 Ext. Header

Pin Num.

ODD_0 38 EH1_33 U29 C13

ODD_1 36 EH1_34 U28 A14

ODD_2 34 EH1_35 T30 B14

ODD_3 32 EH1_36 T31 C14

ODD_4 30 EH1_37 R31 A15

ODD_5 28 EH1_38 R30 B15

ODD_6 26 EH1_39 R29 C15

ODD_7 24 EH1_40 R28 A16

ODD_8 22 EH1_41 P30 B16

ODD_9 20 EH1_42 P29 C16

ODD_10 18 EH1_43 P28 A17

ODD_11 16 EH1_44 N31 B17

ODD_12 14 EH1_45 N30 C17

ODD_13 12 EH1_46 N28 A18

ODD_14 10 EH1_47 M31 B18

ODD_15 8 EH1_48 M30 C18

CLK_K 6 - - -

Connector Pin Name

Pin Num.

Signal Name

FPGA Pin Number

X1 Ext. Header

Pin Num.

EVEN_0 37 EH1_49 M29 A19

EVEN_1 35 EH1_50 M28 B19

EVEN_2 33 EH1_51 L30 C19

EVEN_3 31 EH1_52 L29 A20

EVEN_4 29 EH1_53 K31 B20

EVEN_5 27 EH1_54 K30 C20

EVEN_6 25 EH1_55 K28 A21

EVEN_7 23 EH1_56 J30 B21

EVEN_8 21 EH1_57 J29 C21

EVEN_9 19 EH1_58 J28 B22

EVEN_10 17 EH1_59 H31 C22

EVEN_11 15 EH1_60 H30 A23

EVEN_12 13 EH1_61 H29 B23

EVEN_13 11 EH1_62 H28 C23

EVEN_14 9 EH1_63 G30 A24

EVEN_15 7 EH1_64 G29 B24

CLK_J 5 - - -


Connector Pin Name

Pin Num.

Signal Name

FPGA Pin Number

X1 Ext. Header

Pin Num.

ODD_0 38 EH1_65 G28 C24

ODD_1 36 EH1_66 F31 A25

ODD_2 34 EH1_67 F29 B25

ODD_3 32 EH1_68 F28 C25

ODD_4 30 EH1_69 E31 A26

ODD_5 28 EH1_70 E30 B26

ODD_6 26 EH1_71 E29 C26

ODD_7 24 EH1_72 E28 A27

ODD_8 22 EH1_73 D31 B27

ODD_9 20 EH1_74 D30 C27

ODD_10 18 EH1_75 C30 A28

ODD_11 16 EH1_76 AG30 B28

ODD_12 14 EH1_77 AG31 C28

ODD_13 12 EH1_78 AH30 A29

ODD_14 10 EH1_79 AH31 B29

ODD_15 8 EH1_80 AK28 C29

CLK_K 6 USER_CLK/WDCLK

AL16 B30

Connector Pin Name

Pin Num Signal Name FPGA Pin

Number

X1 Ext. Header

Pin Num.

EVEN_0 37 EH1_81 AL28 A30

EVEN_1 35 EH1_83 AJ27 C30

EVEN_2 33 EH1_84 AK27 A31

EVEN_3 31 EH1_85 AL27 B31

EVEN_4 29 EH1_86 AH26 C31

EVEN_5 27 LED0_0 - -

EVEN_6 25 LED1_0 - -

EVEN_7 23 HARDRESET_0 - -

EVEN_8 21 GNET1_0 - A2

EVEN_9 19 GNET2_ GRESET_0

D6 B2

EVEN_10 17 TASTER_ RESET_0

- -

EVEN_11 15 CPLDIO1 D1 -

EVEN_12 13 CPLDIO2 - -

EVEN_13 11 CPLDIO3 - -

EVEN_14 9 CS95_2_0 - -

EVEN_15 7 - - -

CLK_J 5 - - -



Connector Pin Name

Pin Num.

Signal Name

FPGA Pin Number

X2 Ext. Header

Pin Num.

ODD_0 38 EH2_01 AJ26 C2

ODD_1 36 EH2_02 AK26 A3

ODD_2 34 EH2_03 AL26 B3

ODD_3 32 EH2_04 AH25 C3

ODD_4 30 EH2_05 AJ25 A4

ODD_5 28 EH2_06 AK25 B4

ODD_6 26 EH2_07 AJ24 C4

ODD_7 24 EH2_08 AK24 A5

ODD_8 22 EH2_09 AL24 B5

ODD_9 20 EH2_10 AH23 C5

ODD_10 18 EH2_11 AJ23 A6

ODD_11 16 EH2_12 AK23 B6

ODD_12 14 EH2_13 AH22 C6

ODD_13 12 EH2_14 AJ22 A7

ODD_14 10 EH2_15 AL22 B7

ODD_15 8 EH2_16 AJ21 C7

CLK_K 6 - - -

Connector Pin Name

Pin Num.

Signal Name

FPGA Pin Number

X2 Ext. Header

Pin Num.

EVEN_0 37 EH2_17 AK21 A8

EVEN_1 35 EH2_18 AH20 B8

EVEN_2 33 EH2_19 AJ20 C8

EVEN_3 31 EH2_20 AK20 A9

EVEN_4 29 EH2_21 AL20 B9

EVEN_5 27 EH2_22 AH19 C9

EVEN_6 25 EH2_23 AJ19 A10

EVEN_7 23 EH2_24 AL19 B10

EVEN_8 21 EH2_25 AH18 C10

EVEN_9 19 EH2_26 AJ18 B11

EVEN_10 17 EH2_27 AK18 C11

EVEN_11 15 EH2_28 AH17 A12

EVEN_12 13 EH2_29 AJ17 B12

EVEN_13 11 EH2_30 AK17 C12

EVEN_14 9 EH2_31 AL17 A13

EVEN_15 7 EH2_32 AH15 B13

CLK_J 5 - - -


Connector Pin Name

Pin Num.

Signal Name

FPGA Pin Number

X2 Ext. Header

Pin Num.

ODD_0 38 EH2_33 AJ15 C13

ODD_1 36 EH2_34 AK15 A14

ODD_2 34 EH2_35 AL15 B14

ODD_3 32 EH2_36 AH14 C14

ODD_4 30 EH2_37 AJ14 A15

ODD_5 28 EH2_38 AK14 B15

ODD_6 26 EH2_39 AH13 C15

ODD_7 24 EH2_40 AJ13 A16

ODD_8 22 EH2_41 AL13 B16

ODD_9 20 EH2_42 AH12 C16

ODD_10 18 EH2_43 AJ12 A17

ODD_11 16 EH2_44 AK12 B17

ODD_12 14 EH2_45 AL12 C17

ODD_13 12 EH2_46 AJ11 A18

ODD_14 10 EH2_47 AK11 B18

ODD_15 8 EH2_48 AH10 C18

CLK_K 6 - - -

Connector Pin Name

Pin Num.

Signal Name

FPGA Pin Number

X2 Ext. Header

Pin Num.

EVEN_0 37 EH2_49 AK10 A19

EVEN_1 35 EH2_50 AL10 B19

EVEN_2 33 EH2_51 AH9 C19

EVEN_3 31 EH2_52 AJ9 A20

EVEN_4 29 EH2_53 AK9 B20

EVEN_5 27 EH2_54 AJ8 C20

EVEN_6 25 EH2_55 AK8 A21

EVEN_7 23 EH2_56 AL8 B21

EVEN_8 21 EH2_57 AH7 C21

EVEN_9 19 EH2_58 AJ7 B22

EVEN_10 17 EH2_59 AK7 C22

EVEN_11 15 EH2_60 AH6 A23

EVEN_12 13 EH2_61 AJ6 B23

EVEN_13 11 EH2_62 AK6 C23

EVEN_14 9 EH2_63 AL6 A24

EVEN_15 7 EH2_64 AH5 B24

CLK_J 5 - - -



Connector Pin Name

Pin Num.

Signal Name

FPGA Pin Number

X2 Ext. Header

Pin Num.

ODD_0 38 EH2_65 AJ5 C24

ODD_1 36 EH2_66 AK5 A25

ODD_2 34 EH2_67 AL5 B25

ODD_3 32 EH2_68 AJ4 C25

ODD_4 30 EH2_69 AK4 A26

ODD_5 28 EH2_70 AL4 B26

ODD_6 26 EH2_71 AK3 C26

ODD_7 24 EH2_72 AH2 A27

ODD_8 22 EH2_73 AH1 B27

ODD_9 20 EH2_74 AG3 C27

ODD_10 18 EH2_75 AG2 A28

ODD_11 16 EH2_76 AG1 B28

ODD_12 14 EH2_77 AF4 C28

ODD_13 12 EH2_78 AF3 A29

ODD_14 10 EH2_79 AF2 B29

ODD_15 8 EH2_80 AE4 C29

CLK_K 6 - - -

Connector Pin Name

Pin Num.

Signal Name

FPGA Pin Number

X2 Ext. Header

Pin Num.

EVEN_0 37 EH2_81 AE3 A30

EVEN_1 35 EH2_82 AE2 B30

EVEN_2 33 EH2_83 AD4 C30

EVEN_3 31 EH2_84 AD3 A31

EVEN_4 29 EH2_85 AD2 B31

EVEN_5 27 EH2_86 AD1 C31

EVEN_6 25 FIO_CS_0 B7 -

EVEN_7 23 FWR_0 C6 -

EVEN_8 21 FRD_0 B6 -

EVEN_9 19 FWAIT_0 A6 -

EVEN_10 17 F_INT_0 D7 -

EVEN_11 15 GNET1_0 - A2

EVEN_12 13 GNET2_ GRESET_0

D6 B2

EVEN_13 11 LLOCK_ - -

EVEN_14 9 DMPAF_ - -

EVEN_15 7 PCHK_ - -

CLK_J 5 - - -


4 Configuration of the Virtex FPGAThe Board supports various alternatives for programming the Virtex FPGA with the designconfiguration file generated by the Xilinx development tools:

• through PCI bus in PC based mode;• through the FPGA JTAG interface, using Xilinx X-Checker or Parallel Cable;• from the on board located parallel Xilinx EEPROMs XCV18V0x.

4.1 Configuration through PCI Bus The main facility for configuration of the Virtex device on the Board is through the PCI bus byusing supplied software utility xloadv2. This method provides the optimal conditions for theFPGA configuration, being much more reliable than JTAG based one. It is recommended toprefer its usage then of the other configuration alternatives.For downloading bit image through the PCI Interface, the Virtex device is configured in theselect-map mode. The start-up clock is the CCLK clock generated by the CPLD. See Xilinxdevelopment software documentation for more information on configuration of the FPGAdevice.The xloadv2 utility can download the design configuration file only generated in the binarybitstream format (*.bit) format. Section describes usage of the xloadv2 utility.You must have the Board installed in PCI base mode, as described in section 6, before you canstart with this way of configuration.Configuration of the Virtex FPGA through its PCI interface as follows:

• perform the complete development process for your design using Xilinx software and generate the configuration file in the binary bitstream format (.bit);

• start xloadv2 utility by double clicking on the xloadv2 program from a Window NT browser. The message "Board opened successfully" indicates successful installation and configuration of the Board. The message „Board ist tot“ indicates an error when the pro-gram tried to communicate with the Board. In this case you must check if all installation steps have been performed correctly and try again before the message "Board opened suc-cessfully" appeared.

• with the following messages the program will inform you about the device-ID, vendor-ID bus number and slot number of the Board. The "Enter Filename and hit RETURN:" mes-

sage will invite you to type in the name of the design bit image.• type in the name of the design file and push Return key. The program begins configura-

tion process with the following messages. It gives out the points as the configuration pro-

ceeds. The red Done LED (J19) (see Section 3.1) is turned on during configuration. When

There is 1 board in this computer.Board opened successfullyU32 DeviceId is 9080U32 VendorId is 10B5U32 BusNumber is 0000U32 SlotNumber is 000DSerialNumber[16] is pci9080-0

Enter Filename and hit RETURN:

FPGA design: yourdesign.ncd part: v300bg432 date: 2000/07/21 time: 10:38:09 size: 218976 bytes

Programming.............


the downloading finished the program gives the message indicating with the simultane-

ous turning-off of the Done LED successfully completed configuration;• press any key to close the xloadv2 window.

After the configuration is completed the Done LED (J19) will turn off, indicating its successfulcompletion. Now your design is ready for operating.

4.2 Configuration through FPGA JTAG Interface The Board enables programming of the Virtex FPGA through its JTAG interface. Such aconfiguration method is supported by Xilinx Foundation or Alliance Series Software. You canuse either the XChecker cable or the parallel download cable from Xilinx for it. The XCheckercable can be connected to the serial port of the workstation, while the parallel download cablesupports the configuration process only through the PC’s parallel printer port. The configurationcables are not delivered by the FZI and must be purchased from the Xilinx distributers.The cable must be connected to the board through the FPGA JTAG interface connector X5.Figure 18 and Table 24 show the location of this connector on the Board and its pin allocation.See Xilinx development software documentation for more information on configuration of theFPGA device through the JTAG interface.You must have the Board installed either in PCI base or stand-alone mode, as described in section6, before you can start with this way of configuration.Configuration of the Virtex FPGA through its JTAG interface proceeds as follows:


• execute the configuration process of the Virtex FPGA device, using Xilinx development software.

218976 bytes written, waiting for done...

FPGA programmed successfully! Press any key

Figure 18: FPGA JTAG Connector

87

21

X5


Signal Name Pin

TCK 1

TDI 2

TDO 3

TMS 4

- 5

GND 6

+5V 7

+3.3V 8


4.3 Configuration from the parallel PROMs XC18V0xThe two parallel PROM chips (XC18V0x) offer another facility to configure the Virtex FPGA.They are cascaded to provide enough memory (6Mbit) for the biggest available Virtex FPGA(XCV800).The main advantage of this configuration alternative is that in this case the FPGA is programmedautomatically, when the power goes up on the Board. You need not perform any configurationprocedures manually. Thus the external programming equipment is not longer necessary.This is the basic configuration way, when using the Board after completion of FPGA designdebugging. It is very useful for the stand-alone applications.This configuration method is used to demonstrate the Board’s correct functionality by loadingthe stored FPGA bit image after power-on. The preprogrammed FPGA bit image is the blinkerdesign (see section 7.1) and its correct operating you can detect by the fluttering FPGA LED (J18and U39-A) (see Section 3.1).The Board enables programming of the PROM devices through their JTAG interfaces. Such aconfiguration method is supported by Xilinx Foundation or Alliance Series Software. You canuse either the XChecker cable or the parallel download cable from Xilinx for it. The XCheckercable can be connected to the serial port of the workstation, while the parallel download cablesupports the configuration process only through the PC’s parallel printer port. The configurationcables are not delivered by the FZI and must be purchased from the Xilinx distributers.The cable must be connected to the board through the PROM JTAG interface connector X5.Figure 19 and Table 25 show the location of this connector on the Board and its pin allocation.See Xilinx development software documentation for more information on configuration of thePROM devices through the JTAG interface.You must have the Board installed either in PCI base or stand-alone mode, as described in section6, before you can start with this way of configuration.Configuration of the Virtex FPGA through its JTAG interface proceeds as follows:


• execute the configuration process of the PROM devices, using Xilinx development soft-ware.

Figure 19: PROM JTAG Connector

87

21

X27


Signal Name Pin

TCK 1

TDI 2

TMS 3

TDO 4

- 5

GND 6

+5V 7

+3.3V 8


5 Board Service SoftwareTo enable easy control, diagnosis, configuration, and communication with the Board, specialservice software has been developed. These programs (utilities) run under Windows NT andcommunicate with the PCI9080 and XC94144XL internal registers.The following utilities are provided with the this Board version:

• ready.exe• reset.exe• xloadv2.exe• sram1en.exe• sram2en.exe• sram1dis.exe• sram2dis.exe

The most recent software version can be downloaded via the Internet from the FZI WWW-site.The service software is stored in the directory \software\utililies\bin on the CDROM which isprovided with the Board from FZI. To install it on your computer copy all the utilities from thisdirectory to any location on the PC hard disk.The utilities can be started:

• from the MS-DOS command window by typing their names in the command line and pressing Enter;

• by double clicking on the utility icon in the Browser window.The service programs provided with the Board are described further in this section.

Nameready

Synopsisready

DescriptionDis-activates signal GNET2_GRESET_ (see section 2.4.1), turning off theFPGA Reset (U40-B) and CPLD 0 (J15) LEDs.

File\software\utilities\bin\ready.exe

See alsoreset


Namereset

Synopsisreset

DescriptionActivates signal GNET2_GRESET_ (see section 2.4.1), turning on the FPGAReset (U40-B) and CPLD 0 (J15) LEDs.

File\software\utilities\bin\reset.exe

See alsoready

Namexloadv2

Synopsisxloadv2

DescriptionDownloads the design configuration file in bit-format via PCI Interface intothe FPGA.

File\software\utilities\bin\xloadv2.exe


Namesram1en

Synopsissram1en

DescriptionEnables usage of the SSRAM1 device. This is one of the necessary conditionsfor SSRAM activation. After executing this command the FPGA design cancontrol SSRAM accesses on the Board.

File\software\utilities\bin\sram1en.exe

See alsosram1dis, sram2en, sram2dis

Namesram1dis

Synopsissram1dis

DescriptionDisables usage of the SSRAM1 device. After executing this command theSSRAM accesses can not be controlled from the FPGA design.

File\software\utilities\bin\sram1dis.exe

See alsosram1en, sram2en, sram2dis


Namesram2en

Synopsissram2en

DescriptionEnables usage of the SSRAM2 device. This is one of the necessary conditionsfor SSRAM activation. After executing this command the FPGA design cancontrol SSRAM accesses on the Board.

File\software\utilities\bin\sram2en.exe

See alsosram2dis, sram1en, sram1dis

Namesram2dis

Synopsissram2dis

DescriptionDisables usage of the SSRAM2 device. After executing this command theSSRAM accesses can not be controlled from the FPGA design.

File\software\utilities\bin\sram2dis.exe

See alsosram2en, sram1en, sram1dis


6 Board InstallationTo set up the Board in one of its two operation modes (PC based or stand-alone) and adjust it forusage in your system configuration with wished customization settings, it is necessary to takesome easy preparation steps before you can use it.Execute the following steps to set up the Board:

• set the jumper X3, as described in section 2.3 to choose PCI or external power supply source for the Board. Connect the external power source through the connector PSW5, if necessary;

• check the presence of the jumpers X24 and X25 (Fig. 3) on the Board;• if you connect some external hardware to the Board through the extension headers X1 or/

and X2, set the jumpers X8 -X15 as described in section 2.8. Connect the external hard-ware to the Board through X1 or/and X2;

• set the DIP switches S1-5 and/or S1-6 to activate SSRAM devices on the Board if neces-sary;

• install the supplied Windows NT device driver and plxapi.dll library, or you must have PLX SDK software installed on your PC (see PCI SDK User’s Manual for details)

• insert the Board in a free PCI slot for PC base mode;• turn on the external power supply switch, if necessary, or/and turn on the PC with the

installed Board. The PC starts boot process, automatically configurating the Board under Windows NT operation system. See section 2.5.1 to get to know, how the initialization of the Board PCI Adapter runs. After power-on the Test (J16 and U40-A) LEDs must be burning;

• execute the utilities sram1en.exe or/and sram2en.exe to activate SSRAM device(s), if necessary.

The board detects automatically, if it is placed in the PCI-Slot or not. If not, it disables the PCI9080 Adapter, bringing its I/O in the high-impedance state, and initiates the FPGA configurationprocess. The FPGA design bit image is loaded from the Xilinx XC18V0x PROMs, and theapplication is activated afterwards.After these steps have been successfully executed, the Board is ready for operating. You can re-program the Virtex FPGA now, as described in section 4. You can download one of the supplieddemonstration designs represented in section 7 to test the Board features and ensure yourself inits correct behaviour.


7 Demonstration Designs of Board OperatingThe Board is supplied with the following designs and programs for demonstration of itsoperating:

• Blinker (PC based and stand-alone mode);• Multiplier (PC based mode);• SSRAM Test (PC based mode);• FPGA power consumption test (PC based and stand-alone mode).

Blinker is a simple design which purpose is only to force the FPGA LED J18 blinking. Itrepresent the most simple mean for testing the Board. SSRAM Test consist of a Virtex FPGA design and a program. The design enables data transferbetween the PC and SSRAM devices on the Board through the PCI bus. The program runs asimple test of the both SSRAM devices on the Board through the PCI interface.The source codes of these demonstration designs are represented in Appendices A through B andsupplied on the CDROM. In this section we describe the procedure of configuration and running this designs.

7.1 BlinkerTo run Blinker design you should first copy the configuration file from the supplied CDROMinto any location on the hard disk of the PC, containing the installed Board. The Blinker designis located on the CDROM in the directory: \demos\blinker. It contains one subdirectory for eachVirtex FPGA type (XCV300 and XCV800) which contain the configuration files (blinker.bit) forBlinker design generated for PCI based configuration. Directory src contains the file blinker.vhdwith the RTL-level design description in VHDL and the file in the UCF format blinker.ucf. Theyhave been used for synthesis and implementation of this design by XILINX design software.You can run Blinker design application either in PC based or in stand-alone mode. In the secondcase you can use only JTAG based configuration method.You must first install your Board as described in section 6. Then proceed with the PCI basedconfiguration as follows:

• start xloadv2 utility by double clicking on the xloadv2 program from a Window NT browser. The message "There is 1 Board in this computer.“ indicates successful installa-tion and configuration of the Board. The message „ERROR: No board found !!!“ indi-cates an error when the program tried to communicate with the Board. In this case you must check if all installation steps have been performed correctly and try again before the message "There is 1 Board in this computer." appeared.

• type in the name of the design file blinker.bit and press the Return key. The program begins configuration process with the following messages. It gives out the points as the configuration proceeds. The red Done LED (J19 and U39-B) is turned on during configu-

There is 1 board in this computer.Board opened successfullyU32 DeviceId is 9080U32 VendorId is 10B5U32 BusNumber is 0000U32 SlotNumber is 000DSerialNumber[16] is pci9080-0

Enter Filename and hit RETURN:


ration. When the downloading finished the program gives the message „FPGA pro-

grammed successfully!“ indicating with the simultaneous turning-off of the Done LED that the configuration was completed successfully. The design is activated afterwards and you can see the yellow/green FPGA LED (J18 and U39-A) blinking on the Board;

• press any key to close the xload window;• reset the Blinker design by starting the program reset.exe. The FPGA LED will be turned

off and the FPGA Reset (J3) as well as the CPLD 0 (J15) LEDs will be turned on;• activate the Board normal operating by executing ready.exe utility. The FPGA LED will

continues blinking.See section 4.2 to get more information on performing JTAG-based FPGA configuration.By pushing Reset button on the Board you can generate hardware reset signal. LEDs J3 and U40-B will be burning until the button is pushed off. You can activate software reset executing utilityreset.exe.

7.2 SSRAM TestThe SSRAM Test demo consist of the FPGA configuration file and the program running underWindows NT. The design enables data transfer between the PC and SSRAM devices on theBoard through the PCI bus. The program executes some tests (Data Bus Test, Address Bus Test,Device Test, Pseudo Random Pattern Test) of the both SSRAM devices on the Board through thePCI interface. You can run this demo only in PC based mode.To run SSRAM Test demo you should first copy the FPGA configuration file and the programfrom the supplied CDROM into any location on the hard disk of the PC with the installed Board.SSRAM Test design is located on the CDROM in the directory: \demos\sramtest. It contains onesubdirectory for each Virtex FPGA type (XCV300 and XCV800) with the configuration files(sramtest.bit) for this demonstration design generated for the PCI based configuration. Directorysrc contains the file sramtest.vhd with the RTL-level design description in VHDL, the file inUCF-format sramtest.ucf and C source code of the program sramtest.c. The first two have beenused for synthesis and implementation of this design by XILINX design software. The directory\demos\sramtest\bin contain the program executable sramtest.exe.To run SSRAM Test demo you must first install the Board as described in section 6. Then startPCI based configuration process executing the utility xload for the file sramtest.bit from theconfiguration directory on the hard disk as described for the Blinker demo in the section aboveAfter the configuration is completed, the Done LED (J19 and U39-B) will turn off and you willsee FPGA LED J18 and U39-A blinking on the Board, indicating correct design operating. TheBlinker subdesign used in this demo to indicate successful downloading and activation of theSSRAM Test demo design.Activate the both SSRAM devices on the Board by executing the sram1en.exe and sram2en.exeutilities. They are located in the directory \software\utilities\bin.

FPGA design: blinker.ncd part: v300bg432 date: 2000/07/21 time: 10:38:09 size: 218976 bytes

Programming.............

218976 bytes written, waiting for done...

FPGA programmed successfully! Press any key


Now you can run test of the SSRAM devices by starting the sramtest.exe program. The programasks you to select the SSRAM size and the device number and executes the test. The followingmessages indicate successful test run for the SSRAM2 device:

7.3 MultiplierThis design performs multiplication of two 8-bit signed integer operands returning 16-bit valueas a result. The multiplier realized as a combinational circuit is accessed from the PC over thePCI interface. Using the demonstration program, the customer can execute multiplication of twointeger values and check the result. The demo is located in the directory /demos/multiplier andcontains the Virtex FPGA image file (multiplier.bit) generated for the PCI based configurationas well as the multiplier.exe program. The source code file are also supplied.Download the multiplier.bit file as described in the previous sections and test the multiplier’sfunctionality using the demonstration program.

7.4 FPGA Power Consumption TestThis demo can be used for FPGA power consumption measurements. It enables very high usageof the FPGA configurable hardware resources with their maximal possible switching degree. To run the FPGA Power Consumption Test demo you should first copy the FPGA configurationfile from the supplied CDROM into any location on the hard disk of the PC with the installedBoard. It is located on the CDROM in the directory: \demos\powertest. The directory containsone subdirectory for each available Virtex FPGA type (XCV300 and XCV800) with the

Spyder-Virtex SSRAM Test

SSRAM Size: 1 : 32k x 32 2 : 64k x 32 3 : 128k x 32 4: 128k x 32Select SSRAM Size (1): SSRAM Range under Test: 32k x 32

Select PRP Test Length (Number of Cycles): 1 : 1 Cycle2 : 10 Cycles3 : 100 Cyclesx : Input Value Select PRP Length (1): Test Length is 1 Cycle

SSRAM Device 1 : SSRAM1 2 : SSRAM2 9 : SSRAM1 and SSRAM2Select SSRAM Device (9):

Testing SSRAM1 SSRAM1 Data Bus Test ... OK! SSRAM1 Address Bus Test ... OK! SSRAM1 Device Test ... OK! SSRAM1 Pseudo Random Test ... OK!

Testing SSRAM2 SSRAM2 Data Bus Test ... OK! SSRAM2 Address Bus Test ... OK! SSRAM2 Device Test ... OK! SSRAM2 Pseudo Random Test ... OK!

Press any key to exit


configuration files (t22io200.bit) generated for the PCI based configuration. Directory srccontains the file t22io200.vhd with the RTL-level design description in VHDL, the file in UCF-format t22io200.ucf .You must first install your Board as described in section 6. Then start PCI based configurationprocess executing the utility xload for the file t22io200.bit from your configuration directory onthe hard disk as described for the Blinker demo in previous section. After the configuration iscompleted, the Done LED (J19 and U39-B) will turn off and the application is activated.


Appendix A: Blinker Demo Source Code File: blinker.vhdlibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;

entity BLINKER is Port (COMCLK : IN std_logic;

Reset_0 : IN std_logic;LED_0 : BUFFER std_logic;

HDC : OUT std_logic);end BLINKER;

architecture behavior of BLINKER isSIGNAL count : INTEGER Range 0 to 1000000;BEGINHDC <= '0';COUNTPROC: PROCESS(COMCLK, Reset_0, LED_0, count) BEGIN IF Reset_0 = '0' THEN LED_0 <= '1';-- LED aus count <= 0; ELSIF (COMCLK'event and COMCLK = '1') THEN IF count = 1000000 THEN

count <= 0;LED_0 <= not LED_0;

ELSEcount <= count+1;

END IF; END IF; END PROCESS;END behavior;


Appendix B: SSRAM Test Demo Source Code FilesFile sramtest.vhd:--------------------------------------------------------------------------- File: ssramtest.vhd-- SSRAM (up to 256k 32-bit words) Test-- I.Katchan, SiM, FZI-- 01.08.99-- updated for re-design-- 28.12.99-------------------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all; entity mem_test is Port ( PCLK : in std_logic; GNET2_GRESET_0 : in std_logic;

FRD_0 : in std_logic;FWR_0 : in std_logic;

-- Local BUS InterfaceLA : in std_logic_vector(26 downto 2) ;LBE0_0 : in std_logic;LBE1_0 : in std_logic;LBE2_0 : in std_logic;LBE3_0 : in std_logic;LD : inout std_logic_vector(31 downto 0) ;

-- SSRAM interface SYS_CLK : out std_logic; SSCS1_0 : out std_logic; GW1_0 : out std_logic; SSBWE1_0 : out std_logic; ADSP1_0 : out std_logic; ADSC1_0 : out std_logic; SSCE1 : out std_logic; SS_SNOOZ1 : out std_logic; SSOE1_0 : out std_logic; ADV1_0 : out std_logic; SSMODE1 : out std_logic;

SSCS2_0 : out std_logic; GW2_0 : out std_logic; SSBWE2_0 : out std_logic; ADSP2_0 : out std_logic; ADSC2_0 : out std_logic; SSCE2 : out std_logic; SS_SNOOZ2 : out std_logic; SSOE2_0 : out std_logic; ADV2_0 : out std_logic; SSMODE2 : out std_logic; BWE1_0 : out std_logic_vector (3 downto 0); SSA1 : out std_logic_vector (19 downto 2); SSD1 : inout std_logic_vector (31 downto 0);

BWE2_0 : out std_logic_vector (3 downto 0); SSA2 : out std_logic_vector (19 downto 2); SSD2 : inout std_logic_vector (31 downto 0);-- LEDs FPGA_LED_0 : out std_logic);end mem_test; architecture BEHAVIORAL of mem_test issignal INT_CLK : std_logic;signal SSRAM1_SpaceCS : std_logic;signal SSRAM2_SpaceCS : std_logic;signal count : integer range 0 to 20000000;signal LED_TMP_0 : std_logic;

begin

INT_CLK <= PCLK;SYS_CLK <= PCLK;GW1_0 <= '1';SSBWE1_0 <= '0';ADSP1_0 <= '1';ADSC1_0 <= '0' ;SSCE1 <= '1';SS_SNOOZ1 <= '0';SSOE1_0 <= '0';ADV1_0 <= '1';SSMODE1 <= '1';GW2_0 <= '1';SSBWE2_0 <= '0';


ADSP2_0 <= '1';ADSC2_0 <= '0' ;SSCE2 <= '1';SS_SNOOZ2 <= '0';SSOE2_0 <= '0';ADV2_0 <= '1';SSMODE2 <= '1';

SSRAM1_SpaceCS <= '1' when LA(26 downto 19) = "00000000" else '0';SSRAM2_SpaceCS <= '1' when LA(26 downto 19) = "00000001" else '0';SSA1 <= '0' & LA(18 downto 2);SSA2 <= '0' & LA(18 downto 2);

SS1Choose_P : process(SSRAM1_SpaceCS, FRD_0, FWR_0)begin

if (SSRAM1_SpaceCS = '1' and (FRD_0 = '0' or FWR_0 = '0')) then SSCS1_0 <= '0';else SSCS1_0 <= '1';end if;

end process;

SS2Choose_P : process(SSRAM2_SpaceCS, FRD_0, FWR_0) begin

if (SSRAM2_SpaceCS = '1' and (FRD_0 = '0' or FWR_0 = '0')) then SSCS2_0 <= '0';else SSCS2_0 <= '1';

end if;end process;

BWE1_P : process (LBE0_0, LBE1_0, LBE2_0, LBE3_0, FWR_0, SSRAM1_SpaceCS)begin if (FWR_0 ='0' and SSRAM1_SpaceCS = '1') then BWE1_0(0) <= LBE0_0; BWE1_0(1) <= LBE1_0; BWE1_0(2) <= LBE2_0; BWE1_0(3) <= LBE3_0; else BWE1_0(0) <= '1'; BWE1_0(1) <= '1'; BWE1_0(2) <= '1'; BWE1_0(3) <= '1'; end if;end process; BWE2_P : process (LBE0_0, LBE1_0, LBE2_0, LBE3_0, FWR_0, SSRAM2_SpaceCS)begin if (FWR_0 ='0' and SSRAM2_spaceCS = '1') then BWE2_0(0) <= LBE0_0; BWE2_0(1) <= LBE1_0; BWE2_0(2) <= LBE2_0; BWE2_0(3) <= LBE3_0; else BWE2_0(0) <= '1'; BWE2_0(1) <= '1'; BWE2_0(2) <= '1'; BWE2_0(3) <= '1'; end if;end process;

LD_TRI_STATE_P: process (FRD_0, SSD1, SSD2, SSRAM1_SpaceCS, SSRAM2_SpaceCS) begin if (FRD_0 ='0') then if SSRAM1_SpaceCS = '1' then LD <= SSD1 ; elsif SSRAM2_SpaceCS = '1' then LD <= SSD2 ; else LD <= (others => 'Z'); end if; else LD <= (others => 'Z'); end if; end process;

SSD1_TRI_STATE_P: process (LD, SSRAM1_SpaceCS, FWR_0) begin if (FWR_0 ='0' and SSRAM1_SpaceCS = '1') then SSD1 <= LD; else SSD1 <= (others => 'Z'); end if;end process;


SSD2_TRI_STATE_P: process (LD, SSRAM2_SpaceCS, FWR_0) begin if (FWR_0 ='0' and SSRAM2_SpaceCS = '1') then SSD2 <= LD; else SSD2 <= (others => 'Z'); end if;end process;

FPGA_LED_0 <= LED_TMP_0 ;LED_BLINKER_P: process (INT_CLK, GNET2_GRESET_0, count, LED_TMP_0) begin if (INT_CLK'event and INT_CLK = '1') then if GNET2_GRESET_0 = '0' then LED_TMP_0 <= '1'; count <= 0; else if count = 15000000 then count <= 0; LED_TMP_0 <= not LED_TMP_0; else count <= count + 1; end if; end if; end if;end process;end BEHAVIORAL;

File: ssramtest.c:/****************************************************************************** * Copyright (c) 1997 - 1998 PLX Technology, Inc. * * PLX Technology Inc. licenses this software under specific terms and * conditions. Use of any of the software or derviatives thereof in any * product without a PLX Technology chip is strictly prohibited. * * PLX Technology, Inc. provides this software AS IS, WITHOUT ANY WARRANTY, * EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. PLX makes no guarantee * or representations regarding the use of, or the results of the use of, * the software and documentation in terms of correctness, accuracy, * reliability, currentness, or otherwise; and you rely on the software, * documentation and results solely at your own risk. * * IN NO EVENT SHALL PLX BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS, * LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES * OF ANY KIND. IN NO EVENT SHALL PLX’S TOTAL LIABILITY EXCEED THE SUM * PAID TO PLX FOR THE PRODUCT LICENSED HEREUNDER. * *****************************************************************************/#include <windows.h>#include <stdio.h>#include <conio.h>#include "d:\Plx\PciSdk\Inc\pcitypes.h"#include "d:\Plx\PciSdk\Inc\plxtypes.h"#include "d:\Plx\PciSdk\Inc\PlxError.h"#include "d:\Plx\PciSdk\Inc\plx.h"#include "d:\Plx\PciSdk\Inc\PciApi.h"

/********************************************************//* U32 Pseudo Random Test Data and Functions*//* *//********************************************************/U32 nextPRP(U32 previous) {

const U32 feedBackPoly = 0xEDB88320;

U32 termData = 0x0; termData = previous >> 1; if (previous & 0x01) return (termData ^ feedBackPoly); else return (termData);} // nextPRP

/********************************************************/// PCI Data// Used to work with a PCI device /********************************************************/ RETURN_CODE rc; DEVICE_LOCATION device;

HANDLE myPlxDevice;VIRTUAL_ADDRESSES virtualAddresses;

void openVirtex() {


/************************************************************/// PCI9080 Device Open/************************************************************/

// opens PCI access to the Spyder-Virtex Board// You must close the PCI access by closeVirtex before exit !

device.BusNumber = MINUS_ONE_LONG; device.SlotNumber = MINUS_ONE_LONG; device.DeviceId = MINUS_ONE_LONG; device.VendorId = MINUS_ONE_LONG; strcpy (device.SerialNumber, "pci9080-0"); rc = PlxPciDeviceOpen (&device, &myPlxDevice); if (rc != ApiSuccess) { printf ("\n\nErrors in opening device.\n"); printf ("Returned code is %d\n",rc); printf ("Press any key to exit....."); getch(); return; }

}

void closeVirtex() {/************************************************************/// PCI9080 Device Close/************************************************************/

// closes PCI access to the Spyder-Virtex Boardrc = PlxPciDeviceClose(myPlxDevice);if (rc != ApiSuccess) {

printf ("\n\nerrors in closing device.\n");printf ("Returned code is %d\n",rc);printf ("Press any key to exit.....");getch();return;

}else

return;}/************************************************************//* SSRAM Data and Functions*//************************************************************/const unsigned char ssram1 = 1;const unsigned char ssram2 = 2;volatile PU32 pSSRAM1 = 0x0; volatile PU32 pSSRAM2 = 0x0;

void findSSRAMs() {/************************************************************/// Get PCI Virtual Base Addresses/************************************************************/

// determines the virtual addresses of the SSRAM1 and SSRAM2 (See ssramtest.vhd)// sets the global vars: virtualAddresses and pSSRAM1 pSSRAM2// can be used only when PCI9080 Device is open

rc = PlxPciBaseAddressesGet(myPlxDevice, &virtualAddresses); if ( rc != ApiSuccess ) {

printf ("\a\nFailed to get virtual address with error code %081X",rc);exit (0);

} else {

pSSRAM1 = (PU32) virtualAddresses.Va3;pSSRAM2 = (PU32) (virtualAddresses.Va3 + 0x80000);

}}

void ssramDataBusTest(unsigned char ssramNo) {/************************************************************//* Data Bus SSRAM Test*//************************************************************/

volatile PU32 pSSRAM = 0x0;U32 valueU32 = 0x0;openVirtex();findSSRAMs();if (ssramNo == ssram1) {

pSSRAM = pSSRAM1;printf("\n SSRAM1 Data Bus Test");

} else if (ssramNo = ssram2) {printf("\n SSRAM2 Data Bus Test");pSSRAM = pSSRAM2;

} else printf("\n SSRAM is not correctly defined");for (valueU32 = 1; valueU32 != 0; valueU32 <<= 1) {

*pSSRAM = valueU32;if (*pSSRAM != valueU32) {

printf("\nError! (Address %08x : Must be %08x - really %08x",pSSRAM, valueU32, *pSSRAM);closeVirtex();


return ;}

}printf(" ... OK!");closeVirtex();return ;

} /* SSRAM Data Bus Test */

void ssramAddressBusTest(unsigned char ssramNo, U32 ssramSize32) {// ssramSize32 is the SSRAM size if 32bit words// must be power of 2

volatile PU32 pSSRAM = 0x0;const U32 testPattern1 = 0xAAAAAAAA;const U32 testPattern2 = 0x55555555;const U32 offsetFirst = 0x1;U32 offset = 0x0;U32 offset2 = 0x0;U32 offsetMask = ssramSize32 - 1;U32 ssramValue;

openVirtex();findSSRAMs();if (ssramNo == ssram1) {

pSSRAM = pSSRAM1;printf("\n SSRAM1 Address Bus Test");

} else if (ssramNo = ssram2) {printf("\n SSRAM2 Address Bus Test");pSSRAM = pSSRAM2;

} else printf("\n SSRAM is not correctly defined");

// Write 0pSSRAM[0] = testPattern1;for (offset = offsetFirst; (offset & offsetMask) != 0; offset = offset << 1 ) {

pSSRAM[offset] = testPattern1;}pSSRAM[0] = testPattern2;for (offset = offsetFirst; (offset & offsetMask) != 0; offset = offset << 1) {

ssramValue = pSSRAM[offset]; if (ssramValue != testPattern1) {

printf("\nError! (Address %08x (%08x): Must be %08x - really %08x",((U32) pSSRAM) + 4*offset, offset,testPattern1, ssramValue);closeVirtex();return ;

}}pSSRAM[0] = testPattern1;

// Write others & Check allfor (offset2 = offsetFirst; (offset2 & offsetMask) != 0; offset2 = offset2 << 1) {

pSSRAM[offset2] = testPattern2;ssramValue = pSSRAM[0x0];if (ssramValue != testPattern1) {

printf("\nError! (Address %08x (%08x) : Must be %08x - really %08x",pSSRAM, offset2, testPattern1, ssramValue);closeVirtex();return;

}for (offset = offsetFirst; (offset & offsetMask) != 0; offset = offset << 1) {

if (offset2 != offset) {ssramValue = pSSRAM[offset];if (ssramValue != testPattern1) {

printf("\nError! (Address %08x (%08x): Must be %08x - really %08x",((U32) pSSRAM) + 4*offset, offset, testPattern1, ssramValue);closeVirtex();return;}

}}pSSRAM[offset2] = testPattern1;

}printf(" ... OK!");closeVirtex();return;

} /* SSRAM Address Bus Test */

void PRPtestSSRAM(unsigned char ssramNo, U32 addrRange, U32 noOfCycles) {/************************************************************//* PRP SSRAM Test*//************************************************************/

// ssramNo : 1 - SSRAM1; 2 - SSRAM2// addrRange : size of the ssram address space under test.// Must be power of 2!!! f.e.: 0x40000 - 256k x 32// noOfCycles : PRP test lenth

volatile PU32 pSSRAM = 0x0; U32 firstPRP = 0xFFFFFFFF;


U32 valueU32;U32 nextCyclePRP;U32 cycleCount;U32 offset;U32 ssramValue;

U32 count = 0;

openVirtex();findSSRAMs();

if (ssramNo == ssram1) {pSSRAM = pSSRAM1;printf("\n SSRAM1 Pseudo Random Test");

} else if (ssramNo = ssram2) {pSSRAM = pSSRAM2;printf("\n SSRAM2 Pseudo Random Test");


nextCyclePRP = firstPRP;

for (cycleCount = 0; cycleCount < noOfCycles; cycleCount++) { valueU32 = nextCyclePRP; for (offset = 0; offset < addrRange; offset++) {

pSSRAM[offset] = valueU32;valueU32 = nextPRP(valueU32);

}

// printf("\n Reading SSRAM");valueU32 = nextCyclePRP; for (offset=0; offset < addrRange; offset++) {

ssramValue = pSSRAM[offset];if (ssramValue != valueU32) {

printf("\nError! (Address %08x : Must be %08x - really %08x",((U32) pSSRAM) + 4*offset, valueU32, ssramValue);

closeVirtex(); return;

}valueU32 = nextPRP(valueU32);

}nextCyclePRP = valueU32;

}printf(" ... OK!");closeVirtex();

}

void ssramIncDecTest(unsigned char ssramNo, U32 addrRange) {/************************************************************//* PRP SSRAM Test*//************************************************************/

volatile PU32 pSSRAM = 0x0; const U32 pattern1 = 0x1;const U32 pattern2 = 0xFFFFFFFE;U32 pattern;U32 offset;U32 ssramValue;

openVirtex();findSSRAMs();

if (ssramNo == ssram1) {pSSRAM = pSSRAM1;printf("\n SSRAM1 Device Test");

} else if (ssramNo = ssram2) {pSSRAM = pSSRAM2;printf("\n SSRAM2 Device Test");


// printf("\n Writing ppatern1 to SSRAM");for (offset = 0, pattern = pattern1 ; offset < addrRange; offset++, pattern++) {

pSSRAM[offset] = pattern;}

// printf("\n Reading SSRAM");for (offset=0, pattern = pattern1; offset < addrRange; offset++, pattern++) {

ssramValue = pSSRAM[offset];if (ssramValue!= pattern) {

printf("\nError! (Address %08x (%08x) : Must be %08x - really %08x",((U32) pSSRAM) + 4*offset, offset, pattern, ssramValue);

closeVirtex();return;

}}


// printf("\n Writing ppatern2 to SSRAM");for (offset = 0, pattern = pattern2 ; offset < addrRange; offset++, pattern--) {

pSSRAM[offset] = pattern;}

// printf("\n Reading SSRAM");for (offset=0, pattern = pattern2; offset < addrRange; offset++, pattern--) {

ssramValue = pSSRAM[offset];if (ssramValue != pattern) {

printf("\nError! (Address %08x : Must be %08x - really %08x",((U32) pSSRAM) + 4*offset, pattern, ssramValue);

closeVirtex();return;

}}printf(" ... OK!");closeVirtex();

}

void main () {

char choiceKeyDevice = ’9’;char choiceKeySize = ’1’;char choiceLength = ’1’;U32 ssramSize = 0x8000; // default 32k x 32U32 numberOfPRPCycles = 10;

printf("\n\n Spyder-Virtex SSRAM Test ");printf("\n\n SSRAM Size:");printf("\n 1 : 32k x 32");printf("\n 2 : 64k x 32");printf("\n 3 : 128k x 32");printf("\n 4 : 256k x 32");printf("\nSelect SSRAM Size (1): ");choiceKeySize = getch();switch (choiceKeySize) {

case ’1’: ssramSize = 0x8000;// 32k x 32 printf("\nSSRAM Range under Test: 32k x 32"); break;

case ’2’: ssramSize = 0x10000; // 64k x 32 printf("\nSSRAM Range under Test: 64k x 32"); break;

case ’3’: ssramSize = 0x20000; // 128k x 32 printf("\nSSRAM Range under Test: 128k x 32"); break;

default: ssramSize = 0x8000;// 32k x 32 printf("\nSSRAM Range under Test: 32k x 32"); break;

}

printf("\n\nSelect PRP Test Length (Number of Cycles): "); printf("\n1 : 1 Cycle"); printf("\n2 : 10 Cycles");

printf("\n3 : 100 Cycles" ); printf("\nx : Input Value "); printf("\nSelect PRP Length (1): ");

choiceLength = getch();switch (choiceLength) {case ’1’: printf("\n Test Length is 1 Cycle");

numberOfPRPCycles = 1;break;

case ’x’: printf("\nInput Number of Cycles:");

scanf("%d", &numberOfPRPCycles);break;

case ’2’: printf("\n Test Length is 10 Cycles");


case ’3’: printf("\n Test Length is 100 Cycles");


default: printf("\n Test Length is 1 Cycle");


}

printf("\n\n SSRAM Device");printf("\n 1 : SSRAM1");printf("\n 2 : SSRAM2");printf("\n 9 : SSRAM1 and SSRAM2");printf("\nSelect SSRAM Device (9): ");choiceKeyDevice = getch();


switch (choiceKeyDevice) {case ’1’: printf("\n\nTesting SSRAM1");

ssramDataBusTest(ssram1);ssramAddressBusTest(ssram1, ssramSize); ssramIncDecTest(ssram1, ssramSize); PRPtestSSRAM(ssram1, ssramSize, numberOfPRPCycles);break;

case ’2’: printf("\n\nTesting SSRAM2");ssramDataBusTest(ssram2);ssramAddressBusTest(ssram2, ssramSize); ssramIncDecTest(ssram2, ssramSize); PRPtestSSRAM(ssram2, ssramSize, numberOfPRPCycles);break;

default: printf("\n\nTesting SSRAM1");

ssramDataBusTest(ssram1);ssramAddressBusTest(ssram1, ssramSize); ssramIncDecTest(ssram1, ssramSize); PRPtestSSRAM(ssram1, ssramSize, numberOfPRPCycles);

printf("\n\nTesting SSRAM2");ssramDataBusTest(ssram2);ssramAddressBusTest(ssram2, ssramSize); ssramIncDecTest(ssram2, ssramSize); PRPtestSSRAM(ssram2, ssramSize, numberOfPRPCycles);break;

}

printf ("\n\nPress any key to exit");getch ();

}


Appendix C: Multiplier Demonstration ProgramFile: multiplier.vhd:------------------------------------------------------------- File name : multi.vhd-- Description : Local Bus Interface-- Date : 20.08.99-------------------------------------------------------------------------

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all; entity LocalBusInterface is Port ( LCLK : in std_logic; GNET2_GRESET_0 : in std_logic;

FRD_0 : in std_logic;FWR_0 : in std_logic;

-- Local BUS InterfaceLA : in std_logic_vector(31 downto 2) ;LBE0_0 : in std_logic;LBE1_0 : in std_logic;LBE2_0 : in std_logic;LBE3_0 : in std_logic;LD : inout std_logic_vector(31 downto 0) ;

-- LEDs FPGA_LED_0 : out std_logic);end LocalBusInterface; architecture behavioral of LocalBusInterface issignal count : integer range 0 to 4000000;signal a, b : signed(7 downto 0);signal c : signed(15 downto 0);signal LED_TMP_0 : std_logic;signal regSpaceCS : std_logic;signal reg0: std_logic_vector(31 downto 0);signal reg1 : std_logic_vector(31 downto 0);signal reg2 : std_logic_vector(31 downto 0);

begina <= signed(reg0(7 downto 0));b <= signed(reg0(23 downto 16));reg1(15 downto 0) <= conv_std_logic_vector(a * b, 16);reg1(31 downto 16) <= (others => '0');regSpaceCS <= '1' when LA(31 downto 5) = "000010000000000000000000000" else '0';

reg0WriteP : process(GNET2_GRESET_0, LCLK, FWR_0, LBE3_0, LBE2_0, LBE1_0, LBE0_0, LA, regSpacecs, LD)begin if (GNET2_GRESET_0 = '0') then reg0 <= (others => '0'); elsif (LCLK'event and LCLK = '1') then if (regSpaceCS = '1' and LA(4 downto 2) = "000" and FWR_0 = '0') then if (LBE3_0 = '0') then reg0(31 downto 24) <= LD(31 downto 24) ; end if; if (LBE2_0 = '0') then reg0(23 downto 16) <= LD(23 downto 16); end if; if (LBE1_0 = '0') then reg0(15 downto 8) <= LD(15 downto 8); end if; if (LBE0_0 = '0') then reg0(7 downto 0) <= LD(7 downto 0); end if; end if; end if; end process;

reg2WriteP : process(GNET2_GRESET_0,LCLK, FWR_0, LBE3_0, LBE2_0, LBE1_0, LBE0_0, LA, regSpacecs, LD)begin if (GNET2_GRESET_0 = '0') then reg2 <= (others => '0'); elsif (LCLK'event and LCLK = '1') then if (regSpaceCS = '1' and LA(4 downto 2) = "010" and FWR_0 = '0') then if (LBE3_0 = '0') then reg2(31 downto 24) <= LD(31 downto 24) ; end if; if (LBE2_0 = '0') then reg2(23 downto 16) <= LD(23 downto 16); end if; if (LBE1_0 = '0') then reg2(15 downto 8) <= LD(15 downto 8); end if;


if (LBE0_0 = '0') then reg2(7 downto 0) <= LD(7 downto 0); end if; end if; end if; end process;

readBufP : process (FRD_0, regSpaceCS, reg0, reg1, reg2, LA)begin if (regSpaceCS = '1' and FRD_0 = '0') then case LA(4 downto 2) is when "000" => LD <= reg0; when "001" => LD <= reg1; when "010" => LD <= reg2; when others => LD <= (others => 'Z'); end case; else LD <= (others => 'Z'); end if; end process; -- readBus

FPGA_LED_0 <= LED_TMP_0 ;LED_BLINKER_P: process (LCLK, GNET2_GRESET_0, LED_TMP_0, count) begin if (LCLK'event and LCLK = '1') then if GNET2_GRESET_0 = '0' then LED_TMP_0 <= '1'; count <= 0; else if count = 1000000 then count <= 0; LED_TMP_0 <= not LED_TMP_0; else count <= count + 1; end if; end if; end if;end process;end BEHAVIORAL;

File: multiplier.c:/****************************************************************************** * Copyright (c) 1997 - 1998 PLX Technology, Inc. * * PLX Technology Inc. licenses this software under specific terms and * conditions. Use of any of the software or derviatives thereof in any * product without a PLX Technology chip is strictly prohibited. * * PLX Technology, Inc. provides this software AS IS, WITHOUT ANY WARRANTY, * EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. PLX makes no guarantee * or representations regarding the use of, or the results of the use of, * the software and documentation in terms of correctness, accuracy, * reliability, currentness, or otherwise; and you rely on the software, * documentation and results solely at your own risk. * * IN NO EVENT SHALL PLX BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS, * LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES * OF ANY KIND. IN NO EVENT SHALL PLX’S TOTAL LIABILITY EXCEED THE SUM * PAID TO PLX FOR THE PRODUCT LICENSED HEREUNDER. * *****************************************************************************/

#include <windows.h>#include <stdio.h>#include <conio.h>#include "d:\Plx\PciSdk\Inc\pcitypes.h"#include "d:\Plx\PciSdk\Inc\plxtypes.h"#include "d:\Plx\PciSdk\Inc\PlxError.h"#include "d:\Plx\PciSdk\Inc\plx.h"#include "d:\Plx\PciSdk\Inc\PciApi.h"

/********************************************************/// PCI Data// Used to work with a PCI device /********************************************************/ RETURN_CODE rc; DEVICE_LOCATION device;

HANDLE myPlxDevice;VIRTUAL_ADDRESSES virtualAddresses;

void openVirtex() {/************************************************************/// PCI9080 Device Open/************************************************************/


// opens PCI access to the Spyder-Virtex Board// You must close the PCI access by closeVirtex before exit !

device.BusNumber = MINUS_ONE_LONG; device.SlotNumber = MINUS_ONE_LONG; device.DeviceId = MINUS_ONE_LONG; device.VendorId = MINUS_ONE_LONG; strcpy (device.SerialNumber, "pci9080-0"); rc = PlxPciDeviceOpen (&device, &myPlxDevice); if (rc != ApiSuccess) { printf ("\n\nErrors in opening device.\n"); printf ("Returned code is %d\n",rc); printf ("Press any key to exit....."); getch(); return; }

}

void closeVirtex() {/************************************************************/// PCI9080 Device Close/************************************************************/

// closes PCI access to the Spyder-Virtex Boardrc = PlxPciDeviceClose(myPlxDevice);if (rc != ApiSuccess) {

printf ("\n\nerrors in closing device.\n");printf ("Returned code is %d\n",rc);printf ("Press any key to exit.....");getch();return;

}else

return;}

/************************************************************//* Data and Functions*//************************************************************/volatile PU32 pBase = 0x0;

void findBoard() {/************************************************************/// Get PCI Virtual Base Addresses/************************************************************/

// determines the virtual addresses of the memory // sets the global vars: virtualAddresses and pBase// can be used only when PCI9080 Device is open

rc = PlxPciBaseAddressesGet(myPlxDevice, &virtualAddresses); if ( rc != ApiSuccess ) {

printf ("\a\nFailed to get virtual address with error code %081X",rc);exit (0);

} else {

pBase = (PU32) virtualAddresses.Va3; }}

void writeMemCell (U32 addrOff, U32 value32) {openVirtex();findBoard();pBase[addrOff] = value32; closeVirtex();return ;

}

U32 readMemCell(U32 addrOff){U32 memValue32;openVirtex();findBoard();memValue32 = pBase[addrOff];closeVirtex();return memValue32 ;

}

void main () {const unsigned char reg0Addr = 0;const unsigned char reg1Addr = 1;const unsigned char reg2Addr = 2;U16 operand1;U16 operand2;U32 reg0;U32 reg1;printf("\n\n Integer Multiplier Test");printf("\n\n Please download the multiplier design into the FPGA ...");

do { printf("\n\n Input Operand 1: ");


scanf("%08d", &operand1); printf(" Input Operand 2: ");

scanf("%08d", &operand2);reg0 = (operand1 << 16) | (0x0000FFFF & operand2 ) ;writeMemCell(reg0Addr, reg0);reg1 = readMemCell(reg1Addr);if (reg1 & 0x00008000)

reg1 = 0xFFFF0000 | reg1; printf("\n Result : %08d ", reg1);

} while (1);printf ("\n\nPress any key to exit");getch ();

}


Appendix D: Power Test Source Code FilesFile: t22io200.vhd-- Testsystem mit TT-FF für Syder-ASIC-X2-- Version 1.0-- VHDL, Xilinx Foundation 1.5-- Carsten OetkerLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY FFTEST IS GENERIC(MAX_IO : IN INTEGER := 20; MAX_OR : IN INTEGER := 22); PORT (GNET2_GRESET_0 : IN STD_LOGIC; PCLK : IN STD_LOGIC; FPGAPin1 : BUFFER STD_LOGIC_VECTOR(MAX_IO-1 DOWNTO 0); FPGAPin2 : BUFFER STD_LOGIC_VECTOR(MAX_IO-1 DOWNTO 0); FPGAPin3 : BUFFER STD_LOGIC_VECTOR(MAX_IO-1 DOWNTO 0); FPGAPin4 : BUFFER STD_LOGIC_VECTOR(MAX_IO-1 DOWNTO 0); FPGAPin5 : BUFFER STD_LOGIC_VECTOR(MAX_IO-1 DOWNTO 0); FPGAPin6 : BUFFER STD_LOGIC_VECTOR(MAX_IO-1 DOWNTO 0); FPGAPin7 : BUFFER STD_LOGIC_VECTOR(MAX_IO-1 DOWNTO 0); FPGAPin8 : BUFFER STD_LOGIC_VECTOR(MAX_IO-1 DOWNTO 0); FPGAPin9 : BUFFER STD_LOGIC_VECTOR(MAX_IO-1 DOWNTO 0); FPGAPin10 : BUFFER STD_LOGIC_VECTOR(MAX_IO-1 DOWNTO 0); LED_0 : OUT STD_LOGIC);

END FFTEST;

ARCHITECTURE FFTEST_behavior OF FFTEST IS

TYPE ODERVERKNUEPFUNG IS ARRAY(INTEGER Range 0 TO MAX_IO-1) OF STD_LOGIC_VECTOR(MAX_OR-1 DOWNTO 1);SIGNAL TEMP1, TEMP2, TEMP3, TEMP4, TEMP5, TEMP6, TEMP7, TEMP8, TEMP9, TEMP10 : ODERVERKNUEPFUNG;SIGNAL FlipFlops1,FlipFlops2,FlipFlops3,FlipFlops4 : STD_LOGIC_VECTOR(MAX_IO*MAX_OR-1 DOWNTO 0);SIGNAL FlipFlops5,FlipFlops6,FlipFlops7,FlipFlops8 : STD_LOGIC_VECTOR(MAX_IO*MAX_OR-1 DOWNTO 0);SIGNAL FlipFlops9,FlipFlops10 : STD_LOGIC_VECTOR(MAX_IO*MAX_OR-1 DOWNTO 0);

BEGIN

LED_0 <= ’0’; Flip_Flops1: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FlipFlops1’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FlipFlops1(I) <= ’0’; ELSE FlipFlops1(I) <= NOT(FlipFlops1(I)); END IF; END LOOP; END IF; END PROCESS; Flip_Flops2: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FlipFlops2’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FlipFlops2(I) <= ’0’; ELSE FlipFlops2(I) <= NOT(FlipFlops2(I)); END IF; END LOOP; END IF; END PROCESS; Flip_Flops3: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FlipFlops3’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FlipFlops3(I) <= ’0’; ELSE FlipFlops3(I) <= NOT(FlipFlops3(I)); END IF; END LOOP; END IF; END PROCESS;


Flip_Flops4: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FlipFlops4’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FlipFlops4(I) <= ’0’; ELSE FlipFlops4(I) <= NOT(FlipFlops4(I)); END IF; END LOOP; END IF; END PROCESS; Flip_Flops5: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FlipFlops5’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FlipFlops5(I) <= ’0’; ELSE FlipFlops5(I) <= NOT(FlipFlops5(I)); END IF; END LOOP; END IF; END PROCESS; Flip_Flops6: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FlipFlops6’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FlipFlops6(I) <= ’0’; ELSE FlipFlops6(I) <= NOT(FlipFlops6(I)); END IF; END LOOP; END IF; END PROCESS; Flip_Flops7: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FlipFlops4’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FlipFlops7(I) <= ’0’; ELSE FlipFlops7(I) <= NOT(FlipFlops7(I)); END IF; END LOOP; END IF; END PROCESS; Flip_Flops8: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FlipFlops8’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FlipFlops8(I) <= ’0’; ELSE FlipFlops8(I) <= NOT(FlipFlops8(I)); END IF; END LOOP; END IF; END PROCESS; Flip_Flops9: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FlipFlops9’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FlipFlops9(I) <= ’0’; ELSE FlipFlops9(I) <= NOT(FlipFlops9(I)); END IF; END LOOP; END IF; END PROCESS; Flip_Flops10: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FlipFlops10’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FlipFlops10(I) <= ’0’; ELSE FlipFlops10(I) <= NOT(FlipFlops10(I)); END IF;


END LOOP; END IF; END PROCESS; -------------------------------------------------------------------- OR_TEMP1: PROCESS(FlipFlops1, TEMP1) BEGIN FOR J IN 0 TO (MAX_IO-1) LOOP TEMP1(J)(1) <= FlipFlops1(J*MAX_OR) OR FlipFlops1(J*MAX_OR+1); FOR I IN 2 TO (MAX_OR-1) LOOP TEMP1(J)(I) <= TEMP1(J)(I-1) OR FlipFlops1(J*MAX_OR+I); END LOOP; END LOOP; END PROCESS; OR_TEMP2: PROCESS(FlipFlops2, TEMP2) BEGIN FOR J IN 0 TO (MAX_IO-1) LOOP TEMP2(J)(1) <= FlipFlops2(J*MAX_OR) OR FlipFlops2(J*MAX_OR+1); FOR I IN 2 TO (MAX_OR-1) LOOP TEMP2(J)(I) <= TEMP2(J)(I-1) OR FlipFlops2(J*MAX_OR+I); END LOOP; END LOOP; END PROCESS; OR_TEMP3: PROCESS(FlipFlops3, TEMP3) BEGIN FOR J IN 0 TO (MAX_IO-1) LOOP TEMP3(J)(1) <= FlipFlops3(J*MAX_OR) OR FlipFlops3(J*MAX_OR+1); FOR I IN 2 TO (MAX_OR-1) LOOP TEMP3(J)(I) <= TEMP3(J)(I-1) OR FlipFlops3(J*MAX_OR+I); END LOOP; END LOOP; END PROCESS; OR_TEMP4: PROCESS(FlipFlops4, TEMP4) BEGIN FOR J IN 0 TO (MAX_IO-1) LOOP TEMP4(J)(1) <= FlipFlops4(J*MAX_OR) OR FlipFlops4(J*MAX_OR+1); FOR I IN 2 TO (MAX_OR-1) LOOP TEMP4(J)(I) <= TEMP4(J)(I-1) OR FlipFlops4(J*MAX_OR+I); END LOOP; END LOOP; END PROCESS; OR_TEMP5: PROCESS(FlipFlops5, TEMP5) BEGIN FOR J IN 0 TO (MAX_IO-1) LOOP TEMP5(J)(1) <= FlipFlops5(J*MAX_OR) OR FlipFlops5(J*MAX_OR+1); FOR I IN 2 TO (MAX_OR-1) LOOP TEMP5(J)(I) <= TEMP5(J)(I-1) OR FlipFlops5(J*MAX_OR+I); END LOOP; END LOOP; END PROCESS; OR_TEMP6: PROCESS(FlipFlops6, TEMP6) BEGIN FOR J IN 0 TO (MAX_IO-1) LOOP TEMP6(J)(1) <= FlipFlops6(J*MAX_OR) OR FlipFlops6(J*MAX_OR+1); FOR I IN 2 TO (MAX_OR-1) LOOP TEMP6(J)(I) <= TEMP6(J)(I-1) OR FlipFlops6(J*MAX_OR+I); END LOOP; END LOOP; END PROCESS; OR_TEMP7: PROCESS(FlipFlops7, TEMP7) BEGIN FOR J IN 0 TO (MAX_IO-1) LOOP TEMP7(J)(1) <= FlipFlops7(J*MAX_OR) OR FlipFlops7(J*MAX_OR+1); FOR I IN 2 TO (MAX_OR-1) LOOP TEMP7(J)(I) <= TEMP7(J)(I-1) OR FlipFlops7(J*MAX_OR+I); END LOOP; END LOOP; END PROCESS; OR_TEMP8: PROCESS(FlipFlops8, TEMP8) BEGIN FOR J IN 0 TO (MAX_IO-1) LOOP TEMP8(J)(1) <= FlipFlops8(J*MAX_OR) OR FlipFlops8(J*MAX_OR+1); FOR I IN 2 TO (MAX_OR-1) LOOP TEMP8(J)(I) <= TEMP8(J)(I-1) OR FlipFlops8(J*MAX_OR+I); END LOOP; END LOOP; END PROCESS; OR_TEMP9: PROCESS(FlipFlops9, TEMP9)


BEGIN FOR J IN 0 TO (MAX_IO-1) LOOP TEMP9(J)(1) <= FlipFlops9(J*MAX_OR) OR FlipFlops9(J*MAX_OR+1); FOR I IN 2 TO (MAX_OR-1) LOOP TEMP9(J)(I) <= TEMP9(J)(I-1) OR FlipFlops9(J*MAX_OR+I); END LOOP; END LOOP; END PROCESS; OR_TEMP10: PROCESS(FlipFlops10, TEMP10) BEGIN FOR J IN 0 TO (MAX_IO-1) LOOP TEMP10(J)(1) <= FlipFlops10(J*MAX_OR) OR FlipFlops10(J*MAX_OR+1); FOR I IN 2 TO (MAX_OR-1) LOOP TEMP10(J)(I) <= TEMP10(J)(I-1) OR FlipFlops10(J*MAX_OR+I); END LOOP; END LOOP; END PROCESS; --------------------------------------------------------------------------

FPGA_PIN1: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FPGAPin1’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FPGAPin1(I) <= ’0’; ELSE FPGAPin1(I) <= TEMP1(I)(MAX_OR-1); END IF; END LOOP; END IF; END PROCESS; FPGA_PIN2: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FPGAPin2’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FPGAPin2(I) <= ’0’; ELSE FPGAPin2(I) <= TEMP2(I)(MAX_OR-1); END IF; END LOOP; END IF; END PROCESS; FPGA_PIN3: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FPGAPin3’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FPGAPin3(I) <= ’0’; ELSE FPGAPin3(I) <= TEMP3(I)(MAX_OR-1); END IF; END LOOP; END IF; END PROCESS; FPGA_PIN4: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FPGAPin4’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FPGAPin4(I) <= ’0’; ELSE FPGAPin4(I) <= TEMP4(I)(MAX_OR-1); END IF; END LOOP; END IF; END PROCESS; FPGA_PIN5: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FPGAPin5’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FPGAPin5(I) <= ’0’; ELSE FPGAPin5(I) <= TEMP5(I)(MAX_OR-1); END IF; END LOOP; END IF; END PROCESS; FPGA_PIN6: PROCESS(PCLK, GNET2_GRESET_0)


BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FPGAPin6’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FPGAPin6(I) <= ’0’; ELSE FPGAPin6(I) <= TEMP6(I)(MAX_OR-1); END IF; END LOOP; END IF; END PROCESS; FPGA_PIN7: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FPGAPin7’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FPGAPin7(I) <= ’0’; ELSE FPGAPin7(I) <= TEMP7(I)(MAX_OR-1); END IF; END LOOP; END IF; END PROCESS; FPGA_PIN8: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FPGAPin8’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FPGAPin8(I) <= ’0’; ELSE FPGAPin8(I) <= TEMP8(I)(MAX_OR-1); END IF; END LOOP; END IF; END PROCESS; FPGA_PIN9: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FPGAPin9’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FPGAPin9(I) <= ’0’; ELSE FPGAPin9(I) <= TEMP9(I)(MAX_OR-1); END IF; END LOOP; END IF; END PROCESS; FPGA_PIN10: PROCESS(PCLK, GNET2_GRESET_0) BEGIN IF (PCLK’event AND PCLK = ’1’) THEN FOR I IN FPGAPin10’RANGE LOOP IF (GNET2_GRESET_0 = ’0’) THEN FPGAPin10(I) <= ’0’; ELSE FPGAPin10(I) <= TEMP10(I)(MAX_OR-1); END IF; END LOOP; END IF; END PROCESS; END FFTEST_behavior;

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