microcontroller 8051 instruction set

7/27/2019 Microcontroller 8051 Instruction Set

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Contents:

IntroductionBlock Diagram and Pin Description of the 8051

Registers

Some Simple Instructions

Structure of Assembly language and Runningan 8051 program

Memory mapping in 8051

8051 Flag bits and the PSW register

Addressing Modes

16-bit, BCD and Signed Arithmetic in 8051

Stack in the 8051

LOOP and JUMP InstructionsCALL Instructions

I/O Port Programming


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Introduction

CPU

General-

Purpose

Micro-processor

RAM ROM I/O

Port

TimerSerial

COM

Port

Data Bus

Address Bus

General-Purpose Microprocessor System

CPU for Computers

No RAM, ROM, I/O on CPU chip itself

ExampleIntels x86, Motorolas 680x0

Many chips on mothers board

General-purpose microprocessor


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RAM ROM

I/O

PortTimer

Serial

COM

PortMicrocontroller

CPU

A smaller computer

On-chip RAM, ROM, I/O ports...

ExampleMotorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

A single chip

Microcontroller :


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Microprocessor

CPU is stand-alone, RAM,

ROM, I/O, timer are separate

designer can decide on theamount of ROM, RAM and

I/O ports.

expansive

versatility

general-purpose

Microcontroller

CPU, RAM, ROM, I/O and

timer are all on a single chip

fix amount of on-chip ROM,RAM, I/O ports

for applications in which cost,

power and space are critical

single-purpose

Microprocessor vs. Microcontroller


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Embedded system means the processor is embeddedinto that

application.

An embedded product uses a microprocessor or microcontroller to

do one taskonly.

In an embedded system, there is only one application software thatis typicallyburned into ROM.

Exampleprinter, keyboard, video game player

Embedded System


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1. meeting the computing needs of the task efficiently and cost

effectively

speed, the amount of ROM and RAM, the number of I/O ports

and timers, size, packaging, power consumption

easy to upgrade

cost per unit

2. availability of software development tools

assemblers, debuggers, C compilers, emulator, simulator,

technical support3. wide availability and reliable sources of the microcontrollers.

Three criteria in Choosing a Microcontroller


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Block Diagram

CPU

On-chip

RAM

On-chip

ROM for

program

code

4 I/O Ports

Timer 0

Serial

PortOSC

Interrupt

Control

External interrupts

Timer 1

Timer/Counter

Bus

Control

TxD RxDP0 P1 P2 P3

Address/Data

Counter

Inputs


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Feature 8051 8052 8031

ROM (program space in bytes) 4K 8K 0K

RAM (bytes) 128 256 128Timers 2 3 2

I/O pins 32 32 32

Serial port 1 1 1

Interrupt sources 6 8 6

Comparison of the 8051 Family Members


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Pin Description of the 8051

PDIP/Cerdip

1234567

891011121314151617181920

40393837363534

33323130292827262524232221

P1.0P1.1P1.2P1.3P1.4P1.5P1.6

P1.7RST(RXD)P3.0(TXD)P3.1

(T0)P3.4(T1)P3.5

XTAL2XTAL1

GND

(INT0)P3.2

(INT1)P3.3

(RD)P3.7(WR)P3.6

VccP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)

P0.6(AD6)P0.7(AD7)

EA/VPPALE/PROG

PSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)

8051

(8031)


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Registers

A

B

R0

R1

R3

R4

R2

R5

R7

R6

DPH DPL

PC

DPTR

PC

Some 8051 16-bit Register

Some 8-bitt Registers of

the 8051


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Memory mapping in 8051

ROM memory map in 8051 family

0000H

0FFFH

0000H

1FFFH

0000H

7FFFH

8751

AT89C51 8752AT89C52

4k

DS5000-32

8k 32k

from Atmel Corporationfrom Dallas Semiconductor


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RAM memory space allocation in the 8051

7FH

30H

2FH

20H

1FH

17H10H

0FH

07H

08H

18H

00HRegister Bank 0

(Stack) Register Bank 1

Register Bank 2

Register Bank 3

Bit-Addressable RAM

Scratch pad RAM


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RAM memory space allocation in the 8051

Total of 128 bytes of RAM

inside the 8051 are assigned addresses 00H to7FH

(a) Total of 32 bytes from locations 00H to 1FH

are set aside for register bank and the stack.

(b) Total of 16 bytes from locations 20H to 2FHare set aside for bit addressable read/writememory.

(c) Total of 80 bytes from locations 30H to 7FH

are used for read and write storage, calledScratch pad area used for storing data.


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8051 Flag bits and the PSW register PSW Register

CY AC F0 RS1 OVRS0 P--

CYPSW.7Carry flag

ACPSW.6Auxiliary carry flag

--PSW.5Available to the user for general purpose

RS1PSW.4Register Bank selector bit 1

RS0PSW.3Register Bank selector bit 0OVPSW.2Overflow flag

--PSW.1User define bit

PPSW.0Parity flag Set/Reset odd/even parity

RS1 RS0 Register Bank Address

0 0 0 00H-07H

0 1 1 08H-0FH

1 0 2 10H-17H

1 1 3 18H-1FH


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Instructions that Affect Flag Bits:

Note: X can be 0 or 1


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8051 instruction set

MOV copy the data from data memory

MOVC copy the data from code memory

MOVX - copy the data from external

memory


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MOV A,#data(8bit) load accumulator with 8-

bit data

eg: MOV A,#16hA 16h

MOV A,10h the data from RAM location 10

will be loaded to accumulator.

A 34h

12

11

10 34

0F0E


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MOV Rn,# data

Eg: MOV R4,#56h

R4 56h

MOV 03h, # 45h

03h 45h (03 0r R3 is address)

MOV A,Rn

Eg: MOV A,R3load Accumulator with thecontent of R3

MOV Rn,ARn A


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MOV addr(8),addr(8)

To represent data starting with alphabets

from A to F, should be added 0 as prefix

Eg : MOV 00h,# 0AEh

MOV addr(8), A

Addr A

MOV Rn,Rn is invalid


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[Rp is R0 or R1)

MOV A, @Rn The content of memory

location whose address is stored in theregister Rp will be moved to the

accumulator.

MOV addr(8),@Rp

MOV @Rp, #data

MOV @Rp, A

MOV @Rp,addr(8)

DATA POINTER


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DATA POINTER

The Data Pointer (DPTR) is the 8051s only user-accessable 16-bit (2-byte) register. The

Accumulator, "R" registers, and "B" register are all1-byte values.

DPTR, as the name suggests, is used to point todata. It is used by a number of commands which

allow the 8051 to access external memory. Whenthe 8051 accesses external memory it will accessexternal memory at the address indicated by DPTR.

While DPTR is most often used to point to data inexternal memory, many programmers often take

advantage of the fact that its the only true 16-bitregister available. It is often used to store 2-bytevalues which have nothing to do with memorylocations.


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MOVX Function: Move Data To/From External Memory

(XRAM)

Syntax: MOVX operand1,operand2 Instructions

MOVX @DPTR,A

MOVX @Rp, A

MOVX A,@DPTR MOVX A, @Rp

Description: MOVX moves a byte to or from ExternalMemory into or from the Accumulator.

Ifoperand1 is @DPTR, the Accumulator is moved to the16-bit External Memory address indicated by DPTR. Thisinstruction uses both P0 (port 0) and P2 (port 2) tooutput the 16-bit address and data.


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MOVX

Ifoperand2is DPTR then the byte is movedfrom External Memory into the Accumulator.

Ifoperand1 is @R0 or @R1, the Accumulator is

moved to the 8-bit External Memory address

indicated by the specified Register. Thisinstruction uses only P0 (port 0) to output the 8-

bit address and data.

P2 (port 2) is not affected. Ifoperand2is @R0 or@R1 then the byte is moved from External

Memory into the Accumulator.


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MOVC Operation: MOVC

Function: Move Code Byte to Accumulator

Syntax: MOVC A, @A+register

Instructions :

MOVC A,@A+DPTR

MOVC A,@A+PC Description: MOVC moves a byte from Code

Memory into the Accumulator. The CodeMemory address from which the byte will bemoved is calculated by summing the value of the

Accumulator with either DPTR or the ProgramCounter (PC).

In the case of the Program Counter, PC is firstincremented by 1 before being summed with the

Accumulator.


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ARITHMETIC INSTRUCTIONS

All addition is done with the A register as thedestination of the result

ADD A,#data(8) A+data(8) A

ADD A, Rn(n=0 to 7) add A and the content ofRn, result is in A

A+addr(8) A ADD A,add(8) - add A and the content of

address, result is in A

A+addr(8) A

ADD A, @Rp (Rp is R0 or R1) add the contentsof address in Rp ; put result in A


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ADDC add with carry

ADDC A,#data(8)A + data(8)+ CY A

ADDC A,Rn

A + Rn+CY A

ADDC A,add(8)

A + addr(8)+CY A

ADDC A,@Rp add the content of A, thecontent of indirect address in Rp,and the C flag;

put result in A

SUBTRACTION


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SUBTRACTION

Subtraction can be done by taking the

twos complement of the number to be

subtracted, the subtrahend and adding itto the other number.

The 8051 has commands to perform the

direct subtraction of two unsigned andsigned numbers.

Like addition Register A is the destination

address for the subtraction. Subtraction always subtract the carry flag

(borrow) as part of the operation

S bt ti


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Subtraction SUBB A,#data(8)

A - data(8)- CY A

Subtract immediate data(8) and the C Flag fromA and the result will be in A.

SUBB A, add(8)

A add(8) - CY A

SUBB A, Rn

A- Rn- CY A

SUBB A, @Rp: Subtract the contents of theaddress in Rp and the C Flag from A and resultis stored in A


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Unsigned subtraction In the above instruction C Flag is always

subtracted from A along with the source byte. It must be set to 0, if programmer does not want

the carry Flag to be included in the subtraction.

In a multibyte subtraction the carry flag has to be

cleared for first byte and then included for thesubsequent higher byte operations.

The result will be in the true form, with no borrowif the source number is smaller than A.

The result will be in Twos complement form,with borrow if the source is larger than A.

All bits are considered as the magnitude.


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Multiplication and Division The 8051 has the capability to perform

8-bit integer multiplication and division using A and Bregisters.

Multiplication: Multiplication use registers A and B asboth source and destination addresses.

MUL AB multiply A by B; put the lower byte of

the product in A, and the higher order byte in B The unsigned number in register A is multiplied with the

unsigned number in register B and the result will bestored in A, if the product is less than FF h.

If the product is greater than FF h, the OV Flag will beSet. The higher order bytes will be stored in register Band lower order bytes in register A.

The carry flag is always cleared to 0.


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Example

MOV A, #7B H ;A=7Bh

MOV 0F0h,#02h ;B=02h

MUL AB ;A=F6h and B=00h,OV=0MOV B, #0FEh ;B= FEh

MUL AB ;A=14h, B=F4h,OV Flag=1


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Division Division operation use registers A and B

as both the source and destinationaddresses for the operation.

DIV AB Divide A by B; the integer

part of quotient in register A and theinteger part of the remainder in B.

The OV flag is cleared to 0 unless B holds

00h before the DIV. Then the overflow flagis set to 1 to show division by 0. This

division is undefined.

The carry flag is always reset.


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Example

MOV A,#0FFh - A = FFhMOV 0F0h,#2Ch - B = 2Ch

DIV AB - A = 05h and B = 23h



DIV AB - A = ? and B = ?; OV = 1

Decimal arithmetic


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Decimal arithmetic

Most of the real world application which

involves interacting with the humanbeings, which insists the numbering to bedone in decimal number system.

Four bits are required to represent thedecimal 0-9 (0000h-1001h)

DA A Adjust the sum of two packedBCD numbers found in A register;

result in A The DA A will work with the instruction

ADDC or ADD.

INCREMENT


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Wednesday, October 23,

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INCREMENT Operation: INC

No flags are affected(C,AC,OV)

Function: Increment Register Instructions

INC A

INC Rn

INC @Rp INC addr

INC DPTR

Description: INC increments the value of

registeror content of address by 1. In the case of "INC DPTR", the value two-byte

unsigned integer value of DPTR is incremented.

Decrement


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Decrement

Operation:DEC

Instructions DEC A

DEC Rn

DEC @Rp DEC addr(8)

Description: DEC decrements the value

ofregisteror the content of address by 1.

Cl


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Clear

Operation:CLR

Instructions

CLR addr(8) Clear the content of address

specified

CLR C Clear carry flag CLR A Clear the content of accumulator

Description: CLR clears (sets to 0) all the bit(s)

of the indicated register. If the register is a bit

(including the carry bit), only the specified bit is

affected. Clearing the Accumulator sets the

Accumulators value to 0.


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Logical Instruction Operation: CPL

Function: Complement Syntax: CPL operand

Instructions

CPL A - complement each bit of A CPL C - complement Carry

CPL addr(8) - complement each bit of thecontent of address specified.

AND operation


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AND operation Operation: ANL

Function: Bitwise AND

Instructions ANL addr(8), AAND each bit of A with same bit

of direct RAM address and store the result in addr(8)

ANL A,addr(8) -AND each bit of A with same bit

of direct RAM address and store the result in A ANL addr(8), #data

ANL A, #data

ANL A, Rn

ANL A, @Rp ANL A,R0

ANL C, bit addr

XOR


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XOR Operation: XRL

Function: Bitwise Exclusive OR

Instructions XRL addr(8), A

XRL addr(8), #data

XRL A, #data

XRL A, addr(8)

XRL A, @Rp

Description: XRL does a bitwise "EXCLUSIVEOR" operation between operand1 and operand2,leaving the resulting value in operand1. Thevalue of operand2 is not affected.


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OR Operation Operation: ORL

Function: Bitwise OR

Instructions

ORL addr(8), A

ORL addr(8), #data

ORL A, #data ORL A, addr(8)

ORL A,@R0

ORL C, bit

Description: ORL does a bitwise "OR" operationbetween operand1 and operand2, leaving the resultingvalue in operand1. The value ofoperand2is notaffected.

RR RL RRC RLC A


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RRRLRRCRLC A

EXAMPLE:

RR A

RR:

RRC:

RL:

RLC:

C

C


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ROTATE LEFT Operation: RL

Function: Rotate Accumulator Left

Syntax: RL A

Description: Shifts the bits of the Accumulator to theleft. The left-most bit -bit 7 of the Accumulator is loadedinto bit0.

Operation: RLC Function: Rotate Accumulator Left Through Carry

Syntax: RLC A

Description: Shifts the bits of the Accumulator to the

left. The left-most bit (bit 7) of the Accumulator is loadedinto the Carry Flag, and the original Carry Flag is loadedinto bit 0 of the Accumulator. This function can be usedto quickly multiply a byte by 2.

ROTATE RIGHT


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ROTATE RIGHT Operation: RR

Function: Rotate Accumulator Right

Syntax: RR A

Description: Shifts the bits of the Accumulator to theright. The right-most bit -bit 0 of the Accumulator isloaded into bit7.

Operation: RRC Function: Rotate Accumulator Right Through Carry

Syntax: RRC A

Description: Shifts the bits of the Accumulator to the

right. The right-most bit (bit 0) of the Accumulator isloaded into the Carry Flag, and the original Carry Flag isloaded into bit 7. This function can be used to quicklydivide a byte by 2.


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LOOP and JUMP Instructions

JZ Jump if A=0

JNZ Jump if A/=0

DJNZ Decrement and jump if A/=0

CJNE A, byte Jump if A/=byte

CJNE reg, #data Jump if byte/=#data

JC Jump if CY=1

JNC Jump if CY=0

JB Jump if bit=1

JNB Jump if bit=0

JBC Jump if bit=1 and clear bit

Conditional Jumps :


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LJMP(long jump)

LJMP is an unconditional jump. It is a 3-byte instruction. Itallows a jump to any memory location from 0000 to FFFFH.

AJMP(absolute jump)

In this 2-byte instruction, It allows a jump to any memorylocation within the 2k block of program memory.

SJMP(short jump)

In this 2-byte instruction. The relative address range of 00-FFH is divided into forward and backward jumps, that is ,

within -128 to +127 bytes of memory relative to the address ofthe current PC.


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JMP

Operation: JMP Function: Jump to Data Pointer +

Accumulator

Syntax: JMP @A+DPTR Description: JMP jumps unconditionally

to the address represented by the sum of

the value of DPTR and the value of theAccumulator.

CJNE


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CJNE Operation: CJNE

Function: Compare and Jump If Not Equal

Syntax: CJNE operand1,operand2,reladdr CJNE A, #data ,relative-address

Compare the content of the accumulator and the data andbranch to the relative address if not equal

CJNE A, addr(8),relative-address

CJNE @Rp, #data, relative-address

Description: CJNE compares the value ofoperand1and operand2and branches to the indicated relativeaddress ifoperand1 and operand2are not equal. If the

two operands are equal program flow continues with theinstruction following the CJNE instruction.

The Carry bit (C) is set ifoperand1 is less thanoperand2, otherwise it is cleared.


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JNC

Operation: JNC

Function: Jump if Carry Not Set

Syntax: JNC reladdr

Description: JNC branches to the

address indicated by reladdrif the carry bit

is not set. If the carry bit is set program

execution continues with the instruction

following the JNC instruction.


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JC

Operation: JC

Function:Jump if Carry Set

Syntax:JC reladdr

Description: JC will branch to the address

indicated by reladdrif the Carry Bit is set.

If the Carry Bit is not set program

execution continues with the instruction

following the JC instruction.


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JNZ

Operation: JNZ

Function: Jump if Accumulator Not Zero

Syntax:JNZ reladdr

Description: JNZ will branch to theaddress indicated by reladdrif the

Accumulator contains any value except 0.

If the value of the Accumulator is zeroprogram execution continues with theinstruction following the JNZ instruction.


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JZ

Operation: JZ

Function:Jump if Accumulator Zero

Syntax:JZ reladdr

Description: JZ branches to the addressindicated by reladdrif the Accumulatorcontains the value 0. If the value of the

Accumulator is non-zero programexecution continues with the instructionfollowing the JZ instruction.


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JNB

Operation: JNB

Function: Jump if Bit Not Set

Syntax: JNB bit addr, reladdr

Description: JNB will branch to the

address indicated by relative address if the

indicated bit is not set. If the bit is set

program execution continues with the

instruction following the JNB instruction.


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JB

Operation: JB

Function:Jump if Bit Set

Syntax:JB bit addr, reladdr

Description: JB branches to the address

indicated by relative address if the bit

indicated by bit addris set. If the bit is not

set program execution continues with the

instruction following the JB instruction.


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JBC

Operation: JBC

Function: Jump if Bit Set and Clear Bit

Syntax: JB bit addr, reladdr

Description: JBC will branch to the addressindicated by reladdrif the bit indicated by bit

addris set. Before branching to reladdrthe

instruction will clear the indicated bit. If the bit is

not set program execution continues with the

instruction following the JBC instruction.


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SETB

Operation: SETB

Function: Set Bit

Syntax: SETB bit addr

Description: Sets the specified bit.


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SWAP

Operation: SWAP

Function: Swap Accumulator Nibbles

Syntax: SWAP A

Description:

SWAP swaps bits 0-3 of the Accumulator

with bits 4-7 of the Accumulator. This instruction is identical to executing

"RR A" or "RL A" four times.

Stack in the 8051


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Stack in the 8051

The register used toaccess the stack iscalled SP (stackpointer) register.

The stack pointer inthe 8051 is only 8 bitswide, which meansthat it can take value00 to FFH. When 8051powered up, the SPregister contains value07.

7FH

30H

2FH

20H

1FH

17H

10H

0FH

07H08H

18H

00HRegister Bank 0


Register Bank 2

Register Bank 3

Bit-Addressable RAM

Scratch pad RAM


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PUSH Operation: PUSH

Function: Push Value Onto Stack

PUSH addr(8);

Description: PUSH "pushes" the value of

the specified addr(8) onto the stack. PUSHfirst increments the value of the StackPointer by 1, then takes the value stored in

internal RAM addrand stores it in InternalRAM at the location pointed to by theincremented Stack Pointer.


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POP

Operation: POP

Function: Pop Value From Stack

Syntax: POP

POP addr(8) Description: POP "pops" the last value placed

on the stack into the internal RAM addressspecified. In other words, POP will load addr(8)

with the value of the Internal RAM addresspointed to by the current Stack Pointer. Thestack pointer is then decremented by 1.


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CALL Instructions

Another control transfer instruction is the CALL instruction,

which is used to call a subroutine.

LCALL(long call)

This 3-byte instruction can be used to call subroutineslocated anywhere within the 64Kbyte address space

of the 8051.

ACALL (absolute call)

ACALL is 2-byte instruction. The target address of thesubroutine must be within 2Kbyte range.


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RETURN

Operation: RET Function: Return From Subroutine

Syntax: RET

Description: RET is used to return from asubroutine previously called by LCALL or

ACALL.

Program execution continues at the addressthat is calculated by popping the topmost 2 bytes

off the stack. The most-significant-byte is popped off the stack

first, followed by the least-significant-byte.


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RETURN FROM INTERRUPT

Operation:RETI Function:Return From Interrupt

Description: RETI is used to return from an interruptservice routine.

RETI first enables interrupts of equal and lower prioritiesto the interrupt that is terminating.

Program execution continues at the address that iscalculated by popping the topmost 2 bytes off the stack.The most-significant-byte is popped off the stack first,followed by the least-significant-byte.

RETI functions identically to RET if it is executed outsideof an interrupt service routine.


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XCH

Function: Exchange Bytes

Syntax: XCH A, Rn

XCH A, @Rp

XCH A, addr

Description: Exchanges the value of the

Accumulator with the value contained in

register.

XCHDF ti E h Di it


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Function: Exchange Digit

Syntax: XCHD A,@Rp

XCHD A,@R0 XCHD A,@R1

Description: Exchanges bits 0-3 of theAccumulator with bits 0-3 of the Internal RAM

address pointed to indirectly by R0 or R1. Bits 4-7 of each register are unaffected.

Eg: RAM location 40H = 97H

MOV A,#12H

MOV R1,#40H

XCHD A,@R1

After execution A = 17H and RAM location 40H =92H


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Operation: NOP

Function: None, waste time Syntax: No Operation

Description:NOP, as its name suggests,

causes No Operation to take place for onemachine cycle.

NOP is generally used only for timing

purposes. Absolutely no flags or registersare affected.


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Addressing Modes

Immediate

Register

Direct Register Indirect

Indexed


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Immediate Addressing Mode

MOV A,#65HMOV A,#A

MOV R6,#65H

MOV DPTR,#2343H

MOV P1,#65H

Example :

Num EQU 30

MOV R0,Num

MOV DPTR,#data1

ORG 100H

data1: db IRAN


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Register Addressing Mode

MOV Rn, A ;n=0,..,7

ADD A, Rn

MOV DPL, R6

MOV DPTR, A

MOV Rn, Rn

Direct Addressing Mode


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gAlthough the entire of 128 bytes of RAM can be accessedusing direct addressing mode, it is most often used to accessRAM loc. 307FH.

MOV R0, 40H

MOV 56H,A

MOV A, 4 ; MOV A, R4

MOV 6, 2 ; copy R2 to R6; MOV R6,R2 is invalid !

SFR register and their address

MOV 0E0H, #66H ; MOV A,#66H

MOV 0F0H, R2 ; MOV B, R2

MOV 80H,A ; MOV P0,A

Bit Addressable

Page 359,360

Register Indirect Addressing Mode


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g g In this mode, register is used as a pointer to the data.

MOV A,@Rp ; move content of RAM loc.Where address is held by Ri into A

( i=0 or 1 )

MOV @R1,B

In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBBinsructions.

Example:

Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAMlocation starting at 59h.

Solution:

MOV R0,37h ; source pointer

MOV R1,59h ; dest pointer

MOV R2,10 ; counter

L1: MOV A,@R0

MOV @R1,AINC R0

INC R1

DJNZ R2,L1

jump

Indexed Addressing Mode And On-Chip


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Indexed Addressing Mode And On-Chip

ROM Access

This mode is widely used in accessing data elementsof look-up table entries located in the program (code)space ROM at the 8051

MOVC A,@A+DPTR

A= content of address A +DPTR from ROM

Note:

Because the data elements are stored in the program(code ) space ROM of the 8051, it uses the instructionMOVC instead of MOV. The C means code.


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Pins of 80511/4

Vccpin 40

Vcc provides supply voltage to the chip.

The voltage source is +5V.

GNDpin 20ground

XTAL1 and XTAL2pins 19,18

These 2 pins provide external clock.

Way 1using a quartz crystal oscillator

Way 2using a TTL oscillator

Example 4-1 shows the relationship between XTAL and themachine cycle.


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Pins of 80512/4

RSTpin 9reset

It is an input pin and is active highnormally low.

The high pulse must be high at least 2 machine cycles.

It is a power-on reset.

Upon applying a high pulse to RST, the microcontroller willreset and all values in registers will be lost.

Reset values of some 8051 registers

Way 1Power-on reset circuit

Way 2Power-on reset with debounce


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Pins of 80513/4

/EApin 31external access

There is no on-chip ROM in 8031 and 8032 .

The /EA pin is connected to GND to indicate the code is stored

externally.

/PSEN ALE are used for external ROM. For 8051, /EA pin is connected to Vcc.

/ means active low.

/PSENpin 29program store enable

This is an output pin and is connected to the OE pin of the ROM. See Chapter 14.


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Pins of 80514/4

ALEpin 30address latch enable

It is an output pin and is active high.

8051 port 0 provides both address and data.

The ALE pin is used for de-multiplexing the address and data by

connecting to the G pin of the 74LS373 latch. I/O port pins

The four ports P0, P1, P2, and P3.

Each port uses 8 pins.

All I/O pins are bi-directional.


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Figure 4-2 (a). XTAL Connection to 8051

C2

30pF

C1

30pF

XTAL2

XTAL1

GND

Using a quartz crystal oscillator

We can observe the frequency on the XTAL2 pin.


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Figure 4-2 (b). XTAL Connection to an External Clock Source

N

C

EXTERNAL

OSCILLATORSIGNAL

XTAL2

XTAL1

GND

Using a TTL oscillator

XTAL2 is unconnected.


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Example :

Find the machine cycle for

(a) XTAL = 11.0592 MHz

(b) XTAL = 16 MHz.

Solution:

(a) 11.0592 MHz / 12 = 921.6 kHz;

machine cycle = 1 / 921.6 kHz = 1.085 s

(b) 16 MHz / 12 = 1.333 MHz;machine cycle = 1 / 1.333 MHz = 0.75 s


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RESET Value of Some 8051 Registers:

0000DPTR

0007SP

0000PSW

0000B0000ACC

0000PC

Reset ValueRegister

RAM are all zero.


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Figure 4-3 (a). Power-On RESET Circuit

30 pF

30 pF

8.2 K

10 uF

+

Vcc

11.0592 MHz

EA/VPP

X1

X2

RST

31

19

18

9

i 4 3 (b) O S i h b


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Figure 4-3 (b). Power-On RESET with Debounce

EA/VPP

X1

X2RST

Vcc

10 uF

8.2 K

30 pF

9

31

Pi f I/O P


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Pins of I/O Port

The 8051 has four I/O ports

Port 0pins 32-39P0P0.0P0.7

Port 1pins 1-8 P1P1.0P1.7



Each port has 8 pins.

Named P0.XX=0,1,...,7, P1.X, P2.X, P3.X

ExP0.0 is the bit 0LSBof P0

ExP0.7 is the bit 7MSBof P0

These 8 bits form a byte.

Each port can be used as input or output (bi-direction).



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MOV dest,source ; dest = source

MOV A,#72H ;A=72H

MOV A, #r ;A=r OR72H

MOV R4,#62H ;R4=62H

MOV B,0F9H ;B=the content of F9th byte of RAM

MOV DPTR,#7634H

MOV DPL,#34H

MOV DPH,#76H

MOV P1,A ;mov A to port 1

Note 1:

MOV A,#72H MOV A,72H

After instruction MOV A,72H the content of72th byte of RAM will replace in Accumulator.

8086 8051

MOV AL,72H MOV A,#72H

MOV AL,r MOV A,#r

MOV BX,72HMOV AL,[BX] MOV A,72H

Note 2:

MOV A,R3 MOV A,3


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ADD A, Source ;A=A+SOURCE

ADD A,#6 ;A=A+6

ADD A,R6 ;A=A+R6

ADD A,6 ;A=A+[6] or A=A+R6

ADD A,0F3H ;A=A+[0F3H]

SETB bit ; bit=1


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;

CLR bit ; bit=0

SETB C ; CY=1SETB P0.0 ;bit 0 from port 0 =1

SETB P3.7 ;bit 7 from port 3 =1

SETB ACC.2 ;bit 2 from ACCUMULATOR =1

SETB 05 ;set high D5 of RAM loc. 20h

Note:

CLR instruction is as same as SETB

i.e:

CLR C ;CY=0

But following instruction is only for CLR:

CLR A ;A=0

Bit Addressable

Page 359,360

SUBB A,source ;A=A-source-CY


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SUBB A,source ;A A source CY

SETB C ;CY=1SUBB A,R5 ;A=A-R5-1

ADC A,source ;A=A+source+CY

SETB C ;CY=1

ADC A,R5 ;A=A+R5+1

DEC byte ;byte=byte-1


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y ; y y

INC byte ;byte=byte+1

INC R7

DEC ADEC 40H ; [40]=[40]-1

CPL A ;1s complementExample:

MOV A,#55H ;A=01010101 B

L01: CPL AMOV P1,A

ACALL DELAY

SJMP L01

NOP & RET & RETI

All are like 8086 instructions.

CALL

ANL ORL XRL


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ANL - ORL - XRL

EXAMPLE:MOV R5,#89H

ANL R5,#08H

RRRLRRCRLC A

EXAMPLE:RR A

Structure of Assembly language


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Structure of Assembly language

and Running an 8051 program

ORG 0H

MOV R5,#25H

MOV R7,#34HMOV A,#0

ADD A,R5

ADD A,#12H

HERE: SJMP HEREEND

EDITOR

PROGRAM

ASSEMBLER

PROGRAM

LINKER

PROGRAM

OH

PROGRAM

Myfile.asm

Myfile.obj

Other obj fileMyfile.lst

Myfile.abs

Myfile.hex


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Example:

MOV A,#38H

ADD A,#2FH

38 00111000

+2F +00101111---- --------------

67 01100111

CY=0 AC=1 P=1

Example:

MOV A,#88H

ADD A,#93H

88 10001000

+93 +10010011

---- --------------

11B 00011011

CY=1 AC=0 P=0

Example:

MOV A,#9CH

ADD A,#64H

9C 10011100

+64 +01100100

---- --------------

100 00000000

CY=1 AC=1 P=0

Example:

Assuming that ROM space starting at 250h contains Hello., write a program to transfer the


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Assuming that ROM space starting at 250h contains Hello. , write a program to transfer thebytes into RAM locations starting at 40h.

Solution:

ORG 0

MOV DPTR,#MYDATAMOV R0,#40H

L1: CLR A

MOVC A,@A+DPTR

JZ L2

MOV @R0,A

INC DPTR

INC R0SJMP L1

L2: SJMP L2

;-------------------------------------

ORG 250H

MYDATA: DB Hello,0

END

Notice the NULL character ,0, as end of string and how we use the JZ instruction todetect that.

Example:

Write a program to get the x value from P1 and send x2 to P2 continuously


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Write a program to get the x value from P1 and send x to P2, continuously .

Solution:

ORG 0

MOV DPTR, #TAB1MOV A,#0FFH

MOV P1,A

L01:

MOV A,P1

MOVC A,@A+DPTR

MOV P2,A

SJMP L01

;----------------------------------------------------

ORG 300H

TAB1: DB 0,1,4,9,16,25,36,49,64,81

END

16-bit, BCD and Signed


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Arithmetic in 8051

Exercise:

Write a program to add n 16-bit number. Get nfrom port 1. And sent Sum to LCD

a) in hex

b) in decimal

Write a program to subtract P1 from P0 and sendresult to LCD

(Assume that ACAL DISP display A to LCD )

MUL & DIV


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MUL & DIV

MUL AB ;B|A = A*BMOV A,#25H

MOV B,#65H

MUL AB ;25H*65H=0E99;B=0EH, A=99H

MUL AB ;A = A/B, B = A mod B

MOV A,#25

MOV B,#10

MUL AB ;A=2, B=5

Stack in the 8051


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Stack in the 8051

The register used to accessthe stack is called SP (stack

pointer) register.

The stack pointer in the

8051 is only 8 bits wide,which means that it can takevalue 00 to FFH. When8051 powered up, the SPregister contains value 07.

7FH

30H

2FH

20H

1FH

17H

10H

0FH

07H

08H

18H

00HRegister Bank 0


Register Bank 2

Register Bank 3

Bit-Addressable RAM

Scratch pad RAM

Example:


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p

MOV R6,#25H

MOV R1,#12H

MOV R4,#0F3H

PUSH 6PUSH 1

PUSH 4

0BH

0AH

09H

08H

Start SP=07H

25

0BH

0AH

09H

08H

SP=08H

F3

12

25

0BH

0AH

09H

08H

SP=08H

12

25

0BH

0AH

09H

08H

SP=09H



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DJNZ:

Write a program toclear ACC, then

add 3 to the accumulator ten time

Solution:

MOV A,#0;

MOV R2,#10

AGAIN: ADD A,#03

DJNZ R2,AGAING ;repeat until R2=0 (10 times)

MOV R5,A

Other conditional jumps :


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j p

JZ Jump if A=0

JNZ Jump if A/=0

DJNZ Decrement and jump if A/=0

CJNE A,byte Jump if A/=byte

CJNE reg,#data Jump if byte/=#data

JC Jump if CY=1

JNC Jump if CY=0

JB Jump if bit=1

JNB Jump if bit=0

JBC Jump if bit=1 and clear bit


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SJMP and LJMP:

LJMP(long jump)LJMP is an unconditional jump. It is a 3-byte instruction inwhich the first byte is the opcode, and the second and third

bytes represent the 16-bit address of the target location. The20byte target address allows a jump to any memory locationfrom 0000 to FFFFH.

SJMP(short jump)

In this 2-byte instruction. The first byte is the opcode and thesecond byte is the relative address of the target location. The

relative address range of 00-FFH is divided into forward andbackward jumps, that is , within -128 to +127 bytes of memoryrelative to the address of the current PC.

CJNE JNC


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CJNE , JNC

Exercise:

Write a program that compare R0,R1.

If R0>R1 then send 1 to port 2,

else if R0


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CALL Instructions

Another control transfer instruction is the CALLinstruction, which is used to call a subroutine.

LCALL(long call)In this 3-byte instruction, the first byte is the opcode

an the second and third bytes are used for the address

of target subroutine. Therefore, LCALL can be used

to call subroutines located anywhere within the 64Kbyte address space of the 8051.

ACALL ( b l t ll)


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ACALL (absolute call)

ACALL is 2-byte instruction in contrast to LCALL,which is 13 bytes. Since ACALL is a 2-byte instruction,the target address of the subroutine must be within 2K

bytes address because only 11 bits of the 2 bytes are used

for the address. There is no difference between ACALLand LCALL in terms of saving the program counter onthe stack or the function of the RET instruction. The onlydifference is that the target address for LCALL can be

anywhere within the 64K byte address space of the 8051while the target address of ACALL must be within a 2K-byte range.

I/O Port Programming


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g g

Port 1pins 1-8

Port 1 is denoted by P1.

P1.0 ~ P1.7

We use P1 as examples to show the operations on ports.

P1 as an output port (i.e., write CPU data to the external pin)

P1 as an input port (i.e., read pin data into CPU bus)

A Pin of Port 1


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A Pin of Port 1

8051 IC

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPUbus

M1

P1.XpinP1.X

TB1

TB2

P0.x

Hardware Structure of I/O Pin


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Hardware Structure of I/O Pin

Each pin of I/O ports Internal CPU buscommunicate with CPU

A D latch store the value of this pin

D latch is controlled by Write to latch

Write to latch1write data into the D latch

2 Tri-state buffer

TB1: controlled by Read pin

Read pin1really read the data present at the pin

TB2: controlled by Read latch Read latch1read value from internal latch

A transistor M1 gate

Gate=0: open

Gate=1: close

Tri-state Buffer


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Tri state Buffer

Output Input

Tri-state control

(active high)

L H Low

Highimpedance

(open-circuit)HH

L H

Writing 1 to Output Pin P1 X


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Writing 1 to Output Pin P1.X

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPUbus

M1

P1.XpinP1.X

8051 IC

2. output pin is

Vcc1. write a 1 to the pin1

0 output 1

TB1

TB2

Writing 0 to Output Pin P1 X


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Writing 0 to Output Pin P1.X

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPUbus

M1

P1.X

pinP1.X

8051 IC

2. output pin is

ground1. write a 0 to the pin0

1 output 0

TB1

TB2

Port 1 as OutputWrite to a Port


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Port 1 as OutputWrite to a Port

Send data to Port 1

MOV A,#55H

BACK: MOV P1,A

ACALL DELAYCPL A

SJMP BACK

Let P1 toggle.

You can write to P1 directly.

Reading Input v.s. Port Latch


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Reading Input v.s. Port Latch

When reading ports, there are two possibilities

Read the status of the input pin.from external pin value

MOV A, PX

JNB P2.1, TARGET ; jump if P2.1 is not set

JB P2.1, TARGET ; jump if P2.1 is set

Figures C-11, C-12 Read the internal latch of the output port.

ANL P1, A ; P1 P1 AND A

ORL P1, A ; P1 P1 OR A

INC P1 ; increase P1 Figure C-17

Table C-6 Read-Modify-Write Instruction (or Table 8-5)

See Section 8.3

Reading High at Input Pin


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Reading High at Input Pin

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pin

P1.X

8051 IC

2. MOV A,P1

external pin=High1. write a 1 to the pin MOV

P1,#0FFH

1

0

3. Read pin=1 Read latch=0

Write to latch=1

1

TB1

TB2

Reading Low at Input Pin


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Reading Low at Input Pin

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pin

P1.X

8051 IC

2. MOV A,P1

external pin=Low1. write a 1 to the pin

MOV P1,#0FFH

1

0

3. Read pin=1 Read latch=0

Write to latch=1

0

TB1

TB2

Port 1 as InputRead from Port


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Port 1 as InputRead from Port

In order to make P1 an input, the port must be programmed by writing 1 toall the bit.

MOV A,#0FFH ;A=11111111B

MOV P1,A ;make P1 an input port

BACK: MOV A,P1 ;get data from P0

MOV P2,A ;send data to P2

SJMP BACK

To be an input port, P0, P1, P2 and P3 have similar methods.

Instructions For Reading an Input Port


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Instructions For Reading an Input Port

Mnemonics Examples Description

MOV A,PX MOV A,P2Bring into A the data at P2

pins

JNB PX.Y,.. JNB P2.1,TARGET Jump if pin P2.1 is low

JB PX.Y,.. JB P1.3,TARGET Jump if pin P1.3 is high

MOV C,PX.Y MOV C,P2.4 Copy status of pin P2.4 to CY

Following are instructions for reading external pins of ports:

Reading Latch


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g

Exclusive-or the Port 1MOV P1,#55H ;P1=01010101

ORL P1,#0F0H ;P1=11110101

1. The read latch activates TB2 and bring the data from the Q latch into

CPU.

Read P1.0=0

2. CPU performs an operation.

This data is ORed with bit 1 of register A. Get 1.

3. The latch is modified.

D latch of P1.0 has value 1.4. The result is written to the external pin.

External pin (pin 1: P1.0) has value 1.

Reading the Latch


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g

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pin

P1.X

8051 IC

4. P1.X=12. CPU compute P1.X OR 1

0

0

1. Read pin=0 Read latch=1 Write to

latch=0 (Assume P1.X=0 initially)

1

TB1

TB2

3. write result to latch Read

pin=0 Read latch=0

Write to latch=1

1

0

Read-modify-write Feature


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y

Read-modify-write Instructions Table C-6

This features combines 3 actions in a single instruction

1. CPU reads the latch of the port

2. CPU perform the operation

3. Modifying the latch

4. Writing to the pin

Note that 8 pins of P1 work independently.

Port 1 as InputRead from latch


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Exclusive-or the Port 1MOV P1,#55H ;P1=01010101

AGAIN: XOR P1,#0FFH ;complement

ACALL DELAY

SJMP AGAINNote that the XOR of 55H and FFH gives AAH.

XOR of AAH and FFH gives 55H.

The instruction read the data in the latch (not from the pin).

The instruction result will put into the latch and the pin.

Read-Modify-Write Instructions


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ExampleMnemonics

SETB P1.4SETB PX.Y

CLR P1.3CLR PX.YMOV P1.2,CMOV PX.Y,C

DJNZ P1,TARGETDJNZ PX, TARGET

INC P1INC

CPL P1.2CPL

JBC P1.1, TARGETJBC PX.Y, TARGET

XRL P1,AXRL

ORL P1,AORL

ANL P1,AANL

DEC P1DEC

You are able to answer this Questions:


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You are able to answer this Questions:

How to write the data to a pin

How to read the data from the pin

Read the value present at the external pin.

Why we need to set the pin first

Read the value come from the latchnot from the external

pin.

Why the instruction is called read-modify write?

Other Pins


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P1, P2, and P3 have internal pull-up resisters. P1, P2, and P3 are not open drain.

P0 has no internal pull-up resistors and does not connects to

Vcc inside the 8051.

P0 is open drain.

Compare the figures of P1.X and P0.X.

However, for a programmer, it is the same to program P0, P1,

P2 and P3.

All the ports upon RESET are configured as output.

A Pin of Port 0


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8051 IC

D Q

Clk Q

Read latch

Read pin

Write to latch

Internal CPUbus

M1

P0.X

pinP1.X

TB1

TB2

P1.x

Port 0pins 32-39


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p

P0 is an open drain. Open drain is a term used for MOS chips in the same way

that open collector is used for TTL chips.

When P0 is used for simple data I/O we must connect it to

external pull-up resistors. Each pin of P0 must be connected externally to a 10K ohm

pull-up resistor.

With external pull-up resistors connected upon reset, port 0

is configured as an output port.

Port 0 with Pull-Up Resistors


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P0.0

P0.1P0.2P0.3P0.4P0.5P0.6

P0.7

DS50008751

8951

Vcc10 K

Port

0

Dual Role of Port 0


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When connecting an 8051/8031 to an external memory, the 8051uses ports to send addresses and read instructions.

8031 is capable of accessing 64K bytes of external memory.

16-bit addressP0 provides both address A0-A7, P2 provides

address A8-A15.

Also, P0 provides data lines D0-D7.

When P0 is used for address/data multiplexing, it is connected to the

74LS373 to latch the address.

There is no need for external pull-up resistors as shown in

Chapter 14.

74LS373


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D

74LS373ALE

P0.0

P0.7

PSEN

A0

A7

D0

D7

P2.0

P2.7

A8

A15

OE

OC

EA

G

8051 ROM

Reading ROM (1/2)


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D

74LS373ALE

P0.0

P0.7

PSEN

A0

A7

D0

D7

P2.0

P2.7

A8

A12

OE

OC

EA

G

8051 ROM

1. Send address to

ROM

2. 74373 latches the

address and send to

ROM

Address

Reading ROM (2/2)


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D

74LS373ALE

P0.0

P0.7

PSEN

A0

A7

D0

D7

P2.0

P2.7

A8

A12

OE

OC

EA

G

8051 ROM

2. 74373 latches the

address and send to

ROM

Address

3. ROM send the

instruction back

ALE Pin


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The ALE pin is used for de-multiplexing theaddress and data by connecting to the G pin of

the 74LS373 latch.

When ALE=0, P0 provides data D0-D7.When ALE=1, P0 provides address A0-A7.

The reason is to allow P0 to multiplex address and

data.

Port 2pins 21-28


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Port 2 does not need any pull-up resistors sinceit already has pull-up resistors internally.

In an 8031-based system, P2 are used to

provide address A8-A15.

Port 3pins 10-17


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Port 3 does not need any pull-up resistors since it already

has pull-up resistors internally.

Although port 3 is configured as an output port upon reset,

this is not the way it is most commonly used.

Port 3 has the additional function of providing signals. Serial communications signalRxD, TxDChapter 10

External interrupt/INT0, /INT1Chapter 11

Timer/counterT0, T1Chapter 9

External memory accesses in 8031-based system/WR,/RDChapter 14

Port 3 Alternate Functions


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17RDP3 7

16WRP3.6

15T1P3.5

14T0P3.4

13INT1P3.312INT0P3.2

11TxDP3.1

10RxDP3.0

PinFunctionP3 Bit

microcontroller 8051 instruction set

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