microarchitectural approaches to exceeding the complexity barrier © eric rotenberg 1...

Microarchitectural Approaches to Exceeding the Complexity Barrier© Eric Rotenberg

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Microarchitectural Approaches to Exceeding the Complexity Barrier

Eric Rotenberg

Center for Embedded Systems Research (CESR)

Department of Electrical & Computer Engineering

North Carolina State University

www.tinker.ncsu.edu/ericro

http://www.tinker.ncsu.edu/ericro







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Complexity Barrier(general-purpose systems)

• Deep submicron designs– Technology/circuit trends

• Billions of transistors & multi-GHz clock rates• Low voltage for power management• Risk-prone circuit techniques (e.g., dynamic logic) for

performance• Reduced design tolerances overall• Highly prone to transient faults (I.e., single-event upsets)

– Microarchitecture trends• Increasingly sophisticated techniques for exploiting instruction-

level parallelism• Functional verification becoming intractable• Highly prone to design faults (I.e., bugs)


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processor

Time Redundancy• Conventional time redundancy

– Run program twice, compare answers– Can detect transient faults– Doubles execution time


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Simultaneous Multithreading (SMT)

• Execute multiple programs on wide superscalar processor at same time– Single program does not fully utilize

parallelism of wide superscalar processor– Running two programs simultaneously takes

less time than running them consecutively


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AR-SMT[Rotenberg, FTCS-29, June 1999]

• Run two copies of program at the same time, one slightly ahead of the other– Advanced stream (A-stream) passes its

control flow and data flow outcomes to redundant stream (R-stream) for checking

SMTprocessor

A-stream

R-stream


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AR-SMT[Rotenberg99, FTCS-29]

• Higher processor utilization reduces overhead of time redundancy

• Can reduce overhead further– R-stream has oracle view of the future!– R-stream uses A-stream control flow and data flow

as 100% accurate branch/value predictions1. R-stream executes more efficiently, yielding resources back

to A-stream

2. Exploits existing prediction verification datapaths

– “Misprediction” implies transient fault occurred


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AR-SMT Performance

0

5

10

15

20

25

30

0 1 2 3 4 5 6 7 8

number of PEs used

% o

f al

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les

A-streamR-stream

1

1.1

1.2

1.3

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1)

4 PE8 PE


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DIVA[Austin99, MICRO32]

• Innovative approach for dynamically detecting and recovering from design faults

• Add simple checker processor at commit stage of complex processor– Complex core passes results to checker– Checker re-executes instructions to confirm

correctness of results before committing them– Checker is simple hence verifiable– Dynamic verification relieves burden of finding all

design bugs before shipping


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• Simple checker can keep up with complex core– Like R-stream in AR-SMT, checker not bound

by control/data dependences

DIVA[Austin99, MICRO32]

SimpleChecker

Processor

ComplexProcessor

Core

Reg. File,Memory


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Complexity Barrier(embedded systems)

• What constrains embedded system complexity– Conventional wisdom

• Power, cost, etc.• Not unique to embedded … general-purpose and embedded

systems benefit alike from technology scaling in these respects

– Real-time constraints demand analyzability• Need safe bound on worst-case execution time (WCET)• Worst-case timing analysis tools

– Scalar in-order pipeline with caches and static branch prediction is a complexity limit

• Contemporary processors excluded– Superscalar, OOO execution, dynamic branch prediction, etc.– Unsafe because can’t statically bound WCET


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VISA[Anantaraman et al. 03, ISCA-30]

• Virtual simple architecture (VISA)– VISA is timing specification of hypothetical simple

processor– WCET derived for task assuming VISA– Speculatively execute task on complex pipeline

• Divide task into multiple sub-tasks• Sub-tasks assigned soft deadlines (checkpoints) based on

latest allowable completion time on VISA• Safe progress on unsafe processor confirmed for as long as

checkpoints are met• If miss checkpoint, reconfigure complex pipeline to simple

operating mode that directly implements VISA


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Virtual Simple Architecture

Complex Processorwith Simple Mode

Worst-Case Timing Analysis

EDF scheduler,DVS scheduling, etc.

VISA[Anantaraman et al. 03, ISCA-30]

• Circumvent worst-case timing analysis of complex processors by dynamically confirming behavior bounded by WCET of simpler proxy

WCET abstraction


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Summary• Microarchitectural approaches provide

innovative alternatives for dealing with uncertainty– Theme: View any unsafe system as

speculative, provide dynamic checking and recovery from “mispredictions”

– Mispredictions• Transient faults• Design faults• WCET faults

microarchitectural approaches to exceeding the complexity barrier © eric rotenberg 1...

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