micro unit three

8/13/2019 Micro Unit Three

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COE 381 MICROPROCESSORS

UNIT 3

MICROPROCESSOR INTERFACING


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Chapter Objectives

I/OAddressing

Compromises /Extensions Types of Bus-based I/O

Microprocessor Interfacing:Interrupts Direct Memory Access

Arbitration Multilevel BusArchitecturesError Detection and

Correction


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MICROPROCESSOR INTERFACING

SECTION 1:


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Embedded System Embedded system has three functionality aspects: Processing

Transformation of data Implemented using processors

Storage Retention of data Implemented using memory

Communication Transfer of data between processors and memories Implemented using buses Called interfacing


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Embedded System

CPU MEM

I/O


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Simple Bus

Wires are conducting channels interconnectingsystem devices and components

may be uni-directional or bi-directional Bus is a set of wires with a single function e.g.

address bus, data bus Though may also be an entire collection of wires with

various functionalities Protocol is a set of rules for communication over

the wires or a bus


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Bus Structure

Processor Memory

rd'/wr

enable

addr[0-11]

data[0-7]

bus bus structure


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Ports A port is a conducting device on periphery of a

design entity e.g. a port connects a bus to processor or memory

Ports are often referred to as pins Actual pins are located on the periphery of an IC

package and plugs into a socket on a pc board. Sometimes metallic balls are used instead of pins

A pad may be a single wire or set of wires withsingle function within a chip e.g., 12-wire address port


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Ports

Processor Memory rd'/wr

enable

addr[0-11]

data[0-7]

port

bus


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Timing Diagrams Most common method for describing a communication

protocol is by the use of timing diagrams On a timing diagram, time proceeds to the right on x-axis

A control signal may be low or highat some intervals

assert is used to indicate that the signal is made active and

deassert means deactivated Asserting go means set go=0

Data signal may be valid or not

0

1

valid Invalid


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Timing Diagrams

A bus protocol may have sub-protocols

A sub-protocol is also called a bus cycle e.g., read and write

Each bus cycle may take several clock cycles


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Read Protocol

read protocol

rd'/wr

enable

addr

data

t setup t read

0


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Basic Protocol Concepts

Actor: design entity (e.g. processor ormemory) involved in the data transfer

May master, slave or peer Direction: sender, receiver Addresses: special kind of data that specifies a

location Time (division) multiplexing: Sharing a single

set of wires for multiple pieces of data save amount of wires at expense of time


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Time-Multiplexing

data serializing address/data muxing

Master Servant req

data(8)

data(15:0) data(15:0)

mux demux

Master Servant req

addr/data

req

addr/data

addr data mux demux

addr data

req

data 15:8 7:0 addr data

Time-multiplexed data transfer

Send 16 bit dataover 8 bit

databus

Send both data andaddress through a

single bus


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Control Methods

Strobe protocol

(faster if response time of servant is known)

Handshake protocol

(better if there are multiple servants with differentresponse times ack line required)

Master Servant req

ack

req

data

Master Servant

data

req

data

taccess

req

data

ack

1. Master asserts req (uest) to receive data 2. Servant puts data on bus within time t access

1

2

3

4

3. Master receives data and deassertsreq 4. Servant ready for next request

1

2

3

4

1. Master asserts req to receive data 2. Servant puts data on bus and asserts ack to indicate data isready and valid 3. Master receives data and deasserts req 4. Servant ready for next request

Master wants to receive data Master wants to receive data


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A Strobe/Handshake Compromise

Fast-response case

req

data

wait 1 3

4

1. Master asserts req to receive data 2. Servant puts data on bus within time t access

3. Master receives data and deasserts req 4. Servant ready for next request

2

Slow-response case

Master Servant req

wait

data

req

data

wait 1

3 4

1. Master asserts req to receive data 2. Servant can't put data within t access , asserts wait

3. Servant puts data on bus and deasserts wait 4. Master receives data and deasserts req

2

taccess taccess

5. Servant ready for next request

5

(wait line is unused)


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I/O Addressing

A microprocessor communicates with other devices usingsome of its pins (non-control pins) For an I/O device, communication may be port-based or bus-based

Port-based I/O (parallel I/O) the processor has one or more N-bit ports, connected to dedicated registers

e.g., P0 = 0xFF; v = P1; where P0 and P1 are 8-bit ports

For bus-based I/O the processor has address, data and controlports that form a single bus

Communication protocol is built into the processor a single instruction carries out Read (or Write) sub-protocol on the bus


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Compromises/Extensions

Parallel I/O peripheral: When processor only supports bus-

based I/O but parallel I/O needed Extended parallel I/O:

When processor supports port-basedI/O but more ports needed


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Compromises/Extensions

Processor Memory

Parallel I/O peripheral

Port A

System bus

Port C Port B

Adding parallel I/O to abus-based I/O processor

Address, system andcontrol lines

Parallel I/O peripheral

Port A Port B Port C

Port 0 Port 1 Port 2 Port 3

Extended parallel I/O

Processor


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Types of Bus-based I/O

Processor talks to both memory andperipherals using same bus in two ways

memory-mapped I/O address space is divided between memory and I/O

Standard I/O entire address space is available for memory access entire address space is available for I/O access required access memory or I/O? Need to indicate.


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Memory-Mapped I/Ovs. Standard I/O

Merits of memory-mapped I/O no requirement for special instructions for I/O access instructions involving memory also work with peripherals

Standard I/O requires special instructions to move datafrom/to peripheral registers

Merits of standard I/O no partial loss of memory address space to peripherals simpler address decoding logic in peripherals is possible


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Microprocessor Interfacing

Polling Processor polls peripherals regularly Wasteful if too frequent Ineffective if not frequent enough

Interrupt-driven Peripheral interrupts processor when servicing is

required Upon interrupt assertion

Processor suspends current task Jumps to and run the appropriate ISR in response Interrupt detection mechanism implemented in hardware

Extra pin(s) to facilitate interrupt reception


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Interrupts Fixed interrupt

An address is built into processor Either ISR starts from the address or a jump-to-ISR

instruction is stored there To service multiple peripherals several interrupt pins

needed Vectored interrupt

Peripherals provide addresses of their associated ISRs Commonly used when multiple peripherals are connected

by system bus Only one interrupt pin necessary

Compromise: interrupt address table of knownlocation, peripherals provide indices into table


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Example: Interrupt in Action

Processor running main program: currentlyexecuting instruction from location 100

Peripheral 1 (a sensor) sends an interrupt ISR reads data from sensor, then transform

and write it to Peripheral 2 (a display)


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Interrupt with Fixed ISR


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The Case of Vectored Interrupt


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Vectored Interrupt (2)

Int

P

P1 P2

System bus

Data memory

0x8000 0x8001

16: MOV R0, 0x800017: # modifies R0

18: MOV 0x8001, R0

19: RETI # ISR return

ISR

100:

101:

instruction

instruction

...

Main program ...

Program memory

PC

100

Inta

16 1

Int


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Vectored Interrupt (4) 4: P1 detects Inta and puts interrupt address vector 16 on the data bus

P

P1 P2

Data memory

0x8000 0x8001

16: MOV R0, 0x8000

17: # modifies R0

18: MOV 0x8001, R0


ISR

101:

instruction

instruction

...

Main program

...

Program memory

PC

Int

Inta

16

100

16


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Vectored Interrupt (5) 5(a): PC jumps to the address on the bus (16). The ISR there reads data from

0x8000, modifies the data, and writes the resulting data to 0x8001. 5(b): After being read, P1 deasserts Int .

P

P1 P2

System bus

Data memory

0x8000 0x8001

16: MOV R0, 0x8000

17: # modifies R0

18: MOV 0x8001, R0


ISR

100:

101:

instruction

instruction

...

Main program ...

Program memory

PC

Int

Inta

16

100

16: MOV R0, 0x8000

17: # modifies R0

18: MOV 0x8001, R0


ISR

100:

101:

instruction

instruction

...

Main program ...

P1 P2

0x8000 0x8001

System bus

0

Int


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Vectored Interrupt (6) 6: The ISR returns, thus restoring the PC to 100+1=101, where the P

resumesP

P1 P2

System bus

Data memory

0x8000 0x8001

16: MOV R0, 0x8000

17: # modifies R0

18: MOV 0x8001, R0


ISR

101:

instruction

instruction

...

Main program ...

Program memory

PC

Int

100 100 +1

16: MOV R0, 0x8000

17: # modifies R0

18: MOV 0x8001, R0


ISR

101:

instruction

instruction

...

Main program ...

100


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Interrupt Address Table

A compromise between fixed and vectoredinterrupts

A table in memory holds ISR addresses maybe 256 words

A peripheral provides just an index into the table fewer bits sent by the peripheral

ISR location can be moved without changingperipheral Only one interrupt pin required


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Maskable and Non-Maskable Interrupts

A maskable interrupt A programmer can set a bit (or bits) to cause

processor to ignore the interrupt

Important when processor is responding to criticalsituations A non-maskable interrupt

A separate interrupt pin that cannot be masked Reserved for drastic situations


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Direct Memory Access (DMA)

More efficient in buffering peripheral data inmemory

DMA controller is a single purpose processor moving data between peripherals and memory


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DMA (2) Peripheral makes a request to DMA to write data

to the memory DMA requests system bus control from the P P relinquishes control of bus to DMA controller

no jumping into an ISR with its attendant overhead Regular program need not wait

unless it requires the system bus

In the case of Harvard architecture: processor can fetch and execute instructions, but no

access to data memory


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Three main steps are involved in DMA Processor sets up DMA by supplying

1) device identity, 2) operation to perform, 3) Source ordestination memory address, and 4) number of bytes totransfer

DMA starts and DMA controller arbitrates for the bus

DMA transfer completesDMA controller interrupts CPU, and CPU checks for anypossible errors


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Overhead of DMA I/O Systems

For previous hard disk systems

assume initial setup for DMA takes 1000 clockcycles, handling interrupt at DMA completiontakes 500 cycles, and average transfer from disk is8 kB

Average fraction of CPU time consumed is 0.15%


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Intel 8237 DMA Controller

Intel 8237 D[7..0] A[19..0]

ALEMEMRMEMW

IORIOW

HLDAHRQ

REQ 0 ACK 0

REQ 1 ACK 1REQ 2

ACK 2

REQ 3 ACK 3


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Transfer Without DMA

Recall example on vectored interrupt


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Transfer With DMA1(a): P is executing its mainprogram. It has already configuredthe DMA ctrl registers.

1(b) : P1 receives inputdata in a register withaddress 0x8000.

2: P1 asserts req torequest servicing byDMA ctrl.

7(b): P1 de-asserts req .

T i m

e

3: DMA ctrl assertsDreq to requestcontrol of system bus.

4: After executing instruction 100,P sees Dreq asserted, releasesthe system bus, asserts Dack , andresumes execution. P stalls onlyif it needs the system bus tocontinue executing.

5: (a) DMA ctrl assertsack (b) reads data from0x8000 and (b) writesthat data to 0x0001.

6: . DMA de-assertsDreq and ackcompleting handshakewith P1.7(a):

P de -asserts Dack andresumes control of the bus.


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Transfer With DMAData memory P

DMA ctrl P1

System bus

0x8000 101:

instruction

instruction

... Main program

...

Program memory

PC

100

Dreq Dack

0x0000 0x0001

100:

No ISR needed!

0x0001

0x8000

ack

req


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DMA ctrl P1

System bus

0x8000 101:

instruction

instruction

... Main program

...

Program memory

PC

100

Dreq Dack

0x0000 0x0001

100:

No ISR needed!

0x0001

0x8000

ack

req req 1

P1 Dreq

1

DMA ctrl


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Transfer With DMAData memory

P

DMA ctrl P1

System bus

0x8000 101:

instruction

instruction

... Main program

...

Program memory

PC

100

Dreq Dack

0x0000 0x0001

100:

No ISR needed!

0x0001

0x8000

ack

req

Dack 1


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DMA ctrl P1

System bus

0x8000 101:

instruction

instruction

... Main program

...

Program memory

PC 100

Dreq Dack

0x0000 0x0001

100:

No ISR needed!

0x0001

0x8000

ack

req

Data memory

DMA ctrl P1

System bus

0x8000

0x0000 0x0001

0x0001

0x8000

ack

req

ack 1


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Transfer With DMA

Data memory P

DMA ctrl P1

System bus

0x8000 101:

instruction

instruction

... Main program

...

Program memory

PC 100

Dreq Dack

0x0000 0x0001

100:

No ISR needed!

0x0001

0x8000

ack

req

ack 0 Dreq

0


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Priority Arbiter

Multiple peripherals request service from singleresource (e.g., microprocessor, DMA controller)simultaneously

Which one gets serviced first? A priority arbiter provides a solution

A single-purpose processor is the arbiter makes requests to the resource on behalf of the

requesting peripheral with the highest priority The arbiter is connected to system bus for the

purpose of configuration only


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Priority Arbiter (2)

Micro-processor

Priorityarbiter

Peripheral1

System bus

Int3

5

7 Inta

Peripheral2

Ireq1

Iack2

Iack1

Ireq2

2 2

6


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Types of Priority

There are two types of priority Fixed priority

each peripheral has unique rank highest rank is chosen first in the event of

simultaneous multiple requests preferred when a clear difference in rank betweenperipherals exists

Rotating priority (or round-robin)

priority changes based on history of servicing This affords better distribution of servicing Used especially among peripherals with similar

priority demands


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Intel 8259 Programmable PriorityController

Intel 8259 D[7..0] A[0..0]

RDWRINT

INTA

CAS[2..0]

SP/EN

IR0IR1IR2IR3IR4IR5IR6IR7


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Daisy-chain Arbitration

Arbitration by peripherals themselves Arbitration functionality built into the

peripheral or provided by addedexternal logic req input and ack output on peripherals Peripherals connected together in a

daisy-chain manner


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Priority Arbiter

P System bus

Int

IntaPeripheral1

Ack_in Ack_outReq_out

Req_in

Peripheral2

Ack_in Ack_outReq_out Req_in

Daisy-chain aware peripherals

0


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Pros and Cons of Daisy-chain

Easy to add/remove peripheral - no systemredesign needed

Does not support rotating priority

One broken peripheral can cause loss ofaccess to other peripherals


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Network-oriented Arbitration

When multiple microprocessors share a bus(sometimes called a network) Arbitration typically built into bus protocol

Separate processors may try to writesimultaneously causing collisions This arbitration is typically used for connecting

multiple distant chips


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Multilevel Bus Architectures

Using one bus for all communication Requires high-speed, processor-specific bus

interface

Excess gates, power consumption, and cost System less portable Many peripherals can lead to slow-down of bus

Multilevel bus architecture When one-bus-for-all-communication is not

desirable


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Multilevel Bus Architectures (2)

Processor-local bus

Micro-processor

Cache Memorycontroller

DMAcontroller

BridgePeripheralPeripheralPeripheral

Peripheral bus


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Advanced Communication Principles

Layering breaking complexity of communication protocol

into pieces Pieces are called layers of the protocol

Easier to design and understand Lower layers provide services to higher ones Higher level might work with packets of data

Ad d C i ti P i i l


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Advanced Communication Principles(2)

Parallel communication: Physical layer capable of transporting multiple bits of

data at a time

Serial communication Physical layer transports one bit of data at a time

Wireless communication No physical connection needed for transport at

physical layer


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Parallel Communication

Multiple data, control, and possibly powerwires are involved

A word is sent one bit per wire

High data throughput

Used over short distances


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Serial Communication

Serial: bits sent in sequence one at a time

higher data throughput over long distancesdue to low average capacitance

Cheaper and less bulky


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Serial Communication (2)

more complex interfacing logic andcommunication protocol

Sender needs to decompose word into bits Receiver needs to recompose bits into word Control signals often sent on same wire as data


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Serial Communication (3)

Often more complex electrical connectionsthan just one wire

Fibre-Optic Uses light to communicate

Low Voltage Differential Signal (LVDS) Consists of two signals: one is the inversion of the other


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Wireless Communication Infrared (IR)

Electromagnetic wave just below visible light spectrum Diode emits infrared light to generate signal Infrared transistor detects signal Cheap to build Line-of-sight, limited range

Radio frequency Electromagnetic wave in radio spectrum Analog circuitry and antenna on both sides of T-mission Line of sight is not needed Range is determined by transmitter power


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Error Detection and Correction

Often part of bus protocol Error detection

ability of receiver to detect errors duringtransmission

Error correction ability of receiver and transmitter to cooperate to

correct errors Typically done by acknowledgement/retransmission

protocol


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Error Detection and Correction (2)

Bit error: single bit is inverted Burst of bit error: consecutive bits received

incorrectly Parity: extra bit sent with word used for error

detection Checksum: extra word sent with data packet

of multiple words

micro unit three

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