Michael William Hughes346 Spring Street Newport, Rhode Island Phone:(401) 662-3148 Email: mike.401.hughes@gmail.com

Summary: Hardware Design and Verification Engineer, Hardware Architect, Systems Engineer: Hardware Design and Verification Engineer: FPGA (XILINX, Altera, Actel, etc), ModelSim, HDL Designer, SystemVerilog, UVM/OVM, C/C++, Perl/Python Scripting, ASIC, PCB Design. Hardware Design Engineer with experience in Telecom Network, Enterprise, and Defense and Industrial C4ISR platforms and applications, e.g. Optical/Multi-Gb Ethernet, Digital Modems, PHY Chips, Metro Edge Telecom Optical/Ethernet Switches, Routers, Storage, Controllers, Multicore Server Processors, Hardware Emulation, Embedded Systems, Wireless, and C4ISR Displays.

Hardware Design and Verification, System, Platform, Enterprise Architect (2009-2015)Widget Verticals - Platform and System Architecture Statement of Work (SOW) and System Requirements definition for detailed technology roadmap development for advanced Widget Verticals IaaS Automated Cloud Infrastructure. Systems Architect for nanobiowave systems realtime C4ISR Realtime “Big Data” Health Signals Intelligence Enterprise Architecture and Home Health Command Center Platform Architecture. Concept and System-on-a-Chip architecture of fixed and mobile embedded system integrated circuit platform and realtime health command center design. Systems Test Plan specification for Widget Verticals command center and nanobiowave Human Waveform Systems Architecture with “big data” acquisition from carbon-nanotube and optical nanobiosensor wearable MEMS/NEMS Technology Libraries. Definition of Enterprise Architecture, Platform Architectures, Satcom, XGPON, Wireless Network Architectures, and Realtime Intelligence Algorithms for realtime wireless Health Enterprise Infrastructure Public/Private Utilities Infrastructure for Big Data FPGA/ASIC/Server Systems C4ISR communications and scalable Data Center Module Platforms utlizing UVM verification methodologies on FPGA-ASIC-based Public and Private Cloud Servers and Terabit/sec Cloud Frameworks.

FPGA Hardware Design Engineer and Hardware Verification EngineerM.I.T. LINCOLN LABORATORY (Lexington, Massachusetts) (2008)DVB-S2 Transmitter Waveform Design. FPGA SOC Design of Physical Layer Mapper, Scrambler, Framer for DVB-S2 DigitalVideo Broadcast Transmitter/Modulator for XILINX VIRTEX-5 SXT95 FPGA with QPSK/8PSK Modulation Functions. ETSIDVB-S2 Specification. Tools/Design Flow: MODELSIM RTL Simulation, SYNPLIFY PRO Logic Synthesis, XILINX VIRTEX-5SXT95 FPGA, XILINX ISE Foundation. Consultant expertise in SV/UVM IC and FPGA Design VerificationMethodologies and real-time automated verification hardware emulation platform infrastructure.

Systems Engineeer, Hardware Architect, Design, Verification, and Validation EngineerIndependent Technology Platform Innovation Studies (2002-2007).FPGA, ASIC, SoC, MultiCore IP Hardware Architecture, Design, Verification, and Silicon Validation Engineering SkillsDevelopment. FPGA, ASIC, SoC, MultiCore IP Embedded Hardware Architect, IP Functional Block Design, Integration and Test,Embedded Software Design Engineering Skills Development. Developed Technical skills in Synthesizable VERILOG/VHDL andSystemVerilog Testbench Environments, C/C++/Assembly ISR’s for Embedded High Performance Processors, SynthesizableFPGA Testbench Architectures, and Standard ASIC Chip Design Methodologies to facilitate Career Development focusing onSilicon and System Platform Architecture, Design, Verification, and Validation. Developed skills as an FPGA SoC Architect, Design, Verification, and Silicon Validation Engineer using Standard and Application-Specific Embedded Processor Cores, DSPCores, I/O Cores, Network Processor Architectures, FPGA/ASIC/SOC Synthesizable Design Verification Methodologies, CareerDevelopment Strategizing for maximum longterm ROI. Consultant expertise in Design VerificationMethodologies and real-time automated verification hardware emulation platform infrastructure.

FPGA Hardware Design EngineerSYCAMORE NETWORKS (Wallingford, CT) (1999-2001)FPGA Design Engineer, VHDL Coding, MTI Simulation, Synopsys Synthesis, and Lab Debug of Ingress and Egress Paths ofDS3 to System Interface. FPGA Design Architecture and Functionality consisted of SONET/Packet Flow Control and ExternalSRAM Lookup Table and SONET/Packet modification. Altera FPGA and Altera Quartus Tool suite. Expertise in SV/OVM/UVMIC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform

infrastructure. The Wallingford, CT based Sirrocco Systems, an Optical-Edge Switch Products Start-Up Company, was merged toform the Optical-Edge Switch Product Development Business Unit of Sycamore Networks, a Transport-to-Edge-to-Access OpticalNetworking Infrastructure Corporation (Chelmsford, MA). Successful Startup Company Buyout (Mergers and Acquisitions).

ASIC Design Verification Simulation EngineerLUCENT TECHNOLOGIES (North Andover, MA and Allentown, PA) (1999)ASIC Verification of the SuperMapper ASIC, a SONET STS-1 Mapped to T1/E1, DS2, DS3 and Multiple Standard and CustomSystem Interfaces for large scale TELCO Switching Platform Access. Tasks included developing ASIC Verification OperationsFlow for ASIC RTL Development, Test bench Driver Development in the MTI Simulation Environment, ASIC VerificationOperations Development, Test Plan Development, Verification Operations Perl Script Development, and ASIC Verification TeamDevelopment. Expertise in IC and FPGA Design Verification Methodologies and real-time automated verificationhardware emulation platform infrastructure.

Multichip FPGA Design Verification Team LeaderEMC (Hopkington, MA) Subsidiary McDATA Corporation, North Ontario, Canada (1998-1999)Team Lead for Verilog Multichip FPGA Design Verification of Fibre Channel/Switch/Protocol Controller using Verilog VCS.Team Lead for three FPGA verification engineers responsible for detailed Verification Test Plan Development, FPGA VerificationTest Bench, and Regression Test Scenario Script Development, VeriSure Code Coverage Analysis (Statement Coverage, BranchCoverage, Path Coverage, Condition Coverage), Verilog module bug diagnosis, location, and code edits with Atria Clearcaseverilog source code control. Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.

Verilog ASIC Design Verification Simulation EngineerFUJITSU Corporation, Acton, MA (1998)Verilog ASIC Design Verification of Frame Relay over DS3 ASIC Chipset with Channelized/Unchannelized T1/E1/T3E3. ASICVerification Simulations were executed on the T1/E1/T3/E3 ASIC and the Frame Memory Contoller ASIC which provisionedeight Frame Relay Service Tiers via an ATM Core Switching Hub. Developed T1/E1/T3/E3 Framer Transactor and DesignVerification Strategy/ Framework developed for Standalone ASIC-Level Testbenches, ASIC Chipset/System-Level Verification.Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification hardwareemulation platform infrastructure.

Verilog ASIC Design Verification Simulation EngineerDIGITAL EQUIPMENT CORPORATION, Maynard, MA (1997)Verilog ASIC Design Verification of DEC/Compaq’s next generation Enterprise Server Chipset. ASIC Verification Simulationswere executed on the I/O Spanner ASICs which facilitated the data exchange between the multiprocessor server chipset switchfabric and standard PCI Bus ASICs. Standalone ASIC verification and multiprocessor block (18 ASICs) verification testbeds weredeveloped using verilog VCS, verilog PLI, and Perl Scripts. The Enterprise Server Chipset I/O Spanner block contained thefollowing basic functions: Cached DMA, Cache Coherency State Machines, Multiprocessor Switch Fabric Bus CommandArbitration State Machines, PCI ASIC I/O Command FSMs, TLB Logic, System Interrupts, and I/O CSRs. Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platforminfrastructure.

Verilog ASIC and Board Hardware Design Verification Simulation EngineerCABLETRON SYSTEMS, INC., Rochester, New Hampshire (1995-1997)

Verilog ASIC/Board Hardware Design Verification of Cabletron’s ATM TELCO/Enterprise Backbone Switch Product. The 5.4GBPS ATM Switch Fabric was produced using LSI 500K and G10 Technology. ASIC and Board Level Design VerificationSimulation Environments were developed on Sparc20 Workstations using verilog modules, perl scripts, SignalScan and VirsimWaveform GUIs to verify ASIC Chipset and Board-Level Design Functionality. The PCB/System Level Verilog Netlist consists of17 ASICs from the 5-ASIC ATM Switch Fabric Chipset, their associated Sync RAM and Async RAM Memory Subsystems, anATM SAR Chip and Intel I960 Processor, 155 MBPS and 622 MBPS NIC PHY Layer Chips, XILINX FPGA, and Lattice CPLDverilog models. I developed the design verification environment and performed chipset-level system simulations. Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulationplatform infrastructure.

Hardware Design Verification and Board Power-Up and Debug EngineerASEA BROWN BOVERI (ABB) POWER TRANSMISSION & DISTRIBUTION, Coral Springs, FL (1994)Hardware Design Verification, Power-Up and Debug for MC68360 and MC68332 based PCB design which utilized PowerSubstation Three Phase Voltage and Current Fault Signature Detection to localize Power Transmission and Distribution NetworkPower Outages/Brown-Outs. On this embedded systems development project, many tasks were performed using MotorolaBackground Debug Mode with various 68360 Emulators to download SIM register settings and verify/exercise all boardfunctions.

Hardware Design and Verification EngineerIndependent ASIC Design & Product-Level Hardware Design Cycle Tools, Methodology, Process Study (1993)Independent study to develop detailed knowledge of tools, methodologies, high-level design flow, and hardware verificationframeworks for reducing time-to-market, NRE costs, and tool capital requirements. Design process included ASIC, ASIC Chipset,Off-the-Shelf Chips and optimizing design flow to deliver high end products to Telecommunications and Corporate EnterpriseMarket Customers. Expertise in IC and FPGA Design Verification Methodologies and real-time automatedverification hardware emulation platform infrastructure.

Hardware/Software Test Development EngineerAquidneck Management Associates, Ltd., Middletown, RI (1991-1992)Developed software test plans and test scenarios for guidance and control system software modules and PM/FL softwarealgorithms. Expertise developed on system design bug or hazard analysis methodology.

Hardware Design Verification Simulation Engineer / Test EngineerRaytheon Submarine Signal Division, Portsmouth, RI (1986-1991)Hardware Design Verification Simulations were executed for 27 PCB/SMT Board Designs in Hardware Design Engineering.Developed verilog models for board level design netlist components. Developed board level design verification tests. Leadershipin organizing and documenting methodology for test development team. Functional and Parametric Tests were developed toexercise all module functions and performance requirements. Fault localization test patterns were developed to optimizediagnostic test fault coverage. Fault injection signatures were captured during simulation for stuck-at-one/stuck-at-zero deviceand I/O faults to speed board fault localization. Device I/O and Netlist I/O states were captured for each clock to automate faultlocalization when the board simulations were postprocessed to Teradyne, GenRad, LTX, and PC based Test Stations utilizing

object-oriented data structures implementing fault-localization and fault signature methods for electronic systems validation and manufacturing test operations. Designs Validated include communications waveform synthesis, modulation, and demodulation.Expertise in IC and FPGA Design Verification Methodologies and real-time automated verificationhardware emulation platform infrastructure.

Systems Design, Test, and Integration Engineer for United States Air Force Programs.MITRE C3I Division, Bedford, MA (1984-1986)Performed Hardware, Software and System Test and Integration for advanced prototype WAN/LAN Information Systems.Complex system test scenarios and automated test suites were developed to exercise WAN/LANs and Database System Hardware, Software and GUIs. Lab Debug, IT Systems Integration and Test Engineer. Enterprise and Platform Hardware Validation of acomprehensive Waveform System Architecture and associated electronic systems implementation. Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platforminfrastructure.

Systems Engineer (Northeastern University Co-op) for United States Navy Submarine Systems.Raytheon Integrated Defense Systems (Submarine Systems Division) Portsmouth, RI. (1982-1983)Performed Submarine Systems Hardware and Software Analysis for Military Platform Software Development.EDUCATION: NORTHEASTERN UNIVERSITY, BOSTON, MA, B.S.E.E. 1984.