methodologies to study the scalability and reliability ......stanford university 11.12.2013...

Stanford University

11.12.2013

Methodologies to Study the Scalability and Reliability Physics of Phase-Change Memory Rakesh Jeyasingh1, Scott Fong1, Chiyui Ahn1, SangBum Kim1, Jiale Liang1, Marissa Caldwell1 Zijian Li2, Jaeho Lee2, Elah Bozorg-Grayeli2, Mehdi Asheghi2, Kenneth E. Goodson2, Delia Milliron3 and H. –S. Philip Wong1 1Department of Electrical Engineering and 2Department of Mechanical Engineering, Stanford University, Stanford, CA 94305 3Molecular Foundry, Lawrence Berkeley National Labs

Stanford University

Department of Electrical Engineering Rakesh Jeyasingh 2

Outline

§ Phase Change Memory (PCM) Basics

§ Phase Change Material Scaling using GeTe Nanoparticles

§ 1D Thickness Scaling Studies using Additional Top Electrode (ATE) Devices

§ Programming Current (Electrode) Scaling using CNTs

§ Micro Thermal Stage (MTS) - An On-Chip Heater and Thermometer to Study PCM Reliability Physics

§ Conclusion

Stanford University


Outline





§ Micro Thermal Stage (MTS) - An On-Chip Heater and Thermometer to Study PCM Physics

§ Conclusion

Stanford University


Phase Change Materials

Crystalline Amorphous High

Resistance Low

Resistance

Annealing

Melt-quenched

Phase-change materials:

§ Ge2Sb2Te5 (GST)

§ AIST (AgInSbTe)

§ GeSb, Sb2Te, GeTe…

Stanford University


Phase Change Materials §  Sulphur (S), Selenium (Se) and Tellurium (Te) - group 16 (VIA),

are called chalcogens §  Chalcogenides - group 16 + group 13-15 namely Arsenic (As),

Germanium (Ge), Antimony (Sb), Phosphorus (P) etc.

Most reports in the literature uses the Ge2Sb2Te5 alloy (GST)

Stanford University


Phase Change Memory

§ Amorphization (RESET): Melt and quench (T>TMelt)

§ Crystallization (SET): Anneal (T>Tcrys)

Bottom Electrode

Top Electrode

Programming regionPhase changing material

HeaterInsulator Te

mpe

ratu

re

Time

Tmelt

TcrysRead

SET pulse

RESET pulse

Troom

Stanford University


PCM Current-Voltage Characteristics

A. Pirovano et al., IEEE Trans. Electron Devices, vol. 51, no. 5, pp. 714–719, May 2004.

Stanford University


Phase Change Memory

poly c-GST poly c-GSTpoly c-GST

amorphousamorphous

SiO2 SiO2 SiO2TiN TiN TiN

TiNTiNTiNfully set state partially reset state fully reset state

§ Resistance change achieved by controlling the size of the amorphous region

§ Amorphous volume ∝ Programming power

Stanford University


History of Phase Change Memory

N. Carlisle, “The Ovshinsky invention,” Science & Mechanics,

Feb. 1970

R. G. Neale, D. L. Nelson and G. E. Moore,

“Nonvolatile and Reprogrammable, the Read Mostly Memory is Here,”

Electronics, Sep. 1970

M. Kanga et al., IEDM 2011

F ≈ 2mm 1 bit

F ≈ 350μm 256 bit

F ≈ 20nm 8 Gbit

Stanford University


PCM Status §  90 nm, 128Mb NOR replacement on market §  45 nm, 1Gb (IEDM 09, ISSCC 10), 58 nm 1Gb (ISSCC 11) §  20 nm cell (IEDM 11), 42 nm half pitch 1Gb chip (IEDM

11), 20 nm 8Gb chip (ISSCC 12) § Will keep researchers busy for a long time

– Physics of threshold switching –  Threshold switching voltage and resistance drift – Device size scaling – Partial set and reset (multi-bit operation) –  Thermal engineering (programming energy reduction) – Materials engineering for target applications (speed,

temperature, reliability) – Reliability (thermal expansion, alloy composition) – …

Stanford University


Outline






§ Conclusion

Stanford University


Synthesis of Amorphous GeTe Nanoparticles

Te precursor

Ge precursor Ligand Solvent

Caldwell, M. et al. J. Mater. Chem. 20. (2010) 1285.

2.6 ± 0.39nm 1.8 ± 0.44nm

1 10 1000

5

10

15

20

25

30

35

40

Number

S iz e (nm)

B ig B ig /Med Med/S ma ll S ma ll

20 nm 10 nm

3.4 ± 0.74nm

10nm

15 20 25 30 35 40 45 50 55

*

(042

)

(021

)(0

03)

(220

)(0

24)

Inte

nsity

(AU

)

2 Theta (°)

Amorphous as synthesized Crystallized

(202

)

*

Work completed with Delia Milliron at the Molecular Foundry.

Stanford University


Size Dependence of Crystallization Temperature

Bulk Tcryst

Collected at Brookhaven National Laboratory by Simone Raoux (IBM) and completed with Delia Milliron at the Molecular Foundry.

3.4nm

2.6nm

1.8nm

bulk Tcryst

§ Higher crystallization temperature ↔ Greater amorphous phase stability ↔ Data Retention

Stanford University


Outline






§ Conclusion

Stanford University


Additional Top Electrode (ATE) Structure

§ ATE layer acts as an electrical conductor – Confines probed amorphous

region to a known thickness

0.5 0.55 0.6 0.65 0.70

500

1000

1500

2000

2500

Distance (µm)

Tem

pera

ture

(K)

Tmelt40 nm

Stanford University

Department of Electrical Engineering Rakesh Jeyasingh 17 4.27.11

Thickness Dependence of Vth

§  Vth scales linearly with GST1 thickness –  Both Eth (41mV/nm) and Vth0 match well with previously reported values

S.Kim et al., IEEE Trans. Elec. Dev., vol.58, no.5, 2011

Stanford University


Direct Measurement of Trap Spacing using ATE Devices

Trap spacing changes with thickness and reset voltage

Average number of hoppings

STS =

€

∂ log I∂VA

=

€

q2kT

Δzua

R. Jeyasingh et al., IEEE Trans. Elec. Dev., vol. 58, no. 12, 2011

Thickness (nm)

Average Trap Spacing (nm)

Average Number of Hoppings

Trap Density (cm-3)

8 5.3 1.5 6.7 x 1018

20 6 3.3 4.6 x 1018

30 6.8 4.4 3.2 x 1018

40 7.6 5.3 2.3 x 1018

Stanford University


Outline






§ Conclusion

Stanford University


Phase Change Memory Scaling to ~1µA Prog. Current Reset current: 1.4 µA,

energy: 210 fJ/bit

J. Liang et al., Symp. VLSI Tech., paper 5B-4, 2011 (best paper award); T-ED p. 1155 (2012)

1 10 100100

101

102

103

785478.5

Res

et C

urren

t (µA)

R ed: ITR SB lac k : L iterature

E quivalent C ontac t D iameter (nm)

0.79C ontac t Area (nm2)

Stanford University


Phase Change Memory w/ Carbon Nanotube Electrode

CNT Growth and transfer on SiO2/Si substrate

Pd metal pad evaporation and O2 plasma etch to remove unwanted CNTs

Pt/Ti metal pad evaporation and Al2O3 passivation10nm GST deposition

CNTCNT

Stanford University


PCM with CNT Electrode

0.1 1 10 1000

20

40

60

80

100

res et s tate

Cumula. P

erce

nt. (%)

R es is tanc e (ΜΩ )

s et s tate

50 ns reset pulse

set reset

0.0 0.4 0.8 1.2 1.6 2.00

4

8

12

16

20

Res

istance

(MΩ

)R es et C urrent (µA )

Ires et

Reset current = 1.4 µA 100X lower than state-of-the-art

J. Liang et al., Symp. VLSI Tech. 2011

Stanford University


Phase Change Memory Scaling to 1.8 nm Node Reset current: 1.4 µA,

energy: 210 fJ/bit

200 300 400 500 6000

1

2

3

4

5

6

Counts

R es is t. (KΩ )

CNT

1µm

CNTs

TE

1 10 100100

101

102

103

1.4Work

785478.5

Res

et C

urren

t (µA)

R ed: ITR SB lac k : L iterature

E quivalent C ontac t D iameter (nm)

This

0.79

Effec

tive

Contact A

rea

2.54C ontac t Area (nm2)

J. Liang et al., Symp. VLSI Tech., paper 5B-4, 2011 (best paper award); T-ED p. 1155 (2012)

Reset current: 1.4 µA, Energy: 210 fJ/bit →100X lower than state-of-the-art

Stanford University


Scaling Studies - Summary

§  Scaling is a complex question

§  GeTe Nanoparticles offer a route to investigate size dependent properties –  Ability to solution process PCM opens options for device geometries

§  ATE devices allow scaling studies in a more practical device design –  Study threshold voltage scaling

–  Trap spacings can be directly measured

–  Aids in developing accurate models for sub-threshold conduction

§  CNTs have been shown to be an effective way to probe electrode scaling –  Extremely low RESET current and programming energy

Scaling of Phase Change Memory – Strong prospects of scaling down to few nm both at the materials and the device level

Stanford University


Outline






§ Conclusion

Stanford University


§  Crystalline phase is more stable.

Energy EA

Memory Loss Mechanism in PCM

1. Spontaneous crystallization 2. Multi-bit cell & drift §  Resistance drift

à Smaller margin

D.-H. Kang et al., Symp. VLSI. Tech., 2008.

Spontaneous crystallization

Stanford University


Temperature Dependence of Reliability Issues

Spontaneous crystallization §  Higher temperature

à Faster crystallization.

Drift (RRESET + Vth) §  Higher temperature

à Faster drift

A. Pirovano et al., IEDM, 2003. D. Ielmini et al., Microelectronic Engineering, v.86, p.1942, 2009.

Stanford University


Thermal (program) Disturbance in PCM

§ PCM uses heat for programming.

à Thermal disturbance in PCM.

§ Thermal disturbance makes reliability issues worse – especially for scaled devices

Thermal Disturbance

A.Pirovano et al., IEDM, 2003.

Selected cell

Unselected cell

Stanford University


Micro-thermal stage (MTS)

An external heater integrated with the PCM cell

§  Lateral PCM cell + Pt heater on top

§  Thermal time constant: ~1.5 µs

Temperature calibration on the external heater

PowerTTTRR

heater

heater

∝Δ

Δ+= β)( 0

0.0 5.0m 10.0m 15.0m165

170

175

180

185

Linear fit 40 °C 35 °C

30 °C 25 °C 20 °C

Rhe

ater (Ω

)Power (W)

§  Pt bridge: Heater + thermometer S. Kim et al., IEEE Tran. Elec. Dev. Vol. 58, pp. 584, 2011

Stanford University


Need for a Micro – Thermal Stage (MTS)

§  Enables temperature measurements closer to real device operating conditions § MTS – allows fast measurements of drift and crystallization on real PCM devices § Measurements on technologically relevant melt-quenched amorphous phase § Study the effect of electronic and thermal effects in isolation

T0

Tcrys

TmeltPCM

(+heater) self-

heating

Mirco-thermal stage

Thermal stage

1n 1µ 1m 1 1k

Tem

pera

ture

Termal time constant (s)Thermal )me constant (s)

Stanford University


100µ 1m 10m 100m 1 10

0.05

0.10

0.15

0.20

Drif

t coe

ffici

ent

Time after reset (s)

25oC 35oC 45oC 55oC 65oC

TA:

RRESET Drift Measurement

§  Faster drift at higher TA.

§  3 times larger drift coefficient between 100 µs and 1 ms at 65 °C

VoltageTemperature

ProgrammingRead

t0 t1 t2 tn

Time

From [5]

10µ 1m 100m 10 1k 100k

1M

2M

3M

4M

Res

ista

nce

(Ω)

Time after reset (s)

25oC 35oC 45oC 55oC 65oC

1M

10M

100M

50oC

Resistance (Ω

)

100oC

t0 t1 t2 t3 t4 t5

S. Kim et al., IEEE Tran. Elec. Dev. Vol. 58, pp. 584, 2011

Stanford University


RRESET Drift Impacted by Thermal Disturbances

§ Important features – A: ~25% variation on resistance. – B: Drift is faster – C: Drift is slower – D: No change (>100ms)

10µ 100µ 1m 10m100m 1 10 100

1M

1.5M

2M

2.5M

RR

ES

ET (Ω

)

Delay for read (s)

Delay for annealing 300µs 1.2ms 11ms 110ms

A

)/log()/log(

12

12

ttRR

=γ

100µ 1m 10m 100m 1 100.00

0.05

0.10

0.15

0.20

Drif

t coe

ffici

ent

Delay for read (s)

Delay for annealing 300µs 1.2ms 11ms 110ms no annealing

B

B

CCHeat pulse :

60 °C for 600 µs

D

Voltage

Temperature

Programming Delayed read

TimedA

dA: Delay for annealing (TD)

Stanford University


Crystallization Time (tcrys) Vs Temperature (T)

§  Current MTS enables tcrys measurement down to ~100µs.

§  Arrhenius behavior with constant activation energy (EA)

RESET

PCM

MTSheater

AB

A : Delay for readB : Delay for annealing

read

IPCMτthermal

tcrys

6 orders in time

Stanford University


Crystallization Time (tcrys) with Thermal Disturbance

§  Constant shift in log(tcrys) à The tcrys ratio is constant.

10µ

100µ

1m

10m

100m

1

10

100250 200 150

crys

talli

zatio

n tim

e (s

) With thermal disturbance (TD) Without TD

(°C)

22 24 26 281/kBT (eV-1)

∫=

=

dttTvr

TtTv

cryscrys

cryscrys

))((

)(1)(

crys

TD : 243 °C for 75 µs

vcrys: Crystallization speed rcrys: degree of crystallization

S. Kim et al., IRPS 2010

Stanford University


Effects of Temperature on PCM Reliability - Summary

§ Spontaneous crystallization and Resistance drift – major reliability issues of PCM

§ Significantly impacted by short thermal disturbances – variability in the retention and drift behavior

§ Use of Micro Thermal Stage – fast heater and thermometer to study the reliability physics in short time scales

Stanford University


Non-Volatile Memory Technology Research Initiative (NMTRI) at Stanford University

Stanford University


Technical Collaborators on Memory

Stanford University


Bottom Electrode

HT Oxide

GST

Top Electrode

Understanding Physics & Reliability

Material Scaling

Device Scaling

Methodologies to Study Scalability and Physics of PCM

1.8 ± 0.4nm

10nm

methodologies to study the scalability and reliability ......stanford university 11.12.2013...

Documents