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8/11/2019 Met All Ization

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SEMICONDUCTOR:Metallization


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ObjectivesAfter studying the material in this chapter, you will be

able to:

1. Explain the terminology for metallization.

2. List and describe the six categories of metals

used in wafer fabrication. Discuss the performancerequirements and give applications for each metalcategory.

3. Explain the benefits for using copper

metallization in wafer fabrication. Describe thechallenges for implementing copper.


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Overview of Multilevel Metallization

Interlayer Dielectric

Metal interconnect structure

Diffused active

region in siliconsubstrate

Sub quarter micron CMOS cross section

Via interconnect structure

with tungsten plug

Metal stack interconnect

Local interconnect (tungsten)

Initial metal contact

Figure 12.1


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Traditional vs. Damascene Metallization

Traditional Interconnect Flow

Oxide Via-2 etch

Tungsten deposition + CMP

Metal-2 deposition + etch

Cap ILD layer and CMP

Dual Damascene Flow

Cap ILD layer and CMP

Nitride etch-stop layer(patterned and etched)

Second ILD layer deposition andetch through two oxide layers

Copper fill

Copper CMP

Figure 12.2


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Copper Metallization

Photograph courtesy of Integrated Circuit Engineering

Photo 12.1


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Requirements for Successful Metal

Material

1. Conductivity

2. Adhesion

3. Deposition

4. Patterning/Planarization

5. Reliability

6. Corrosion

7. Stress


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Silicon and Select Wafer Fab Metals

(at 20C)

Material Melting

Temperature (C)

Resistivity

( -cm)

Silicon (Si) 1412 109

Doped Polysilicon (Doped Poly) 1412 500 525

Aluminum (Al) 660 2.65Copper (Cu) 1083 1.678

Tungsten (W) 3417 8

Titanium (Ti) 1670 60

Tantalum (Ta) 2996 13 16

Molybdenum (Mo) 2620 5

Platinum (Pt) 1772 10

Table 12.1


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Metals and Metal Alloys used in

Wafer Fab Aluminum

Aluminum-copper alloys

Copper

Barrier metals

Silicides

Metal plugs


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Aluminum Interconnect

ILD-4

ILD-5

ILD-6

Top NitrideBonding pad Metal-5 (Aluminum)

Metal-4

Via-4

Metal-4 is preceded by other vias, interlayer dielectric, and metal layers.

Metal-3

Figure 12.3


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Ohmic Contact Structure

Gate

Barrier metal

Ohmic contact

Aluminum, tungsten,copper, and so on

Source Drain

Oxide

Figure 12.4


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Junction Spiking

Junction short

Shallowjunction

Figure 12.5


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Hillock on a Metal Line due to

Electromigration

Hillocks short-circuit two metal lines

Void in metal line

Figure 12.6


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The Benefits of Copper

Interconnect1. Reduction in resistivity

1.678 -cm vs. 2.65 -cm for Aluminum

2. Reduction in power consumption

3. Tighter packing density

4. Superior resistance to electromigration

5. Fewer process steps 20 to 30 % fewer steps with damascene

technique


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Change in Interconnect Delay Compared to0.25-m Device Generation

Technology 0.25 m 0.18 m 0.13 m

Conventional Interconnect Technology:

Al/Cu Interconnect Alloy and TiN Barrier Metal

0 +21% +93%

New Technology Introduced by Generation:

Reduced Barrier Thickness

Low-k(3.0) dielectric

Dual Damascene Cu Interconnect and plugs

-10%

-27%

-16%

Table

12.2


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Comparison of Properties/Processes BetweenAl and Cu

Property/Process Al Cu

Resistivity (-cm)2.65

(3.2 for Al-0.5%Cu)1.678

Electromigration resistance Low High

Corrosion resistance (in air) High Low

CVD processing Yes No

CMP (chemical mechanical planarization)

processingYes Yes

Table 12.3


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Three Major Challenges to Using CopperInterconnects in Semiconductor Products

1. Copper diffuses quickly into oxides and silicon.

2. Copper cannot be easily patterned using regular

plasma etching techniques.

3. Copper oxidizes quickly in air at low

temperatures (


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Barrier Layer for Copper Interconnect Structure

Barrier metal

Copper

Figure 12.7


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The Essential Properties of

Barrier Metal1. Good diffusion barrier properties so that the diffusivity of

the two interface materials (e.g., tungsten and silicon) is

low at the sintering temperature (sintering refers to

joining of the materials by thermal means).

2. High electrical conductivity with low ohmic contact

resistance.

3. Good adhesion between the semiconductor and metal.

4. Resistance to electromigration.

5. Stability when thin and at high temperature.

6. Resistance to corrosion and oxidation.


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Requirements for Copper

Barrier Metal1. Prevent copper diffusion.

2. Low film resistivity.

3. Good adhesion to both dielectric material and copper.

4. Compatible with chemical-mechanical polish (CMP).

5. Metal layer is continuous and conformal with good step

coverage and deposition in high aspect ratio gaps.

6. Minimal thickness to allow the copper to occupy themaximum cross-sectional area.


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Ta for Copper Barrier Metal

Copper

Tantalum

Figure 12.8

R f M l Sili id Sili


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Refractory Metal Silicide at a Silicon

Contact

Titanium/titanium-nitride barrier metal

Tungsten metal

Titanium silicide contact

Silicon substrate

Polysilicon gate

Titanium silicide contact

Oxide OxideSource Drain

Figure 12.9


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Some Properties of Select

Silicides

Silicide

Lowest Eutectic

Temperature

(C)

Typical Forming

Temperature1

(C)

Resistivity

( -cm)

Cobalt/silicon (CoSi2) 900 550 700 10 18

Molybdenum/silicon (MoSi2) 1410 900 1100 100

Platinum/silicon (PtSi) 830 700 800 28 35

Tantalum/silicon (TaSi2) 1385 900 1100 35 45

Titanium/silicon (TiSi2) 1330 600 800 13 25

Tungsten/silicon (WSi2) 1440 900 1100 70

1 B. El-Kareh,Fundamentals of Semiconductor Processing Technologies, Kluwercademic Publishing, Boston, MA, 1995, p. 537.

Table 12.4


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Polycide on Polysilicon

Titanium polycide

Titanium silicidePolysilicon gate

Doped silicon

Figure 12.10


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Anneal Phases of TiSi2

Sintering

Temperature

Resistivity

TiSi2 C49

625 675C 60 65 -cm

TiSi2 C54

800C 10 15 -cm

Figure 12.11


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Chip Performance Issues

Related to a Salicide Structure

STI

TiSi2

STI S

G

D

TiSi2 TiSi2

TiSi2

Reduced sheet resistanceReduced gate toS/D resistance

Reduced contactresistance

Reduced diodeleakage

Figure 12.12


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Formation of Self-Aligned Metal Silicide

(Salicide)

2. Titanium deposition

Silicon substrate

1. Active silicon regions

Field oxide

Spacer oxide

Polysilicon

Active siliconregion

3. Rapid thermal anneal treatment

Titanium-siliconreaction regions

4. Titanium strip

TiSi2formation

Figure 12.13


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Tungsten Plug for Multilevel Metal Layers

Early metallization technique

1. Thick oxide deposition2. Oxide planarization

3. Contact etch through oxide

4. Barrier metal deposition

5. Tungsten deposition

6. Tungsten planarization

1. Contact etch through oxide2. Aluminum deposition

3. Aluminum etch

Tungsten plugs

inside contact holes(vias)

Oxide

(dielectric)

Aluminum contacts

Oxide(dielectric)

Current metallization technique

Figure 12.14


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Metal Plugs in IC

SiO2


Photo 12.2


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PVD Cluster Tool

Photo 12.3

Photo Courtesy of Applied Materials, Inc.


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Copper Electroplating

-Cathode

+Copper anode

Substrate

Plating solution

Inlet

OutletOutlet

Copperion

Copper atomattached to wafer

+

+

Figure 12.24


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Electroplating Tool

Used with permission from Novellus Systems, Inc.

Photo 12.4


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Traditional Aluminum

Structure

SiO2


Photo 12 4

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