Memory System Characterization of

Commercial Workloads

Luiz Andre Barroso, Kourosh Gharachorloo, and Edouard Bugnion

Presented by Jerry Wu

Introduction

Motivation Commercial workloads has become the largest market

segment for multiprocessor servers Design of these systems has yet to keep up with the pace

of changes in the market Lack of commercial workload performance requirements

This paper presents performance studies of three classes of commercial workloads

Complications

Lack of availability and restrictions Lack of easy access to commercial database engines

Large scale Large hardware cost

Complexity Non-trivial OS-I/O interactions, lack of source code

Moving target Commercial database engines improve at a very fast pace

Commercial Workloads

OLTP Workload Modeled after the TPC-B benchmark Models a banking system

DSS Workload Modeled after the TPC-D benchmark Simulates the decision support system for a supplier OLTP and DSS workloads run on Oracle Database Engine

Web Index Search Workload State-of-the-art search engine AltaVista (No Google yet)

Methodology

Monitoring OLTP and DSS benchmarks were run on Alpha 21164

using Oracle Utilized IPROBE monitoring tool to access event counters

Simulation Used an Alpha port of SimOS

Key issues Amount of physical memory required Bandwidth requirement for the I/O Total runtime

Monitoring Results

OLTP Importance of hits and misses to secondary caches and latency of dirty

misses

DSS and AltaVista Hits in secondary on-chip cache is the only significant memory

component

Simulation Results Uses an Alpha port of SimOS Observations on OLTP

Small kernel component Benefit from larger cache and

higher associativity Cache and memory system

stalls have large effects Idle time increases with bigger

caches Higher processing rates results

in less demand on I/O Small fraction of

communication in Oracle due to false sharing

Cache Hierarchy Performance Primary cache miss important

for OLTP, but more so for DSS OLTP and DSS have very

different cache performance Large on-chip cache captures

most of the misses in DSS, but not in OLTP

False sharing increases for increasing cache line size

Replacement and instruction miss rate not visibly effected

Questions