memory space of a typical system

Hardware Computer Organization for the Software ProfessionalArnold S. Berger 1

Memory space of a typical system

• Example: Assume a 24-bit addressing range, 16-bit wide data bus- 24-bit addressing >> 16 Mbyte

• Assume 1 Mbyte of RAM memory, 128KByte of ROM

ROM64K x 16

0x

00

00

00

0x

01

FF

FE

IO D

ev

ice

s

IO D

ev

ice

s

0x

FF

FF

FE

0x

F0

00

00

RAM512K x 16

EmptySpace

EmptySpace

EmptySpace

Program code and initialization vectorsProgram code and initialization vectors

Stack and heap, variable storageStack and heap, variable storage


Byte Packing

Word Address

Byte 1 – Address 000001Byte 0 – Address 000000 Byte 3 – Address 000003Byte 2 – Address 000002000000


Byte 1 – Address 000009Byte 0 – Address 000008 Byte 3 – Address 00000BByte 2 – Address 00000A000008

Byte 1 – Address 00000DByte 0 – Address 00000C Byte 3 – Address 00000FByte 2 – Address 00000E00000C


Byte 1 – Address FFFFF1Byte 0 – Address FFFFF0 Byte 3 – Address FFFFF3Byte 2 – Address FFFFF2FFFFF0

Byte 1 – Address FFFFF5Byte 0 – Address FFFFF4 Byte 3 – Address FFFFF7Byte 2 – Address FFFFF6FFFFF4

Byte 1 – Address FFFFF9Byte 0 – Address FFFFF8 Byte 3 – Address FFFFFBByte 2 – Address FFFFFAFFFFF8

Byte 1 – Address FFFFFDByte 0 – Address FFFFFC Byte 3 – Address FFFFFFByte 2 – Address FFFFFEFFFFFC


Memory organization (2)

• Memory organization usually depends upon the width of the processor data bus- The 68000 is a 32-bit processor internally, but interfaces to a 16-bit data

bus- All addresses are 32-bits internally, with 24-bits external (16M)

Bit7 0

0x0000

0xFFFF

0xFFFE

STRING

Byte Addressable memory for an 8-bit processorwith a 16-bit addressing range

7 0

STRING

15 8

Bit

0x000000x00001

0xFFFFE0xFFFFF

Byte Addressable memory for a

16-bit processorwith a 20-bit

addressing rangeIntel 80186

Little Endian

7 0

S TR IN G

15 8

Bit

0x0000010x000000

0xFFFFFF0xFFFFFE

Byte Addressable memory for a

16-bit processorwith a 24-bit

addressing rangeMC68000

Big Endian


Memory organization

• In byte-addressable systems, low-order address bits do the byte addressing- Example: The 68000 has 23 external address lines and can

address 224 bytes ( 0..16,777,215 ) or 223 words ( 0..8,388,607 )- Address bit A0 is implied by two other signals, UDS and LDS

- Can be considered to be the byte selector bits for a word addressing system, A1..A23

- For a 32-bit addressing system and a 32-bit data path ( long word ) address bits A2..A31 ( 0..1,073,741,823 ) address the word and address bits A0,A1 address the byte of the word

7 015 823 1631 24

A0 1 0 1 0A1 1 1 0 0

Little Endian

7 015 823 1631 24

A0 0 1 0 1A1 0 0 1 1

Big Endian


68000 Memory Access

0x0000010x000000

D15

D8D7

D0

0x0000020x000003

0xFF

FF

FD

0xFF

FF

FF

0xFF

FF

FC

0xFF

FF

FE

A1..A23Lower Data Strobe (LDS)

Upper Data Strobe (UDS)

Byte Access

A0=0: LDS=1, UDS=0

A0=1: UDS=1, LDS=0

Word Access

A0=0: LDS=0, UDS=0

A0=1: LDS=1, UDS=1

68000Processor

Note: A word access on a byte boundary wouldrequire two memory operations to complete andis not allowed in the 68000 processor.

Note: A word access on a byte boundary wouldrequire two memory operations to complete andis not allowed in the 68000 processor.


Memory organization (4)

• Storing 32-bit values in a 16-bit external memory

EVEN BYTE ODD BYTE

7 6 5 4 2 1 0 7 6 5 4 3 2 1 0

1 LONG WORD = 32 BITS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LONG WORD 0

MSB

LSB

HIGH ORDER WORD

LOW ORDER WORD

LONG WORD 1

MSB

LSB

LONG WORD 2

MSB

LSB


Introduction to Assembly Language• Every computer system has a fundamental set of operations that it

can perform• These operations are defined by the instruction set of the

processor- The instruction set is the atomic element of the processor- All the complex operations are achieved by building sequences

of these fundamental operations• Assembly language is the human readable form of these

instructions, called machine languageInstead of writing a program in machine language as:

00000412 307B7048 00000416 327B704A 0000041A 1080 0000041C B010 000041E 67000008 00000422 1600 00000424 61000066 00000428 5248 0000042A B0C9

Instead of writing a program in machine language as:

00000412 307B7048 00000416 327B704A 0000041A 1080 0000041C B010 000041E 67000008 00000422 1600 00000424 61000066 00000428 5248 0000042A B0C9

We write the program in assembly language as:

MOVEA.W (TEST_S,PC,D7),A0 *We'll use address indirectMOVEA.W (TEST_E,PC,D7),A1 *Get the end addressMOVE.B D0,(A0) *Write the byteCMP.B (A0),D0 *Test itBEQ NEXT_LOCATION *OK, keep goingMOVE.B D0,D3 *copy bad data BSR ERROR *Bad byteADDQ.W #01,A0 *increment the addressCMPA.W A1,A0 *are we done?

We write the program in assembly language as:

MOVEA.W (TEST_S,PC,D7),A0 *We'll use address indirectMOVEA.W (TEST_E,PC,D7),A1 *Get the end addressMOVE.B D0,(A0) *Write the byteCMP.B (A0),D0 *Test itBEQ NEXT_LOCATION *OK, keep goingMOVE.B D0,D3 *copy bad data BSR ERROR *Bad byteADDQ.W #01,A0 *increment the addressCMPA.W A1,A0 *are we done?


Using labels• Label, a symbolic name given to a variable or a constant

- Usually refers to a memory address- Must be defined in column 1

• Labels make the program readable- A program may be written without labels, but almost no one ever does it- Labels allow the assembler program to automatically calculate addresses

- Avoids errors in addressing• Example, consider the following snippet of code:

• Question: What does this instruction do? foo BRA foo *Huh?

TEST_LOOP MOVE.B (A2),D6 *Let D6 test the patterns for doneCMPI.B #END_TEST,D6 *Are we done?BEQ DONE *We've done the 4 patternsLEA ST_ADDR,A0 *Set up the starting address in A0LEA END_ADDR,A1 *Set up the ending address in A1JSR DO_TEST *Go to the testADDA.W #01,A2 *Point to the next test pattern BRA TEST_LOOP *Go back to the next location

DONE STOP #EXIT *Test is over, stop


Hardware Organization of the MC68000

Program Counter (PC) 32 Effective Address Register (EAR) 32

Memory and I/O

InterfaceControlPipeline

General RegistersD0..D7A0..A6

A7= User Stack pointer (USP)A7’=Supervisor Stack Pointer(SSP)

Temporary Register 3232

InstructionRegister(IR)

16

InstructionDecode

and Control

Arithmetic and Logic Unit(ALU)

32

CCR SR

8

ExternalBus

Internal Bus

Holds addressof the next instruction

to be executed

If necessaryHolds the address

of memory reads/writes

Holds first wordof currently

executing instruction

Holds operands orintermediate results

Performs all logical or arithmeticoperations

( ADD, SHIFT, etc. ) Holds result of ALUOperations


Programmer’s model of an MC68000

D0

D1

D2

D3

D4

D5

D6

0

LSB8,716,1531

MSB

DATA REGISTERS

A0

A1

A2

A3

A4

A5

A6

0 LSB16,1531MSB

ADDRESS REGISTERS

0LSB

16,1531

MSB

A7 (USP)

USER STACK POINTER

031

PC

PROGRAM COUNTER

CCR

07

CONDITION CODE REGISTER

016,1531

A7’ (SSP)

SUPERVISOR STACK POINTER

STATUS REGISTER

SR

015 8,7

CCR

D7


CCR Register

• The Condition Code Register, or CCR register, contains a set of 5 condition bits- Bits change constantly with the result of each instruction

- X BIT: Extend bit- Used with multi-precision arithmetic- N BIT: Negative bit- Indicates that the result is a negative

number- Z BIT: Zero bit: Indicates that the result is equal to zero- V BIT: Overflow: Indicates that the result may have

exceeded the range of the operand- C BIT: Carry bit: Indicates that a carry was generated in a

mathematical operation

X N Z V C CCR

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0


Effective Address

• The effective address, EA, determines how the operands of an instruction are to be accessed by the processor

• The kinds of EA’s are the addressing modes of the architecture• Consider the form of the opcode word shown below:

• MOVE.W instruction: Move the word contents of the memory location specified by the src EA to the memory location specified by the dst EA- This information is encoded in the 16 bits of the op code word

- OPCODE/SIZE = DB12-DB15 ( MOVE.W)- Source Effective Address = DB0-DB5- Destination Effective Address = DB6-DB11

• May have to retrieve additional words from memory to complete the instruction- Note: Not all instructions have the same form as the MOVE

instruction

MOVE.W dst EA src EA

15 12 11 6 5 0


Instruction format in memory

• Example: an immediate operand is the actual data value- Generally represented as OP CODE #DATA- Example: start MOVE.W #$0A55,D0 *Initialize

D0EVEN BYTE ODD BYTE

7 6 5 4 2 1 0 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OP CODE WORD

FIRST WORD SPECIFIES OPERATIONS AND MODES

IMMEDIATE OPERAND

IF ANY, ONE OR TWO WORDS

SOURCE EFFECTIVE ADDRESS EXTENSION


DESTINATION EFFECTIVE ADDRESS EXTENSION


•It is a MOVE.W instruction• The source operand is immediate data• The destination operand is register D0

•It is a MOVE.W instruction• The source operand is immediate data• The destination operand is register D0

• The immediate data value, $0A55 • The immediate data value, $0A55

Not usedNot used


Instruction format in memory(2)

• Example 2: Absolute operands exactly specify the locations of the data - Generally represented as: OP CODE source address,dest address- Example: MOVE.W $0A550000,$1000BB00

EVEN BYTE ODD BYTE

7 6 5 4 2 1 0 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OP CODE WORDFIRST WORD SPECIFIES OPERATIONS AND MODES

SOURCE EFFECTIVE ADDRESSHIGH ORDER WORD

SOURCE EFFECTIVE ADDRESSLOW ORDER WORD

•It is a MOVE.W instruction• The source operand is absolute address• The destination operand is absolute address

•It is a MOVE.W instruction• The source operand is absolute address• The destination operand is absolute address

• $0A55 • $0A55

• $0000• $0000DESTINATION EFFECTIVE ADDRESS

HIGH ORDER WORD

DESTINATION EFFECTIVE ADDRESSLOW ORDER WORD

• $1000 • $1000

• $BB00 • $BB00


• It is best to try to align memory accesses on natural boundaries- Some processors (X86) will allow accesses to occur for non-

aligned words - Requires multiple memory accesses to input data

• MC68000 processor does not allow non-aligned accesses- Will generate an exception trap and an error routine will need

to be called to recover

• Trying to address a word beginning at address 1 will cause a non-aligned access to occur

Word Alignment

01

23

Low order byte

High order byte


Flow charting (3)

Set up environment

Run Self-tests

Scan key board

KeyboardInput

Interpret keystroke

TEST = FALSE

TEST = TRUE

8

memory space of a typical system

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