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Accelerating the next technology revolution
Copyright ©2010 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.
Memory Overview and RRAM Materials Development at SEMATECH
Paul Kirsch,Director Front End ProcessesAugust 22, 2010
Nonvolatile Memory SeminarHot Chips ConferenceMemorial AuditoriumStanford University
5 August 2010 2
Outline
• NVM Memory Trends & Challenges
• Technology Space for RRAM
• Challenges and SEMATECH RRAM Results
High density, low cost, NVM (NAND) Y. N
ishi
, S.M
. Sze
, S
tanf
ord
Uni
v (s
ourc
e IT
RS
200
0)
April 2, 2010 3
System on Chip (SOC)Mobile
Dense, local memory – improve system performance
Future trends: Memory for mobile and SOC applications
• IMPACT: High density, low cost NVM important for mobile application
• IMPACT: Local (embedded) memory important for System on Chip
5 August 2010 4
Advantage Challenges“Speculative”
PriorityPhase Change RAM • Speed & cost vs. NOR • Density, Power (Ireset) production
SiN / Nano Crystal Charge Trap
• Relatively mature• difficult to beat floating gate• candidate for 3 -D
1
RRAM • High speed & density • Materials, I reset, Reliability 2
STT-RAM • endurance, speed , power• Magnetic domain size effect • Etch difficulty• Challenging materials
2
Mechanical memory• Power• Leakage
• Reliable operation• Scalability
4
Molecular memory • Density (Molecule size ~nm) • Poor thermal stability 5
Vertical String • 2-5x lower $$ vs. stacked • deposited tunnel ox• transistor in trench sidewall
1
Cross bar array • effective density below 4F 2• Litho $: more costly vs. NAND• selector device
2
Stacked • similar to current NAND • Litho $: more costly vs. NAND 3
Cel
lA
rchi
tect
ure
Sub 20nm memory cell, architecture candidates
5 August 2010 5
[1] W. Y. Choi, and T.-J. King Liu IEDM p. 603 (2007).[2] A. Driskill-Smith, Y. Huai Future Fab p. 28 (2007).[3] J. E. Green Nature v. 445 p. 414 (2007).[4] B. Yu IEEE Trans on Nanotech 7, p. 496 (2008).[5] Kryder, et. al. IEEE TRANS ON MAGNETICS, 45, NO. 10, (2009)
• MLC = NAND• Cost structure = NAND• Function, reliability = NAND• Density > NAND • Speed > NAND• RRAM, STT interesting.
0 10 20 30 40 50100
101
102
103
104
105
NW-PC
STT
NanowireMolecular
DRAM
PCFeRAM
NEMS SRAM
MRAM
NOR
low power (fJ/bit) mid power (pJ/bit) mid-hi power (low nJ/bit) high power (nJ/bit)
Switc
hing
Tim
e(re
ad+w
rite)
[ns]
Density AF2
NAND
RR
Sub 20nm memory benchmarking
Success Criteria: Future NVM
BL1
BL2
BL3
WL1 WL2 WL3
1F Unit cell = 4F 2
small A = small cell
Bit
cost
($/G
b)
Which space should RRAM target?Associated challenges to compete with DRAM/NAND/NOR
Program/write speed (ns)
DRAM
NAND
NOR
SRAM
0.01
0.1
1
10
100
101 102 103 104 105 106 107
HDD
3-D multilayer crossbar(dense NVM)
1T1R BEOL memory (SOC memory)
To achieve 3-D CrossBar:• $: 9 critical levels
in 4 layer stack• EUV?• DP?• Selector• Etch
25nm L/S
To Compete w/NAND• Cost • Reset current• MLC (density)• 3-D integration
To compete w/DRAM:• Better endurance• Better reset current• Current scaling• Uniformity
RRAM challenge: compete w/ NAND cost
April 2, 2010 6
RR
AM
: 10ns reported
Challenges with RRAM
• Too many materials (manufacturability?)
• Reducing reset currents (power)
• Uniformity
• Endurance
• Integration with selector device (1T1R, 1D1R)
5 August 2010 7
5 August 2010 8
Many RRAM materials: Many not manufacturable
H
Li
Na
K
Rb
Cs
Fr
Be
Mg
Ca
Sr
Ba
Ra
Sc
Y
La
Ac
Ti
Zr
Hf
Rf
V
Nb
Ta
Db
Cr
Mo
W
Sg
Mn
Tc
Re
Bh
Fe
Ru
Os
Hs
Co
Rh
Ir
Mt
Ni
Pd
Pt
Ds
Cu
Ag
Au
Rg
Zn
Cd
Hg
B
Al
Ga
In
Tl
C
Si
Ge
Sn
Pb
N
P
As
Sb
Bi
O
S
Se
Te
Po
F
Cl
Br
I
At
Ne
Ar
Kr
Xe
Rn
He
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu
Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
• Many materials risky to put into a semiconductor development line
X = Materials in RRAM literature report
5 August 2010 9
Which RRAM materials are manufacturing worthy?
H
Li
Na
K
Rb
Cs
Fr
Be
Mg
Ca
Sr
Ba
Ra
Sc
Y
La
Ac
Ti
Zr
Hf
Rf
V
Nb
Ta
Db
Cr
Mo
W
Sg
Mn
Tc
Re
Bh
Fe
Ru
Os
Hs
Co
Rh
Ir
Mt
Ni
Pd
Pt
Ds
Cu
Ag
Au
Rg
Zn
Cd
Hg
B
Al
Ga
In
Tl
C
Si
Ge
Sn
Pb
N
P
As
Sb
Bi
O
S
Se
Te
Po
F
Cl
Br
I
At
Ne
Ar
Kr
Xe
Rn
He
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu
Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
• Focus on engineering materials that are already in the semiconductor fab (green)
X = Materials in RRAM literature report
X = Materials in fabs today
5 August 2010 10
STT-MRAM Materials also challenging
H
Li
Na
K
Rb
Cs
Fr
Be
Mg
Ca
Sr
Ba
Ra
Sc
Y
La
Ac
Ti
Zr
Hf
Rf
V
Nb
Ta
Db
Cr
Mo
W
Sg
Mn
Tc
Re
Bh
Fe
Ru
Os
Hs
Co
Rh
Ir
Mt
Ni
Pd
Pt
Ds
Cu
Ag
Au
Rg
Zn
Cd
Hg
B
Al
Ga
In
Tl
C
Si
Ge
Sn
Pb
N
P
As
Sb
Bi
O
S
Se
Te
Po
F
Cl
Br
I
At
Ne
Ar
Kr
Xe
Rn
He
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu
Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
X = Materials in STT-MRAM
11
PVD metal oxide RRAM development
• PVD ideal for Stoichiometry Control, thin, uniform films
• ALD films also developed, but may still need PVD for electrode.
• IMPACT: Correct material Me:O enables correct function.
O c
onte
nt in
RR
AM
(x
in M
eOx)
(a.
u.)
StoichiometricControl
Stoichiometriesof interest
Process Condition
5 August 2010
• Resistance switching currents (I reset) improved ~ 1000x.
• I reset improved to 1~10 µA range – desire 10x more improvement.
• IMPACT: Sub 1 µA device likely meets U.S. DARPA target for Switching Energy (fJ/bit)
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.510-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
Set
/ R
eset
Cur
rent
[A]
VD [V]
1 2 3 4 5 6 7 8 9 10
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
VD [V]
1 2 3 4 5 6 7 8 9 10
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
VD [V]
1 2 3 4 5 6 7 8 9 10
forming
1
2
4
3
0
Progress in reducing reset currents
12
Reducing Metal oxide RRAM Reset Currents
5 August 2010 13
• SEMATECH has exceeded member company target for 2010 Ireset
• 5 micro-amp reset currents achieved with manufacturable metal oxide
0
5
10
15
20
# M
ater
ials
S
cree
ned
ALD PVD
Process Type
Target
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10 100 1000 10000 100000
Z. Wei, IEDM 2008 p. 239
LRS HRS
Resistance (Ohm)
Pro
babi
lity
RRAM Reset Uniformity Improves
• Uniformity of High Resistance state improve across wafer (>300pts).• IMPACT: Uniformity is key issue for Manufacturability - Multilevel Cell
Improvement
5 August 2010 14
5 August 2010
-2 -1 0 1 210-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
100001 cycle100002 cycle100003 cycle100004 cycle100005 cycle100006 cycle100007 cycle100008 cycle100009 cycle
Voltage [V]C
urre
nt [A
]
After 105 cycles
-2 -1 0 1 210-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
100001 cycle100002 cycle100003 cycle100004 cycle100005 cycle100006 cycle100007 cycle100008 cycle100009 cycle
Voltage [V]C
urre
nt [A
]
-2 -1 0 1 210-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
100001 cycle100002 cycle100003 cycle100004 cycle100005 cycle100006 cycle100007 cycle100008 cycle
-2 -1 0 1 210-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
100001 cycle100002 cycle100003 cycle100004 cycle100005 cycle100006 cycle100007 cycle100008 cycle100009 cycle
Voltage [V]C
urre
nt [A
]
After 105 cyclesDC checkBetween 1st and 2nd 105 cycles
• Good initial RRAM cycling (2x10 5 +) – much work to do yet• IMPACT: If RRAM achieves fJ/bit and 10 15 cycles it competes with DRAM
100 101 102 103 104 10510-7
10-6
10-5
10-4
10-3
10-2
Vread=0.5V
Number of Cycles
Cur
rent
[A]
100 101 102 103 104 105
Number of Cycles
Vread=0.5VAfter 1e5 cycles
100 101 102 103 104 10510-7
10-6
10-5
10-4
10-3
10-2
Vread=0.5V
Number of Cycles
Cur
rent
[A]
100 101 102 103 104 105
Number of Cycles
Vread=0.5VAfter 1e5 cycles
Initial 105 cycles 2nd 105 cycles
Encouraging RRAM endurance check
15
• Further work needed on devices meeting Ireset, but encouraging initial data.
Metal oxide RRAM has demonstrated reasonable retention
100 101 102 103 104
1E-4
1E-5
1E-6Cur
rent
(A
)
April 2, 2010 16
Selector Challenge
Reduce RRAM Reset
Currents <1µA
Relax Selector
Drive Needs <106 A/cm2
5 August 2010 17
Selector Device
Bitline
Wordline
RRAMElement
• Why does reset current matter?
• SELECTOR lesser Ireset means lesser diode current requirements
• IMPACT: Selector flexibility eases challenge of array integration
D. Kau, Intel, IEDM 2009
1D1R
Trade-off
5 August 2010 18
O
OO
O
O
O
metal
metal
O
Basic metal oxide RRAM Mechanism
• Switching, retention, endurance controlled by defec ts
• IMPACT: Need to understand details for reliable product
Binary oxides : filament formation
OO atom
O vacancy
Conductive Filament
“Good” Insulator
SEMATECH test structureTest structure allows reproducible electrical / reliability data
Test Structure
Structure Purpose
1. Contact -type MIM structure
(x-section)
• Quick materials studies
2. Stack -type MIM
structure(X-section)
• Quick materials studies
3. 1T1R test structure(top view)
• Iso 1T1R, Iso 1R, • Cross Pt Array1T1R
• Detailed Ireset studies• Detailed parasitic studies• Array retention, endurance• 25nm x 25nm CD
Si
SiO2
Bottom electrode
TiNMetal cap
Top electrode
Metal Oxide
Substrate
Insulator
TEMOx
Bottom electrode
ILD
April 2, 2010 19
Overview of SEMATECH capabilities
State of Art Test Structure Design
Process Design
New Memory Materials
Sub 30nm Test Structure
Fabrication
Reliability & Parametric
Test
Transfer material, flow, equipment to
manufacturers
5 August 2010 20
Partner with universities
Partner with CNSE,SVTC
Partner with Universities
Partner with Mfg Companies
SEMATECH 1T1R Test Pattern Design
SEMATECH 20nm Nano Devices
SEMATECH Mfg Members Use Modules
5 August 2010 21
Conclusions
• Planar floating gate will be pushed to 2X nm.
• RRAM may compete as SOC memory (BEOL).
• RRAM may fit between NAND &DRAM cost space (stand alone)– Cost will be key– 4F2 cell with ~4 levels achieve effective 1F2 (MLC necessary)
• Materials challenges addressed– Manufacturable MeOx and electrode– Reset / set currents are approaching acceptable levels (1micro-amp)– Improved Uniformity Encouraging– Endurance, retention are promising, need improvement >1e5 cycles– Selector device and polar / bipolar design are challenges
• Quality test structures (1T1R) assist in accurate characterization, development