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Memory ManagementBasic Memory Management

By : Kaushik Vaghani

Prepared By : Kaushik Vaghani

Basic Memory Management

• Background

• Swapping

• Contiguous Memory Allocation

• Paging

• Structure of the Page Table

• Segmentation


Objectives

• To provide a detailed description of variousways of organizing memory hardware

• To discuss various memory-managementtechniques, including paging andsegmentation


Background

• Program must be brought (from disk) into main memoryand placed within a process for it to be run

• Main memory and registers built into processor itself areonly storage, CPU can access directly

• There are machine instructions that take memoryaddresses as arguments, but none that take diskaddresses.

• Therefore, any instructions in execution, and any databeing used by the instructions, must be in one of thesedirect-access storage devices.


Background

• If the data are not in memory, they must be moved therebefore the CPU can operate on them.

• Register access in one CPU clock (or less)

• Main memory can take many cycles

• Cache sits between main memory and CPU registers

• Protection of memory required to ensure correctoperation (to protect OS from user processes and userprocesses from one another). This protection must beprovided by the hardware.


Base and Limit Registers• We can provide this protection by using two registers,

usually a base and a limit.• A pair of base and limit registers

define the logical address space(separate memory space forseparate processes)

• The base register holds the smallestlegal physical memory address; thelimit register specifies the size ofthe range.

• base register = 300040 and the limitregister = 120900, then the programcan legally access addresses from300040 through 420939 (inclusive).


• Protection of memory space is accomplished by having the CPUhardware compare every address generated in user mode with thethese registers.

• Any attempt by a program executing in user mode to accessoperating-system memory or other users' memory results in a trap tothe operating system, which treats the attempt as a fatal error.

• This scheme prevents a user program from (accidentally orintentionally) modifying the code or data structures of either theoperating system or other users.


Binding of Instructions and Data to Memory Address

• Usually, a program resides on a disk as a binaryexecutable file.

• To be executed, the program must be brought intomemory and placed within a process.

• Depending on the memory management in use, theprocess may be moved between disk and memoryduring its execution.

• The processes on the disk that are waiting to bebrought into memory for execution form the inputqueue.



• The normal procedure is to select one of the processesin the input queue and to load that process intomemory.

• As the process is executed, it accesses instructions anddata from memory.

• Eventually, the process terminates, and its memoryspace is declared available.


Multistep Processing of a User Program

Symbolic addressEx: Count

Relocatable addressEx: 14 bytes from beginning of this module.

Absolute addressEx: 74014



• Classically, Address binding of instructions and data tomemory addresses can happen at any three differentstages : compile time, load time, execution time

• Compile time: If you know at compile time where the process will reside in memory, then absolute code can be generated.

– For example, if you know that a user process will residestarting at location R, then the generated compiler code willstart at that location and extend up from there. If, at somelater time, the starting location changes, then it will benecessary to recompile this code.

– The MS-DOS .COM-format programs are bound at compiletime.



• Load time: Compiler must generate relocatable code ifmemory location is not known at compile time.

– In this case, final binding is delayed until load time. Ifthe starting address changes, we need only reload theuser code to incorporate this changed value.

• Execution time: Binding delayed until run time if theprocess can be moved during its execution from onememory segment to another.


Logical vs. Physical Address Space

• The concept of a logical address space that is bound to aseparate physical address space is central to propermemory management

– Logical address – address generated by the CPU; referredto as logical address

– Physical address – address seen by the memory unit

• Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical andphysical addresses differ in execution-time address-bindingscheme. In this case logical address is referred as a virtualaddress.


Logical vs. Physical Address Space

• The set of all logical addresses generated by a program is alogical address space.

• The set of all physical addresses corresponding to theselogical addresses is a physical address space.

• Thus, in the execution-time address-binding scheme, thelogical (virtual) and physical address spaces differ.

• The run-time mapping from virtual to physical addresses isdone by a hardware device called the Memory-Management Unit (MMU).


Memory-Management Unit (MMU)

• Hardware device that maps virtual to physicaladdress

• In this scheme, base register is now called arelocation register.

• In MMU scheme, the value in the relocationregister is added to every address generated bya user process at the time it is sent to memory

• The user program deals with logical addresses;it never sees the real physical addresses


Dynamic relocation using a relocation register

Memory-Management Unit (MMU)

For example,

• if the base is at 14000,then an attempt bythe user to addresslocation 0 isdynamically relocatedto location 14000;

• an access to location346 is mapped tolocation 14346.


Dynamic Loading

• Routine is not loaded until it is called

• Better memory-space utilization; unusedroutine is never loaded

• Useful when large amounts of code areneeded to handle infrequently occurringcases

• No special support from the operating systemis required implemented through programdesign


Swapping• A process must be in memory to be executed.

• A process, however, can be swapped temporarily out of memory toa backing store, and then brought back into memory for continuedexecution.

• A variant of this swapping policy is used for priority-basedscheduling algorithms.

• If a higher-priority process arrives and wants service, the memorymanager can swap out the lower-priority process and then load andexecute the higher-priority process.

• When the higher-priority process finishes, the lower-priority processcan be swapped back in and continued. This variant of swapping issometimes called roll out and roll in.


Swapping (Cont.)• Backing store – It is commonly a fast disk. It must be large enough to

accommodate copies of all memory images for all users, and it mustprovide direct access to these memory images.

• Normally, a process that is swapped out will be swapped back intothe same memory space it occupied previously.

• This restriction is dictated by the method of address binding. Ifbinding is done at assembly or load time, then the process cannotbe easily moved to a different location.

• If execution-time binding is being used, however, then a process canbe swapped into a different memory space, because the physicaladdresses are computed during execution time.


Schematic View of Swapping


Swapping (Cont.)

• The system maintains a ready queue consisting of all processeswhose memory images are on the backing store or in memoryand are ready to run.

• Whenever the CPU scheduler decides to execute a process, it callsthe dispatcher.

• The dispatcher checks to see whether the next process in thequeue is in memory.

• If it is not, and if there is no free memory region, the dispatcherswaps out a process currently in memory and swaps in thedesired process.

• It then reloads registers and transfers control to the selectedprocess.


Swapping (Cont.)• Major part of swap time is transfer time; total transfer time is

directly proportional to the amount of memory swapped

• Swapping is constrained by other factors as well. If we want toswap a process, we must be sure that it is completely idle.

• A process may be waiting for an I/0 operation when we want toswap that process to free up memory.

• However, if the I/0 is asynchronously accessing the user memoryfor I/0 buffers, then the process cannot be swapped.

• Assume that the I/0 operation is queued because the device isbusy. If we were to swap out process P1 and swap in process P2,the I/0 operation might then attempt to use memory that nowbelongs to process P2 .


Swapping (Cont.)

• There are two main solutions to this problem: never swap aprocess with pending I/0, or execute I/0 operations only intooperating-system buffers.

• Transfers between operating-system buffers and process memorythen occur only when the process is swapped in.


Contiguous Memory Allocation• Main memory usually divided into two partitions:

– One for Resident operating system,

– One for User processes.

• We can place the operating system in either low memory or highmemory.

(High memory is memory which is not permanently mapped in thekernel's address space. Low memory is the inverse: Memory that isalways mapped into the kernel's address space.)

• The major factor affecting this decision is the location of theinterrupt vector.

• Since the interrupt vector is often in low memory, programmersusually place the operating system in low memory as well.


Contiguous Allocation (Cont.)• We usually want several user processes to reside in memory at the

same time.

• We therefore need to consider how to allocate available memoryto the processes that are in the input queue waiting to be broughtinto memory.

• In contiguous memory allocation, each process is contained in asingle contiguous section of memory.


Contiguous Allocation (Cont.)

• Relocation registers used to protect user processes fromeach other, and from changing operating-system code anddata

– Base register contains value of smallest physical address

– Limit register contains range of logical addresses – eachlogical address must be less than the limit register

– MMU maps logical address to physical addressdynamically.

Memory Mapping and Protection



• When the CPU scheduler selects a process forexecution, the dispatcher loads the relocation andlimit registers with the correct values as part of thecontext switch.

• Because every address generated by a CPU is checkedagainst these registers, we can protect both theoperating system and the other users’ programs anddata from being modified by this running process.



Hardware support for relocation and limit registers




• One of the simplest methods for allocating memory is to dividememory into several fixed-sized partitions.

• Each partition may contain exactly one process. Thus, the degree ofmultiprogramming is bound by the number of partitions.

• In this multiple-partition method, when a partition is free, aprocess is selected from the input queue and is loaded into thefree partition.

• When the process terminates, the partition becomes available foranother process.

• This method was originally used by the IBM OS/360 operatingsystem (called MFT); it is no longer in use.

Memory Allocation (Fixed Partition)



• The variable-partition method is a generalization of thefixed-partition scheme (called MVT); it is used primarily inbatch environments.

• In this scheme, the operating system keeps a tableindicating which parts of memory are available and whichare occupied.

• Initially, all memory is available for user processes and isconsidered one large block of available memory a hole.Eventually, memory contains a set of holes of various sizes.

Memory Allocation (Variable Partition)



• As processes enter the system, they are put into aninput queue.

• The operating system takes into account the memoryrequirements of each process and the amount ofavailable memory space in determining whichprocesses are allocated memory.

• When a process is allocated space, it is loaded intomemory, and it can then compete for CPU time.

• When a process terminates, it releases its memorywhich the operating system may then fill with anotherprocess from the input queue.



– When a process arrives, it is allocated memoryfrom a hole large enough to accommodate it

– Operating system maintains information about:a) allocated partitions b) free partitions (hole)

OS

process 5

process 8

process 2

OS

process 5

process 2

OS

process 5

process 2

OS

process 5

process 9

process 2

process 9

process 10




Dynamic Storage-Allocation ProblemThis procedure is a particular instance of the general dynamicstorage allocation problem.

How to satisfy a request of size n from a list of free holes

• First-fit: Allocate the first hole that is big enough.

• Best-fit: Allocate the smallest hole that is big enough; mustsearch entire list, unless the list is ordered by size

– Produces the smallest leftover hole

• Worst-fit: Allocate the largest hole; must also search entire list

– Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed andstorage utilization


Fragmentation

• External Fragmentation – total available memory space exists to satisfy a request, but it is not contiguous

• Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used

• Reduce (solution to) external fragmentation by compaction

– Shuffle memory contents to place all free memory together in one large block

– Compaction is not always possible, If relocation is static and is done at assembly or load time.

– Compaction is possible only if relocation is dynamic, and is done at execution time


Fragmentation (Cont.)– If addresses are relocated dynamically, relocation requires only

moving the program and data and then changing the base register toreflect the new base address.

– The simplest compaction algorithm is to move all processes towardone end of memory; all holes move in the other direction, producingone large hole of available memory. This scheme can be expensive.

– I/O problem

• Latch job in memory while it is involved in I/O

• Do I/O only into OS buffers

– Another possible solution to the external-fragmentation problem is topermit the logical address space of the processes to benoncontiguous, thus allowing a process to be allocated physicalmemory wherever such memory is available.

– Two complementary techniques achieve this solution: paging andsegmentation. Prepared By : Kaushik Vaghani

Paging• Paging is a memory-management scheme that permits the

physical address space of a process to be noncontiguous.

• It also solves the considerable problem of fitting memorychunks of varying sizes onto the backing store; most memorymanagement schemes used before the introduction of pagingsuffered from this problem.

• Because of its advantages over earlier methods, paging in itsvarious forms is used in most operating systems.

• Traditionally, support for paging has been handled byhardware. However, recent designs have implemented pagingby closely integrating the hardware and operating system,especially on 64-bit microprocessors.


Method :

• Divide physical memory into fixed-sized blocks called frames

• Divide logical memory into blocks of same size called pages (sizeis typically power of 2, varying between 512 bytes and 16 MB perpage).

• Keep track of all free frames

• To run a process of size n pages, need to find n free frames andload process

• Set up a page table to translate logical to physical addresses

• Internal fragmentation

Paging (Cont.)


Address Translation Scheme• Address generated by CPU is divided into:

– Page number (p) – used as an index into a page table which contains base address of each page in physical memory

– Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit

– For given logical address space 2m and page size 2n

page number page offset

p d

m - n n


Paging Hardware


Paging Model of Logical and Physical Memory


Paging Example

32-byte memory and 4-byte pages

Example:

1. Logical address 0 is page 0, offset 0.Indexing into the page table, we findthat page 0 is in frame 5. Thus, logicaladdress 0 maps to physical address 20[= (5 x 4) + 0].

2. Logical address 3 (page 0, offset 3)maps to physical address 23 [ = (5 x 4)+ 3].

3. Logical address 4 is page 1, offset 0;according to the page table, page 1 ismapped to frame 6. Thus, logicaladdress 4 maps to physical address 24 [= ( 6 x 4) + O].

4. Logical address 13 maps to physicaladdress 9.


Paging (Cont.)

• When we use a paging scheme, we have no externalfragmentation: any free frame can be allocated to a process thatneeds it. However, we may have some internal fragmentation.

• Notice that frames are allocated as units. If the memoryrequirements of a process do not happen to coincide with pageboundaries, the last frame allocated may not be completely full.

• For example, if page size is 2,048 bytes, a process of 72,766 byteswill need 35 pages plus 1,086 bytes. It will be allocated 36 frames,resulting in internal fragmentation of 2,048 - 1,086 = 962 bytes.

• If process size is independent of page size, we expect internalfragmentation to average one-half page per process. Thisconsideration suggests that small page sizes are desirable.


Free Frames

Before allocation After allocationPrepared By : Kaushik Vaghani

Paging (Cont.)

• When a process arrives in the system to be executed, its size,expressed in pages, is examined.

• Each page of the process needs one frame. Thus, if the processrequires n pages, at least n frames must be available in memory.

• If n frames are available, they are allocated to this arrivingprocess.

• The first page of the process is loaded into one of the allocatedframes, and the frame number is put in the page table for thisprocess.

• The next page is loaded into another frame, its frame number isput into the page table, and so on.


Structure of the Page Table

• Hierarchical Paging

• Hashed Page Tables

• Inverted Page Tables


Hierarchical Page Tables• Most modern computer systems support a large logical address

space (232 to 264). In such an environment, the page table itselfbecomes excessively large.

• For example, consider a system with a 32-bit logical address space.If the page size in such a system is 4 KB (212), then a page table mayconsist of up to 1 million entries (232 /212).

• Assuming that each entry consists of 4 bytes, each process mayneed up to 4MB of physical address space for the page table alone.

• Clearly, we would not want to allocate the page table contiguouslyin main memory. One simple solution to this problem is to dividethe page table into smaller pieces.


Hierarchical Page Tables

• Break up the logical address space into multiple page tables

• A simple technique is a two-level page table


• A logical address (on 32-bit machine with 4 KB page size) is dividedinto:

– a page number consisting of 20 bits

– a page offset consisting of 12 bits

• Since we page the page table, the page number is further divided into:

– a 10-bit page number

– a 10-bit page offset

• Thus, a logical address is as follows:

where p1 is an index into the outer page table, and p2 is thedisplacement within the page of the outer page table

page number page offset

p1 p2 d

10 10 12

Two-Level Page-Table Scheme


Two-Level Page-Table Scheme


Address-Translation for a two level paging


Three-level Paging Scheme


Hashed Page Tables

• Common in address spaces > 32 bits

• A common approach for handling address spaces larger than 32bits is to use a hashed page table, with the hash value being thevirtual page number.

• Each entry in the hash table contains a linked list of elements that hash to the same location (to handle collisions).

• Each element consists of three fields:

(1) the virtual page number,

(2) the value of the mapped page frame, and

(3) a pointer to the next element in the linked list.


Hashed Page TablesMethod:

• The virtual page number in the virtual address is hashed into thehash table.

• The virtual page number is compared with field 1 in the firstelement in the linked list.

• If there is a match, the corresponding page frame (field 2) isused to form the desired physical address.

• If there is no match, subsequent entries in the linked list aresearched for a matching virtual page number.


Hashed Page Table


Inverted Page Table• One entry for each real page of memory

• Entry consists of the virtual address of the page stored in that realmemory location, with information about the process that ownsthat page

• Decreases memory needed to store each page table, but increasestime needed to search the table when a page reference occurs

• Use hash table to limit the search to one — or at most a few —page-table entries


Inverted Page Table Architecture


Segmentation• An important aspect of memory management that became

unavoidable with paging is the separation of the user's view ofmemory from the actual physical memory.

• Segmentation is a Memory-management scheme that supportsuser view of memory

• A program is a collection of segments. A segment is a logical unitsuch as:

– main program,

– procedure, function, or method,

– object, local variables, global variables, stack, symbol table,arrays and so on..


User’s View of a Program


Logical View of Segmentation

1

3

2

4

1

4

2

3

user space physical memory space


Segmentation• Each of these modules or data elements is referred to by name.

We talk about "the stack," "the math library," "the main program,"without caring what addresses in memory these elements occupy.

• Users are not concerned with whether the stack is stored beforeor after the Sqrt() function.

• Each of these segments is of variable length

• Elements within a segment are identified by their offset from thebeginning of the segment: the first statement of the program, theseventh stack frame entry in the stack, the fifth instruction of theSqrt (), and so on.

• Segmentation is a memory-management scheme thatsupports this user view of memory.


Segmentation

• A logical address space is a collection of segments.

• Each segment has a name and a length.

• The addresses specify both the segment name and theoffset within the segment.

• The user therefore specifies each address by twoquantities: a segment name and an offset.

(Contrast this scheme with the paging scheme, in which the userspecifies only a single address, which is partitioned by thehardware into a page number and an offset, all invisible to theprogrammer.)


Segmentation• For simplicity of implementation, segments are numbered and are

referred to by a segment number, rather than by a segment name.Thus, a logical address consists of a two tuple:

<segment-number, offset>

• Normally, the user program is compiled, and the compilerautomatically constructs segments reflecting the input program.

• A Compiler might create separate segments for the following:

1. The code

2. Global variables

3. The heap, from which memory is allocated

4. The stacks used by each thread

5. The standard C libraryPrepared By : Kaushik Vaghani

Segmentation• Libraries that are linked in during compile time might be

assigned separate segments. The loader would take all thesesegments and assign them segment numbers.

• Although the user can now refer to objects in the program bya two-dimensional address, the actual physical memory isstill, of course, a one-dimensional sequence of bytes.

• Thus, we must define an implementation to map twodimensional user-defined addresses into one-dimensionalphysical addresses.

• This mapping is effected by a segment table.Prepared By : Kaushik Vaghani

Segmentation• Each entry in the segment table has:

– a segment base : contains the starting physical address wherethe segment resides in memory

– a segment limit : specifies the length of the segment

• A logical address consists of two parts:

a segment number: s, and an offset into that segment: d.

• The segment number is used as an index to the segmenttable. The offset d of the logical address must be between 0and the segment limit.

• When an offset is legal, it is added to the segment base toproduce the address in physical memory.


Segmentation Hardware


Example of Segmentation


Example: The Intel Pentium

• Supports both segmentation and segmentation with paging

• CPU generates logical address

– Given to segmentation unit

• Which produces linear addresses

– Linear address given to paging unit

• Which generates physical address in main memory

• Paging units form equivalent of MMU


Logical to Physical Address Translation in Pentium


Intel Pentium Segmentation


Pentium Paging Architecture


Linear Address in Linux

Broken into four parts:


Three-level Paging in Linux


Thank You


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