memory management 2010
TRANSCRIPT
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Chapter 4:Memory Management
Basic Memory ManagementRelocation and protectionSwappingVirtual MemoryPagingSegmentationPaging with segmentation
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Ideally programmers want memory that is◦ large◦ fast◦ non volatile
Memory hierarchy ◦ small amount of fast, expensive memory –
cache ◦ some medium-speed, medium price, volatile
main memory RAM)◦ Tens of hundreds of gigabytes of slow, cheap
, non-volatile disk storage
Memory manager handles the memory hierarchy
Memory manager :Memory manager :◦which parts of memory are in use
and which parts are not in use◦Allocate and deallocate memory◦Manage swapping between main
memory and disk when main memory is too small to hold all the processes.
Operating System Concepts
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Basic Memory ManagementMonoprogramming without Swapping or Paging
Three simple ways of organizing memory
- an operating system with one user process
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Multiprogramming with Fixed Partitions
Fixed memory partitions◦separate input queues for each
partition◦single input queue
1. When job arrives, it can be put into the input queue for the smallest partition large enough o hold it.
2. May be small jobs have to wait to get into memory, even though plenty of memory is free.
Whenever a partition becomes free, the job closest to the front of the queue that fits in it could be loaded into the empty partition and run.
Search the whole input queue and pick the largest job that fits.
At least one small partition Job may not be skipped over
more than k times.
Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program.
User programs go through several steps before being run.
Operating System Concepts
Multistep Processing of a User Program Multistep Processing of a User Program
Operating System Concepts
Logical vs. Physical Address Logical vs. Physical Address SpaceSpace
Logical address – generated by the CPU; also referred to as virtual address.
Physical address – address seen by the memory unit.
Logical and physical addresses are the same in compile-time and load-time address-binding schemes;
logical (virtual) and physical addresses differ in execution-time address-binding scheme.
Operating System Concepts
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Relocation and Protection
Cannot be sure where program will be loaded in memory◦ address locations of variables, code routines
cannot be absolute◦ must keep a program out of other processes’
partitions
RelocationRelocationWhen a program is linked the
linker must know at what address the program will begin in memory.
Call to a procedure at absolute address 100
Program is Loaded in partition 1100K+100
Operating System Concepts
Dynamic relocation using a relocation Dynamic relocation using a relocation registerregister
Operating System Concepts
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Protection
Divide memory into blocks of 2-KB bytes4-bit protection code to each block (IBM)PSW contained 4-bit keyUse base and limit values
◦ address locations added to base value to map to physical address
◦ address locations larger than limit value is an error
Hardware Support for Relocation and Limit Hardware Support for Relocation and Limit RegistersRegisters
Operating System Concepts
SwappingSwapping A process can be swapped temporarily out of memory to a
backing store, and then brought back into memory for continued execution.
Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images.
Operating System Concepts
Schematic View of Schematic View of SwappingSwapping
Operating System Concepts
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Swapping (1)
Memory allocation changes as ◦ processes come into memory◦ leave memory
Shaded regions are unused memory
Operating System Concepts
swappingComplicates allocation and
deallocation of memory as well as keeping track of it….
Memory compaction : moving one by one all the processes downward as far as possible.
It is usually not done because it requires a lot of CPU time.
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When memory is assigned dynamically os must manage it.
Two ways to keep track of memory usage◦Bitmaps◦Linked list.
Operating System Concepts
Memory Management with Bit Maps
Part of memory with 5 processes, 3 holes◦ tick marks show allocation units◦ shaded regions are free
Corresponding bit mapSame information as a list
Operating System Concepts
Size of allocation unit is important design issue
Smaller the allocation unit the larger the bitmap
Larger the allocation unit , smaller bitmap , but memory may be wasted in the last unit of the process.
Problem : searching a bitmap for a given length is slow operation
Operating System Concepts
Memory Management with Linked Lists
Four neighbour combinations for the terminating
process X
Operating System Concepts
When the processes and holes are kept on a list sorted by address, several algorithms can be used to allocate memory for a newly created process.
First fitNext fitBest fitWorst fitQuick fit
Operating System Concepts
ALGORITHM: First fit :
◦ scan the list of segments until it finds a hole that is big enough to hold process.
◦ The hole is then broken up into two pieces, one for the process and one for the unused memory.
Next fit : ◦ It works the same way as first fit, except
that it keeps track of where it is finds a suitable hole.
◦ The next time it is called to find the hole, it starts searching the list from the place where it left off last time, instead of always at the begging as first fit does.
Best fit : ◦The memory manager scans entire list
of segments and takes the smallest hole that is adequate.
Worst fit : ◦The memory manager scans entire list
of segments and takes the largest available hole .
Operating System Concepts
Quick fit :
◦The memory manager maintains separate lists for common size requested.
◦With quick fit, finding a hole of the required size is extremely fast
◦when a process terminates or is swapped out, finding its neighbours to see if a merge is possible is expensive.
ExampleConsider a swapping system in
which memory consists of the following hole sizes in memory order :
10 4 20 18 7 9 12 15 which hole is taken for successive
requests of a. 12 b. 10 c. 9 for first fit? Repeat the question
for best fit, worst fit, and next fit.
Operating System Concepts
Virtual MemorySplit program into pieces called
overlays.Swapping of overlays in and out
done by system
Ex: 16-MB program can run on 4-MB machine….
Operating System Concepts
Virtual MemoryVirtual address : program
generated address◦Virtual address space is divided up
into units called pages.Physical address : address seen
by memory unit◦Physical address space is divided
into unit called page frame.◦Page and page frame are always
same size.
Memory-Management Unit Memory-Management Unit ((MMUMMU))Hardware device that maps virtual
to physical address.
In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory.
The user program deals with logical addresses; it never sees the real physical addresses.
Operating System Concepts
Operating System Concepts
Virtual MemoryPaging (1)
The position and function of the MMU
Operating System Concepts
Paging (2)
The relation between virtual addresses and physical memory addresses given by page table
Operating System Concepts
Page Tables (1)
Internal operation of MMU with 16 bit,4 KB pages
Operating System Concepts
Page TableThe page number is used as an
index into the page table, yielding the number of the page frame…
P/A bit is o, trap to the OS.P/A bit is 1, the page frame
number found in the page table is copied to the high order 3 bits of the output register…
Operating System Concepts
Page Tables Entry
Typical page table entry Page frame number: Goal of page
mapping to locate this value. Present/absent bit: If 1-entry is valid
and can be used. If 0-virtual page to which the entry belongs is not currently in memory.
Protection bit: It tells that what kind of access are permitted.
Operating System Concepts
Page Table EntryModified and referenced bits : It keep track
of page usage. When a page is written to ,the h/w automatically sets the modified bit.◦ if the page in it has been modified (i.e. is “dirty”), it
must be written back. ◦ If it has not been modified (i.e. is “clean”), it can be
just be abandoned.Referenced Bit: It is set whenever a page is
referenced either for reading or writing. Its value help the O.S choose a page to evict when a page fault occurs.
Caching : This feature is important for page that map onto device reg. rather than memory.
Machine that have separate I/O space and do not use memory mapped I/O do not need this bit.
Page Table
Page table can be extremely large
The mapping must be fast◦Each process needs its own page
table◦Mapping must be done on every
memory referenceSolution :◦single page table consisting of an
array of fast hardware register◦ExpensiveIt can be entirely in main memory
Operating System Concepts
Two-Level Paging Two-Level Paging ExampleExample
A logical address (on 32-bit machine with 4K page size) is divided into:◦ a page number consisting of 20 bits.◦ a page offset consisting of 12 bits.
Since the page table is paged, the page number is further divided into:◦ a 10-bit page number. ◦ a 10-bit page offset.
Thus, a logical address is as follows:
here pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table.
Operating System Concepts
page number page offset
pi p2 d
10 10 12
Operating System Concepts
Two Level Page Tables
In this method avoid keeping all the page tables in memory all time. Those that are not needed should not be kept around.
Second-level page tables
Top-level page table
Implementation of Page Implementation of Page TableTablePage table is kept in main memory.Page-table base register (PTBR) points
to the page table.Page-table length register (PRLR)
indicates size of the page table.In this scheme every data/instruction
access requires two memory accesses. One for the page table and one for the data/instruction.
The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)
Operating System Concepts
Operating System Concepts
TLBs – Translation Lookaside Buffers`
A TLB to speed up pagingTo see virtual page is present in TLB –
comparing all the entries simultaneously.
Paging Hardware With TLBPaging Hardware With TLB
Operating System Concepts
Inverted Page TableInverted Page TableOne entry for each page frame of
memory.Entry consists of the virtual
address of the page stored in that real memory location, with information about the process that owns that page.
Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs.
Use hash table to limit the search to one — or at most a few — page-table entries.
Operating System Concepts
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Inverted Page Tables
Comparison of a traditional page table with an inverted page table
Inverted Page Table Inverted Page Table ArchitectureArchitecture
Operating System Concepts
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Page Replacement Algorithms
Page fault forces choice ◦which page must be removed◦make room for incoming page
Modified page must first be saved◦unmodified just overwritten
Better not to choose an often used page◦will probably need to be brought
back in soon
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FIFO Page Replacement Algorithm
Maintain a linked list of all pages ◦ in order they came into memory◦ With the page at the head of the list the
oldest one and the page at the tail the most recent arrival.
Page at beginning of list replaced
Disadvantage◦ Throwing out heavily used page.
Operating System Concepts
FIFO Page Replacement
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Second Chance Page Replacement Algorithm
Operation of a second chance◦ pages sorted in FIFO order◦ if fault occurs at time 20, A has R bit set
(numbers above pages are loading times)
Operating System Concepts
Second-Chance (clock) Page-Replacement Algorithm
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The Clock Page Replacement Algorithm
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Optimal Page Replacement Algorithm
◦Optimal but unrealizable
◦Working: One of these pages will be referenced on the very next instruction.
◦Other pages may not be referenced until 10, 100 and or perhaps1000 instruction later.
◦ Each page can be labelled with the number of instruction that will be executed before that page is first referenced.
Optimal Page Replacement Algorithm
◦The page with the highest label should be removed.
◦At the time of page fault , the OS has no way of knowing when each of the page will be referenced next.
Not Recently Used :• When a process is started up, both page
bits for all its pages are set to 0 by the O.S.
• Periodically (e.g. on each clock interrupt), the R bit is cleared, to distinguish pages that have not been referenced recently from those that have been.
Operating System Concepts
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Not Recently Used Page Replacement Algorithm
Pages are classified1. not referenced, not modified(0 0)
1. Best page to replace
2. not referenced, modified(0 1)1. Not quite good , because the page will need to be
written out before replacement
3. referenced, not modified(1 0)1. It probably will be used again soon
4. referenced, modified(1 1)1. It probably will be used again soon , and the page
will need to be written out to disk before replacement
NRU removes page at random◦lowest numbered nonempty class
◦It is better to remove a modified page that has not been referenced in at least one clock tick than a clean page that is in heavy us.
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Least Recently Used (LRU)Assume pages used recently will used
again soon◦throw out page that has been unused for
longest timeMust keep a linked list of pages
◦most recently used at front, least at rear◦update this list every memory
reference !! Finding a page in the list, deleting it, and then moving it to the front is a very time consuming operation, even in hardware.
Alternatively keep counter in each page table entry ◦choose page with lowest value counter
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LRU using Matrix
0,1,2,3,2,1,0,3,2,3: the row whose value is lowest is the last recently used.
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NOT FREQUENTLY USED:
It requires a software counter associated with each page, initially zero.
At each clock interrupt the o.s. scans all the pages in memory.
For each page the R bit ,which is 0 or 1 , is added to the counter.
The counters are an attempt to keep track of how often each page has been referenced.
When page fault occurs, the page with the lowest counter is chosen for replacement.
Problem: It never forgets anything.
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Simulating LRU in Software
The aging algorithm simulates LRU in software
Note 6 pages for 5 clock ticks, (a) – (e)
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The Working Set Page Replacement Algorithm (1)
Demand paging: Pages are loaded only on demand not in advance.
During any phase of execution the process reference only a relatively small fraction of its pages.
Working set: The set of pages that a process is currently using is called its working set.
Thrashing : A program causing page fault every few instruction is said to be thrashing.
Working set model: Many paging systems try to keep track of each process’ working set and make sure that it is in memory before letting the process run. This approach is called the working set model. ◦ It is greatly reduce the page fault rate.
Prepaging : Loading of page before letting process run is called prepaging.
Operating System Concepts
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The Working Set Page Replacement Algorithm
Current Virtual Time: Amount of CPU time a process has actually used has since it started
Working set of process is the set of pages it has referenced during the past (T) seconds of virtual time.
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The WSClock Page Replacement Algorithm
The WSClock Page Replacement Algorithm
1. R =0 •If the page is clean, remove
if the page is dirty(cant remove immediately) – to avoid process switch write to disk is scheduled but hand is advanced and the algorithm continues with next page.
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Review of Page Replacement Algorithms
Consider the following page reference string :
◦ 0 1 2 3 0 1 2 3 0 1 2 3 4 5 6 7◦ How many page fault occur in the
following replacement algorithms, assuming three frames.
I. FIFOII. LRUIII. Optimal
Example:Given a system with four page frames, the
following table indicates page, load time, last reference time, dirty bit, and reference bit.
Page L.T. Last reference
Dirty bit
Ref. bit
0 167 374 1 1
1 321 321 0 0
2 254 306 1 0
3 154 331 0 1
Which page will FIFO replace?◦ Ans : 3◦ FIFO selects the page loaded first, page 3 at
time 154Which page will LRU replace?
◦ Ans : 2Which page will NRU replace?
◦ Ans:1◦ NRU first looks for a clean page that was not
recently referenced.Which page will second chance replace?
◦ Second chance first checks the oldest page –page 3◦ Reference bit 1, it is reset and load time replace with
current time◦ Same for 0◦ So page 2 is selected
Given reference to the following pages by a program,0 9 0 1 8 1 8 7 8 7 1 2 8 2 7 8 2 3 8 3
How many page fault will occur if the program has three page frames available to it and uses:
1. FIFO 2. LRU 3. optimal replacement
On a simple paging system with 224 bytes of physical memory, 256 pages of logical address space and a page size of 210 bytes,
a. How many bytes are in page frame?b. How many bits in the physical address
specify the page frame number?c. How many entries are in the page table?d. What is the size of the logical address space?e. How many bits are needed to store an entry
in the page table? Assume each page table entry contains a valid/invalid bit in addition to the page frame number.
On a simple paging system with a page table containing 64 entries of 11 bits (including valid/invalid bit) each and a page size of 512 bytes,
a. How many bits are in the logical address specify the offset within the page?
b. How many bits are in the a logical address?
c. What is the size of the logical address space?
d. How many bits in the physical address specify the page frame number?
e. How many bits in the physical address specify the offset within the page frame?
Before Page Fault after
- - - 0 1 0 - -0 - - 9 2 9 0
-9 0 - 0 2 9 0
- 9 0 - 1 3 1 9
01 9 0
8 4 8 1 9
8 1 9
1 4 8 1 9
8 1 9
8 4 7 8 1
8 1 9
7 5 7 8 1
7 8 1
8 5 7 8 1
7 8 1
7 5 7 8 1
7 8 1
1 5 2 7 8
7 8 1
2 6 2 7 8
2 7 8
8 6 2 7 8
Before Page Fault after2 7 8 2 6 2 7 82 7 8 7 6 2 7 82 7 8 8 6 2 7 82 7 8 2 6 2 7 82 7 8 3 7 3 2 73 2 7 8 8 8 3 28 3 2 3 8 8 3 2
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Design Issues for Paging SystemsLocal versus Global Allocation Policies (1)
Original configurationLocal page
replacementGlobal page
replacement
Local versus Global Allocation Policiesfixed fraction of memory VS dynamic
If working set grows thrashing will result even if free page frame ,If working set shrinks local algorithm waste memory
The system must continually decide how many page frames to assign to each process.
No of pages proportional to process size.
Allocation must be updated dynamically
PFF(page fault frequency) : It tells when to increase or decrease a process page allocation but says nothing about which page to replace..
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Load ControlDespite good designs, system may
still thrash
When PFF algorithm indicates ◦some processes need more memory ◦but no processes need less
Solution :Reduce number of processes competing for memory◦swap one or more to disk, divide up
pages they held◦reconsider degree of multiprogramming
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Page Size (1) Small page size
◦internal fragmentation ◦programs need many pages, larger
page tables Large page size
◦programs need less pages, smaller page tables
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Page Size (2) s = average process size in bytes
◦ p = page size in bytes◦ e = each page entry requires e bytes◦ no. of pages needed per process =s/p◦ Page table space=se/p bytes◦ Internal fragmentation = p/2◦ Total overhead due to the page table and I.F. loss is
given by
2
s e poverhead
p
page table space space
internal fragmentatio
n
Optimized when
2p se
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Separate Instruction and Data Spaces
One address spaceSeparate I and D
spaces
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Shared Pages
Two processes sharing same program : sharing its page table
Shared PagesProgram text can be shared
Separate table for I-space and D-space
Each process has two pointers in its process table
Special data structures are needed to keep track of shared pages.
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Cleaning PolicyPaging works best when there are
plenty of free page frames.
Need for a background process, paging daemon◦periodically inspects state of memory
When too few frames are free◦selects pages to evict using a
replacement algorithm
To implement - two-hand circular list (clock)
◦Front hand controlled by paging daemon
◦Back hand is used for page replacement
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Implementation IssuesOperating System Involvement with Paging
Four times when OS involved with paging
1. Process creation determine program size create page table
2. Process execution MMU reset for new process TLB flushed
3. Page fault time determine virtual address causing
fault swap target page out, needed page in
4. Process termination time release page table, pages
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Page Fault Handling (1)1. Hardware traps to kernel, saving
the program counter on the stack.
2. Assembly code routine is started to save the General registers and other info.
3. OS determines page fault, tries to discover which virtual page needed
4. OS checks validity of address, seeks page frame
5. If selected frame is dirty, write it to disk , context switch take place, suspending faulting process and letting another process until disk transfer
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Page Fault Handling (2)
o OS brings schedules new page in from disk
o Page table updatedo Faulting instruction backed up to
the state when it began o Faulting process scheduledo Registers restoredo Program continues
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Backing Store
(a) Paging to static swap area
(b) Backing up pages dynamically
SwappingSpecial area on the disk-swap
areaAllocate space in advance : copy
entire process image to the swap area
Do not allocate in advance◦Allocate disk space for each page
when it is swapped out and deallocate when swap back in
◦There must be table per process telling for each page on disk where it is.
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Segmentation (1)
One-dimensional address space with growing tables
One table may bump into another
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Segmentation (2): provide machine with many completely independent address space
Allows each table to grow or shrink, independently
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Segmentation (3)
Comparison of paging and segmentation
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Implementation of Pure Segmentation
(a)-(d) Development of checkerboarding(e) Removal of the checkerboarding by
compaction
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Segmentation with Paging: MULTICS
Descriptor segment points to page tables
Segment descriptor
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Segmentation with Paging: MULTICS (2)
A 34-bit MULTICS virtual address
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Segmentation with Paging: MULTICS (3)
Conversion of a 2-part MULTICS address into a main memory address
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Segmentation with Paging: MULTICS (4)
Simplified version of the MULTICS TLB
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Segmentation with Paging: Pentium (1)
A Pentium selector
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Segmentation with Paging: Pentium(2)
Pentium code segment descriptor
Data segments differ slightly
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Segmentation with Paging: Pentium (3)
Conversion of a (selector, offset) pair to a linear address
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Segmentation with Paging: Pentium (4)
Mapping of a linear address onto a physical address