Memory HierarchyDesign

Group Members

Ammarah Khalid (12-CS-01) Farwa Abdul Hanan (12-CS-13) Zainab Khalid (12-CS-33) Aniqa Javed (12-CS-34)

Introduction

Programmers want unlimited amounts of memory with low latency

Fast memory technology is more expensive per bit than slower memory

Solution: organize memory system into a hierarchy

Memory Hierarchy

The memory hierarchy is a concept used for storing & discussing performance issues in computer architectural design

The goal is to provide a memory system with cost per byte almost as low as the cheapest level of memory and speed almost as fast as the fastest level

Memory Hierarchy Design

Main Memory

Disk Storage

Back Storage

Cache

Registers

Back Storage• Offline memory• Used for Backup

Back Storage

Disk Storage• Online memory• Secondary Storage

Disk Storage

Back Storage

Main Memory• Primary Memory• Instructions

resides in main memory Main Memory

Disk Storage

Back Storage

Cache• High speed memory• Costly but Fast• Store CPU executed

outputMain Memory

Disk Storage

Back Storage

Cache

Registers• Part of CPU• Temporary memory

Main Memory

Disk Storage

Back Storage

Cache

Registers

Principle of locality

Principle of locality, also known as the, locality of reference it is a term for the phenomenon in which the same values, or related

storage locations, are frequently accessed.

Memory Hierarchy Basics

Memory Performance Gap

Memory Hierarchy Basics

When a word is not found in the cache The word must be fetched from the memory and placed in the cache

before continuing Each cache block includes a tag to see which memory address it

corresponds to. Most popular scheme is set associative, where a set is a group of blocks

in the cache Then place block into cache in any location within its set, determined by

address(block address) MOD (number of sets)

Memory Hierarchy Basics

n sets => n-way set associative Direct-mapped cache => one block per set Fully associative => one set

Writing to cache: two strategies Write-through

A write-through cache updates the item in the cache and writes through to update main memory Write-back

A write-back cache only updates the copy in the cache. When the block is about to be replaced, it is copied back to memory

Both write strategies can use a write buffer to allow the cache to proceed as soon as the data is placed in the buffer

Memory Hierarchy Basics

Miss rate Fraction of cache access that result in a miss

Causes of misses Compulsory

First reference to a block Compulsory misses are those that occur even if you had an infinite cache.

Capacity Capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and

later retrieved. Conflict

Conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set.

Memory Hierarchy Basics

where Hit time is the time to hit in the cache and Miss penalty is the time to replace the block from memory (that is, the cost of a miss). Average memory access time is still an indirect measure of performancealthough it is a better measure than miss rate, it is not a substitute for execution time

Cache Optimization

Basic Cache Optimizations

Larger block size to reduce miss rate Increase the block size so that more and more data from

frequently used addresses can be stored Drawbacks – Miss Penalty

Bigger caches to reduce miss rate Increase the cache size Drawbacks - potentially longer hit time of the larger cache

memory and higher cost and power.

Continue…

Higher associativity to reduce miss rate Increasing associativity to reduce conflict misses Cost of increased hit time

Multilevel caches to reduce miss penalty Adding another level of cache between cache and memory First level – to match the fast clock cycle in order to keep

pace with the increasing clock rate of the processor Second level – large enough to capture many accesses that

would go to main memory

Continue…

To avoid read after write hazards give priority to read misses over writes to reduce miss penalty and check the contents of the write buffer if no data conflicts then let the memory to read

Avoiding address translation during indexing of the cache to reduce hit time

Address translation

Virtual Memory

Virtual memory is a feature of an operating system (OS) that allows a computer to compensate for shortages of physical memory by temporarily transferring pages of data from random access memory (RAM) to disk storage. It contains virtual addresses

Translation Lookaside Buffer (TLB)

The translation lookaside buffer (TLB) is a cache for page table entries. It works in much the same way as the data cache: it stores recently accessed page table entries.

The END