*ATHENa Automated Tool for Hardware EvaluatioN Supported in part by the National Institute of Standards & Technology (NIST)

ECE 448 FPGA and ASIC Design with VHDL

ATHENa TeamVenkataVinnyMS CpE studentEkawatIce PhD CpE studentMarcin

PhD ECE studentRajesh

PhD ECE studentMichalPhD exchangestudent fromSlovakiaJohn MS CpE student

ECE 448 FPGA and ASIC Design with VHDL

ATHENa Automated Tool for Hardware EvaluatioN*Benchmarking open-source tool,written in Perl, aimed at an AUTOMATED generation of OPTIMIZED results for MULTIPLE hardware platformsCurrently under development at George Mason University. http://cryptography.gmu.edu/athena

ECE 448 FPGA and ASIC Design with VHDL

Why Athena?*"The Greek goddess Athena was frequently called upon to settle disputes between the gods or various mortals. Athena Goddess of Wisdom was known for her superb logic and intellect. Her decisions were usually well-considered, highly ethical, and seldom motivated by self-interest.

from "Athena, Greek Goddess of Wisdom and Craftsmanship"

ECE 448 FPGA and ASIC Design with VHDL

ATHENaServer

FPGA Synthesis and Implementation Result Summary+ Database Entries23HDL + scripts + configuration files1Database EntriesDownload scripts and configuration files8

Designer4HDL + FPGA ToolsUserDatabasequeryRanking of designs56Basic Dataflow of ATHENa0Interfaces + Testbenches

*

ECE 448 FPGA and ASIC Design with VHDL

*synthesizable source filesconfiguration files testbenchconstraint files result summary (user-friendly)database entries (machine- friendly)

ECE 448 FPGA and ASIC Design with VHDL

ATHENa Major Features (1)synthesis, implementation, and timing analysis in batch modesupport for devices and tools of multiple FPGA vendors:

generation of results for multiple families of FPGAs of a given vendor

automated choice of a best-matching device within a given family

*

ECE 448 FPGA and ASIC Design with VHDL

ATHENa Major Features (2)automated verification of designs through simulation in batch mode

support for multi-core processingautomated extraction and tabulation of resultsseveral optimization strategies aimed at findingoptimum options of toolsbest target clock frequencybest starting point of placementOR*

ECE 448 FPGA and ASIC Design with VHDL

*

batch mode of FPGA tools

ease of extraction and tabulation of resultsText Reports, Excel, CSV (Comma-Separated Values)optimized choice of tool optionsGMU_optimization_1 strategy Generation of Results Facilitated by ATHENavs.

*

Relative Improvement of Results from Using ATHENa Virtex 5, 256-bit Variants of Hash Functions Ratios of results obtained using ATHENa suggested optionsvs. default options of FPGA tools

*Other (Somewhat) Similar ToolsExploreAhead (part of PlanAhead)

Design Space Explorer (DSE)

Boldport Flow

EDAx10 Cloud Platform

ECE 448 FPGA and ASIC Design with VHDL

*Distinguishing Features of ATHENaSupport for multiple tools from multiple vendors

Optimization strategies aimed at the best possible performance rather than design closure

Extraction and presentation of results

Seamless integration with the ATHENa database of results

ECE 448 FPGA and ASIC Design with VHDL

Read the Tutorial!Install the Required Tools(see Tutorial - Part 1 Tools Installation)Run ATHENa_setupHow To Start Working With ATHENa?One-Time TasksDownload and unzip ATHENa http://cryptography.gmu.edu/athena/

ECE 448 FPGA and ASIC Design with VHDL

Modify design.config.txt+ possibly other configuration filesRun ATHENaHow To Start Working With ATHENa?Repetitive TasksPrepare or modify your source files& source_list.txt

ECE 448 FPGA and ASIC Design with VHDL

design.config.txtYour Design# directory containing synthesizable source files for the projectSOURCE_DIR =

# A file list containing list of files in the order suitable for synthesis and implementation# low level modules first, top level entity lastSOURCE_LIST_FILE = source_list.txt

# project name# it will be used in the names of result directoriesPROJECT_NAME = SHA256

# name of top level entityTOP_LEVEL_ENTITY = sha256

# name of top level architectureTOP_LEVEL_ARCH = rs_arch

# name of clock netCLOCK_NET = clk

ECE 448 FPGA and ASIC Design with VHDL

design.config.txtTiming Formulas#formula for latencyLATENCY = TCLK*65

#formula for throughputTHROUGHPUT = 512/(TCLK*65)

ECE 448 FPGA and ASIC Design with VHDL

design.config.txtApplication & Optimization Target# OPTIMIZATION_TARGET = speed | area | balancedOPTIMIZATION_TARGET = speed

# OPTIONS = default | userOPTIONS = default

# APPLICATION = single_run | exhaustive_search | placement_search | frequency_search |# GMU_Optimization_1 | GMU_Xilinx_optimization_1APPLICATION = single_run

# TRIM_MODE = off | zip | deleteTRIM_MODE = zip

ECE 448 FPGA and ASIC Design with VHDL

design.config.txtFPGA Families# commenting the next line removes all families of XilinxFPGA_VENDOR = xilinx

#commenting the next line removes a given familyFPGA_FAMILY = spartan3# FPGA_DEVICES = | best_match | allFPGA_DEVICES = best_matchSYN_CONSTRAINT_FILE = defaultIMP_CONSTRAINT_FILE = defaultREQ_SYN_FREQ = 120REQ_IMP_FREQ = 100MAX_SLICE_UTILIZATION = 0.8MAX_BRAM_UTILIZATION = 0.8MAX_MUL_UTILIZATION = 1MAX_PIN_UTILIZATION = 0.9END FAMILY

END VENDOR

ECE 448 FPGA and ASIC Design with VHDL

design.config.txtFPGA Families# commenting the next line removes all families of AlteraFPGA_VENDOR = altera

#commenting the next line removes a given familyFPGA_FAMILY = Stratix III# FPGA_DEVICES = | best_match | allFPGA_DEVICES = best_matchSYN_CONSTRAINT_FILE = defaultIMP_CONSTRAINT_FILE = defaultREQ_IMP_FREQ = 120MAX_LOGIC_UTILIZATION = 0.8MAX_MEMORY_UTILIZATION = 0.8MAX_DSP_UTILIZATION = 0MAX_MUL_UTILIZATION = 0MAX_PIN_UTILIZATION = 0.8END FAMILY

END VENDOR

ECE 448 FPGA and ASIC Design with VHDL

Library Filesdevice_lib/xilinx_device_lib.txtdevice_lib/altera_device_lib.txt

Files created during ATHENa setup

Characterize FPGA families and devices available in the version of Xilinx and Altera tools installed on your computer

Currently supported tool versions:Xilinx WebPACK 9.1, 9.2, 10.1, 11.1, 11.5, 12.1, 12.2, 12.3, 12.4, 13.1, 13.2, 13.3, 14.1, 14.2, 14.3Xilinx Design Suite11.1, 12.1, 12.2, 12.3, 12.4, 13.1, 13.2, 13.3, 14.1, 14.2, 14.3Altera Quartus II Web Edition8.1, 8.2, 9.0, 9.1, 10.0, 10.1, 11.0, 11.1, 12.0, 12.1Altera Quartus II Subscription Edition9.1, 10.0, 10.1, 11.0, 11.1, 12.0, 12.1

In case a library for a given version not available yet, use a library from the closest available version

ECE 448 FPGA and ASIC Design with VHDL

Library Filesdevice_lib/xilinx_device_lib.txt

VENDOR = Xilinx#Device, Total Slices, Block RAMs, DSP, Dedicated Multipliers, Maximum User I/O PinsITEM_ORDER = SLICE, BRAM, DSP, MULT, IOFAMILY = spartan3xc3s50pq208-5, 768,4, 0, 4, 124xc3s200ft256-5, 1920, 12, 0, 12, 173xc3s400fg456-5, 3584, 16, 0, 16, 264xc3s1000fg676-5, 7680, 24, 0, 24, 391xc3s1500fg676-5, 13312, 32, 0, 32, 487END_FAMILY

FAMILY = virtex5xc5vlx30ff676-3, 4800, 32, 32, 0, 400xc5vfx30tff665-3, 5120, 68, 64, 0, 360xc5vlx30tff665-3, 4800, 36, 32, 0, 360xc5vlx50ff1153-3, 7200, 48, 48, 0, 560xc5vlx50tff1136-3, 7200, 60, 48, 0, 480END_FAMILY

ECE 448 FPGA and ASIC Design with VHDL

Result Filesreport_resource_utilization.txt

xilinx : spartan3 +---------+-----------------+-----+------+---+--------+---+-------+----+-------+----+------+---+----+----+| GENERIC | DEVICE | RUN | LUTs | % | SLICES | % | BRAMs | % | MULTs | % | DSPs | % | IO | % |+---------+-----------------+-----+------+---+--------+---+-------+----+-------+----+------+---+----+----+| default | xc3s200ft256-5* | 1 | 142 | 3 | 74 | 3 | 4 | 33 | 7 | 58 | 0 | 0 | 20 | 11 |+---------+-----------------+-----+------+---+--------+---+-------+----+-------+----+------+---+----+----+

xilinx : spartan6 +---------+------------------+-----+------+---+--------+---+-------+---+-------+---+------+----+----+----+| GENERIC | DEVICE | RUN | LUTs | % | SLICES | % | BRAMs | % | MULTs | % | DSPs | % | IO | % |+---------+------------------+-----+------+---+--------+---+-------+---+-------+---+------+----+----+----+| default | xc6slx9csg324-3* | 1 | 41 | 1 | 22 | 1 | 4 | 6 | 0 | 0 | 9 | 56 | 20 | 10 |+---------+------------------+-----+------+---+--------+---+-------+---+-------+---+------+----+----+----+

xilinx : virtex5 +---------+-------------------+-----+------+---+--------+---+-------+----+-------+---+------+----+----+----+| GENERIC | DEVICE | RUN | LUTs | % | SLICES | % | BRAMs | % | MULTs | % | DSPs | % | IO | % |+---------+-------------------+-----+------+---+--------+---+-------+----+-------+---+------+----+----+----+| default | xc5vlx20tff323-2* | 1 | 101 | 1 | 56 | 1 | 4 | 15 | 0 | 0 | 9 | 37 | 20 | 11 |+---------+-------------------+-----+------+---+--------+---+-------+----+-------+---+------+----+----+----+

xilinx : virtex6 +---------+-------------------+-----+------+---+--------+---+-------+---+-------+---+------+---+----+---+| GENERIC | DEVICE | RUN | LUTs | % | SLICES | % | BRAMs | % | MULTs | % | DSPs | % | IO | % |+---------+-------------------+-----+------+---+--------+---+-------+---+-------+---+------+---+----+---+| default | xc6vlx75tff784-3* | 1 | 44 | 1 | 21 | 1 | 4 | 1 | 0 | 0 | 9 | 3 | 20 | 5 |+---------+-------------------+-----+------+---+--------+---+-------+---+-------+---+------+---+----+---+

ECE 448 FPGA and ASIC Design with VHDL

Result Filesreport_timing.txt

REQ SYN FREQ- Requested synthesis clk freq.SYN FREQ Achieved synthesis clk. freq.REQ SYN TCLK- Requested synthesis clk periodSYN TCLK Achieved synthesis clk. periodREQ IMP FREQ- Requested implement. clk freq.IMP FREQ Achieved implement. clk. freq.REQ IMP TCLK- Requested implement. clk periodIMP TCLK Achieved implement clk. periodLATENCY- Latency [ns]THROUGHPUT Throughput [Mbits/s]TP/Area - Throughput/Area [(Mbits/s)/CLB slicesLatency*Area Latency*Area [ns*CLB slices]

xilinx : spartan3 +---------+-----------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+| GENERIC | DEVICE | RUN | REQ SYN FREQ | SYN FREQ | REQ SYN TCLK | SYN TCLK | REQ IMP FREQ | IMP FREQ | REQ IMP TCLK | IMP TCLK | LATENCY | THROUGHPUT | TP/Area | Latency*Area |+---------+-----------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+| default | xc3s200ft256-5* | 1 | default | 207.370 | default | 4.822 | default | 112.448 | default | 8.893 | 17.786 | 449.792 | 6.078 | 1316.164 |+---------+-----------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+

xilinx : spartan6 +---------+------------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+| GENERIC | DEVICE | RUN | REQ SYN FREQ | SYN FREQ | REQ SYN TCLK | SYN TCLK | REQ IMP FREQ | IMP FREQ | REQ IMP TCLK | IMP TCLK | LATENCY | THROUGHPUT | TP/Area | Latency*Area |+---------+------------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+| default | xc6slx9csg324-3* | 1 | default | 75.751 | default | 13.201 | default | 78.119 | default | 12.801 | 25.602 | 312.476 | 14.203 | 563.244 |+---------+------------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+

xilinx : virtex5 +---------+-------------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+| GENERIC | DEVICE | RUN | REQ SYN FREQ | SYN FREQ | REQ SYN TCLK | SYN TCLK | REQ IMP FREQ | IMP FREQ | REQ IMP TCLK | IMP TCLK | LATENCY | THROUGHPUT | TP/Area | Latency*Area |+---------+-------------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+| default | xc5vlx20tff323-2* | 1 | default | 156.347 | default | 6.396 | default | 126.952 | default | 7.877 | 15.754 | 507.808 | 9.068 | 882.224 |+---------+-------------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+

xilinx : virtex6 +---------+-------------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+| GENERIC | DEVICE | RUN | REQ SYN FREQ | SYN FREQ | REQ SYN TCLK | SYN TCLK | REQ IMP FREQ | IMP FREQ | REQ IMP TCLK | IMP TCLK | LATENCY | THROUGHPUT | TP/Area | Latency*Area |+---------+-------------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+| default | xc6vlx75tff784-3* | 1 | default | 158.053 | default | 6.327 | default | 135.410 | default | 7.385 | 14.770 | 541.638 | 25.792 | 310.170 |+---------+-------------------+-----+--------------+----------+--------------+----------+--------------+----------+--------------+----------+---------+------------+------------+--------------+

ECE 448 FPGA and ASIC Design with VHDL

Result Filesreport_options.txt

xilinx : spartan3 +---------+-----------------+-----+------------+------------------------------+-------------------------+--------------+| GENERIC | DEVICE | RUN | COST TABLE | Synthesis Options | Map Options | PAR Options |+---------+-----------------+-----+------------+------------------------------+-------------------------+--------------+| default | xc3s200ft256-5* | 1 | 1 | -opt_level 1 -opt_mode speed | -c 100 -pr b -cm speed | -w -ol std |+---------+-----------------+-----+------------+------------------------------+-------------------------+--------------+

xilinx : spartan6 +---------+------------------+-----+------------+------------------------------+---------------+--------------+| GENERIC | DEVICE | RUN | COST TABLE | Synthesis Options | Map Options | PAR Options |+---------+------------------+-----+------------+------------------------------+---------------+--------------+| default | xc6slx9csg324-3* | 1 | 1 | -opt_level 1 -opt_mode speed | -c 100 -pr b | -w -ol std |+---------+------------------+-----+------------+------------------------------+---------------+--------------+

xilinx : virtex5 +---------+-------------------+-----+------------+------------------------------+-------------------------+--------------+| GENERIC | DEVICE | RUN | COST TABLE | Synthesis Options | Map Options | PAR Options |+---------+-------------------+-----+------------+------------------------------+-------------------------+--------------+| default | xc5vlx20tff323-2* | 1 | 1 | -opt_level 1 -opt_mode speed | -c 100 -pr b -cm speed | -w -ol std |+---------+-------------------+-----+------------+------------------------------+-------------------------+--------------+

xilinx : virtex6 +---------+-------------------+-----+------------+------------------------------+---------------+--------------+| GENERIC | DEVICE | RUN | COST TABLE | Synthesis Options | Map Options | PAR Options |+---------+-------------------+-----+------------+------------------------------+---------------+--------------+| default | xc6vlx75tff784-3* | 1 | 1 | -opt_level 1 -opt_mode speed | -c 100 -pr b | -w -ol std |+---------+-------------------+-----+------------+------------------------------+---------------+--------------+COST TABLE - parameter determining the starting point of placementSynthesis Options options of the synthesis toolMap Options Options of the mapping toolPAR Options Options of the place & route tool

ECE 448 FPGA and ASIC Design with VHDL

Result Filesreport_execution_time.txt

xilinx : spartan3 +---------+-----------------+-----+----------------+---------------------+--------------+| GENERIC | DEVICE | RUN | Synthesis Time | Implementation Time | Elapsed Time |+---------+-----------------+-----+----------------+---------------------+--------------+| default | xc3s200ft256-5* | 1 | 0d 0h:0m:12s | 0d 0h:0m:36s | 0d 0h:0m:48s |+---------+-----------------+-----+----------------+---------------------+--------------+

xilinx : spartan6 +---------+------------------+-----+----------------+---------------------+--------------+| GENERIC | DEVICE | RUN | Synthesis Time | Implementation Time | Elapsed Time |+---------+------------------+-----+----------------+---------------------+--------------+| default | xc6slx9csg324-3* | 1 | 0d 0h:0m:21s | 0d 0h:1m:13s | 0d 0h:1m:34s |+---------+------------------+-----+----------------+---------------------+--------------+

xilinx : virtex5 +---------+-------------------+-----+----------------+---------------------+--------------+| GENERIC | DEVICE | RUN | Synthesis Time | Implementation Time | Elapsed Time |+---------+-------------------+-----+----------------+---------------------+--------------+| default | xc5vlx20tff323-2* | 1 | 0d 0h:0m:39s | 0d 0h:1m:50s | 0d 0h:2m:29s |+---------+-------------------+-----+----------------+---------------------+--------------+

xilinx : virtex6 +---------+-------------------+-----+----------------+---------------------+--------------+| GENERIC | DEVICE | RUN | Synthesis Time | Implementation Time | Elapsed Time |+---------+-------------------+-----+----------------+---------------------+--------------+| default | xc6vlx75tff784-3* | 1 | 0d 0h:0m:22s | 0d 0h:3m:22s | 0d 0h:3m:44s |+---------+-------------------+-----+----------------+---------------------+--------------+Synthesis Time- Time of SynthesisImplementation Time- Time of ImplementationElapsed Time - Total Time

ECE 448 FPGA and ASIC Design with VHDL

design.config.txtFunctional Simulation (1)# FUNCTIONAL_VERFICATION_MODE = FUNCTIONAL_VERIFICATION_MODE =

# directory containing source files of the testbenchVERIFICATION_DIR =

# A file containing a list of testbench files in the order suitable for compilation;# low level modules first, top level entity last.# Test vector files should be located in the same directory and listed# in the same file, unless fixed path is used. Please refer to tutorial for more detail.VERIFICATION_LIST_FILE =

# name of testbench's top level entityTB_TOP_LEVEL_ENTITY =

# name of testbench's top level architectureTB_TOP_LEVEL_ARCH =

ECE 448 FPGA and ASIC Design with VHDL

design.config.txtFunctional Simulation (2)# MAX_TIME_FUNCTIONAL_VERIFICATION = #supported unit are : ps, ns, us, and ms#if blank, simulation will run until it finishes = # = no changes in signals, i.e., clock is stopped and no more inputs coming in.MAX_TIME_FUNCTIONAL_VERIFICATION =

# Perform only verification (synthesis and implementation parameters are ignored)# VERIFICATION_ONLY = VERIFICATION_ONLY =

ECE 448 FPGA and ASIC Design with VHDL

*ATHENa Databaseof Results

ECE 448 FPGA and ASIC Design with VHDL

*ATHENa Databasehttp://cryptography.gmu.edu/athenadb

ECE 448 FPGA and ASIC Design with VHDL

*ATHENa Database Result ViewAlgorithm parametersDesign parametersOptimization targetArchitecture typeDatapath widthI/O bus widthsAvailability of source codePlatformVendor, Family, DeviceTimingMaximum clock frequencyMaximum throughputResource utilizationLogic blocks (Slices/LEs/ALUTs)Multipliers/DSP unitsToolsNames & versionsDetailed optionsCreditsDesigners & contact information

ECE 448 FPGA and ASIC Design with VHDL

*ATHENa Database Compare FeatureMatching fields in greyNon-matching fields in red and blue

ECE 448 FPGA and ASIC Design with VHDL

*Possible Future CustomizationsThe same basic database can be customizedand adapted for other domains, such asDigital Signal ProcessingBioinformaticsCommunicationsScientific Computing, etc.

ECE 448 FPGA and ASIC Design with VHDL

*ATHENa - Website

ECE 448 FPGA and ASIC Design with VHDL

*ATHENa Websitehttp://cryptography.gmu.edu/athena/Download of ATHENa ToolLinks to related toolsSHA-3 Competition in FPGAs & ASICsSpecifications of candidatesInterface proposalsRTL source codesTestbenchesATHENa database of resultsRelated papers & presentations

ECE 448 FPGA and ASIC Design with VHDL

*

GMU Source Codes for all Round 3 SHA-3 Candidates & SHA-2 made available at the ATHENa website at: http://cryprography.gmu.edu/athena

Included in this release:Basic architecturesFolded architecturesUnrolled architecturesEach code supports two variants: with 256-bit and 512-bit output.Each source code accompanied by comprehensive hierarchical block diagrams

GMU Source Codes and Block Diagrams

*ATHENa Result Replication FilesScripts and configuration files sufficient to easily reproduce all results (without repeating optimizations)Automatically created by ATHENa for all results generated using ATHENaStored in the ATHENa DatabaseIn the same spirit of Reproducible Research as:Patrick Vandewalle1, Jelena Kovacevic2, and Martin Vetterli1 (1EPFL, 2CMU) Reproducible research in signal processing - what, why, and how. IEEE Signal Processing Magazine, May 2009. http://rr.epfl.ch/17/J. Claerbout (Stanford University)Electronic documents give reproducible research a new meaning, in Proc. 62nd Ann. Int. Meeting of the Soc. of Exploration Geophysics, 1992, http://sepwww.stanford.edu/doku.php?id=sep:research:reproducible:seg92

. . . . .

ECE 448 FPGA and ASIC Design with VHDL

*Benchmarking Goals Facilitated by ATHENacryptographic algorithms hardware architectures or implementations of the same cryptographic algorithmhardware platforms from the point of view of their suitability for the implementation of a given algorithm, (e.g., choice of an FPGA device or FPGA board)tools and languages in terms of quality of results they generate (e.g. Verilog vs. VHDL, Synplicity Synplify Premier vs. Xilinx XST, ISE v. 13.1 vs. ISE v. 12.3)

Comparing multiple:

ECE 448 FPGA and ASIC Design with VHDL

George Mason University

Modern FPGA Families

ECE 448 FPGA and ASIC Design with VHDL

*

ECE 448 FPGA and ASIC Design with VHDLMajor FPGA VendorsSRAM-based FPGAsXilinx, Inc.Altera Corp.Lattice SemiconductorAtmelAchronixTabulaFlash & antifuse FPGAsActel Corp. (Microsemi SoC Products Group)Quick Logic Corp.~ 51% of the market~ 34% of the market~ 85%

ECE 448 FPGA and ASIC Design with VHDL

Xilinx FPGA Devices

TechnologyLow-costHigh-performance220 nmSpartan IIVirtex120/150 nmVirtex II, II Pro90 nmSpartan 3Virtex 465 nmVirtex 545 nmSpartan 640 nmVirtex 628 nmArtix 7Virtex 7

ECE 448 FPGA and ASIC Design with VHDL

Altera FPGA Devices

TechnologyLow-costMid-rangeHigh-performance130 nmCycloneStratix90 nmCyclone IIStratix II65 nmCyclone IIIArria IStratix III40 nmCyclone IVArria IIStratix IV28 nmCyclone VArria VStratix V

ECE 448 FPGA and ASIC Design with VHDL

*

ResourcesXcell Journalavailable for FREE on line @http://www.xilinx.com/about/xcell-publications/xcell-journal.html

Electronic Engineering Journalavailable for FREE by e-mail after subscribing @ http://www.eejournal.com/subscribe or on the web @ http://www.eejournal.com/design/fpga

George Mason University

Follow-up Courses

ECE 448 FPGA and ASIC Design with VHDL

ECE DepartmentMS in Electrical EngineeringMS EEMS in Computer EngineeringMS CpECOMMUNICATIONS& NETWORKINGSIGNAL PROCESSINGCONTROL & ROBOTICSMICROELECTRONICS/NANOELECTRONICSSYSTEM DESIGNDIGITAL SYSTEMS DESIGNCOMPUTER NETWORKSMICROPROCESSORS& EMBEDDED SYSTEMSNETWORK & SYSTEMSECURITYProgramsSpecializationsBIOENGINEERINGDIGITAL SIGNAL PROCESSING

ECE 448 FPGA and ASIC Design with VHDL

DIGITAL SYSTEMS DESIGN

ECE 545 Digital System Design with VHDL (Fall) K. Gaj, project, FPGA design with VHDL, Aldec/Synplicity/Xilinx/Altera 2. ECE 645 Computer Arithmetic (Spring) K. Gaj, project, FPGA design with VHDL or Verilog, Aldec/Synplicity/Xilinx/Altera

3. ECE 586 Digital Integrated Circuits (Spring) D. Ioannou

4. ECE 681 VLSI Design for ASICs (Fall) H. Homayoun, project/lab, front-end and back-end ASIC design with Synopsys tools 5. ECE 682 VLSI Test Concepts (Spring) T. Storey, homework

6. ECE 699 Digital Signal Processing Hardware Architectures (Spring) A. Cohen, project, FPGA design with VHDL or Verilog

ECE 448 FPGA and ASIC Design with VHDL

DIGITAL SIGNAL PROCESSING

Concentration advisors: Aaron Cohen, Kris Gaj, Ken Hintz, Jill Nelson, Kathleen Wage

ECE 535 Digital Signal Processing L. Griffiths, J. Nelson, Matlab

ECE 545 Digital System Design with VHDL K. Gaj, project, FPGA design with VHDL

ECE 645 Computer Arithmetic K. Gaj, project, FPGA design with VHDL

ECE 699 Digital Signals Processing Hardware Architectures A. Cohen, project, FPGA design with VHDL and Matlab/Simulink

5a. ECE 537 Introduction to Digital Image Processing K. Hintz5b. ECE 738 Advanced Digital Signal Processing K. Wage

ECE 448 FPGA and ASIC Design with VHDL

Possible New Graduate Computer Engineering Courses

5xx Digital System Design with Verilog6xx Reconfigurable Computing (looking for instructors)

ECE 448 FPGA and ASIC Design with VHDL

NETWORK AND SYSTEM SECURITY

ECE 542 Computer Network Architectures and Protocols (Fall, Spring) S.-C. Chang, et al.

ECE 646 Cryptography and Computer Network Security (Fall) K. Gaj, J-P. Kaps lab, project: software/hardware/analytical

ECE 746 Advanced Applied Cryptography (every 2nd Spring, 2015) K. Gaj, J-P. Kaps lab, project: software/hardware/analytical

ECE 699 Cryptographic Engineering (every 2nd Spring, 2014) J-P. Kaps lectures + student/invited guests seminars

ISA 656 Network Security (Fall, Spring) A. Stavrou

ECE 448 FPGA and ASIC Design with VHDL

ECE 645Computer ArithmeticInstructor: Dr. Kris Gaj

ECE 448 FPGA and ASIC Design with VHDL

Advanced digital circuit design course covering addition and subtraction multiplication division and modular reduction exponentiationEfficient architectures for Integersunsigned and signedReal numbers fixed point single and double precision floating pointElementsof the Galoisfield GF(2n) polynomial base

ECE 448 FPGA and ASIC Design with VHDL

At the end of this course you should be able to: Understand mathematical and gate-level algorithms for computer addition, subtraction, multiplication, division, and exponentiation Understand tradeoffs involved with different arithmetic architectures between performance, area, latency, scalability, etc. Synthesize and implement computer arithmetic blocks on FPGAs Be comfortable with different number systems, and have familiarity with floating-point and Galois field arithmetic for future study Understand sources of error in computer arithmetic and basics of error analysis

This knowledge will come about through homework, project and practice exams.

Course Objectives

ECE 448 FPGA and ASIC Design with VHDL

1. Applications of computer arithmetic algorithms. Initial Discussion of Project Topics.INTRODUCTIONLecture topics

ECE 448 FPGA and ASIC Design with VHDL

Basic addition, subtraction, and counting

Addition in Xilinx and Altera FPGAs

3. Carry-lookahead, carry-select, and hybrid adders

4. Adders based on Parallel Prefix Networks

Pipelined Adders Modular addition and subtraction

ADDITION AND SUBTRACTION

ECE 448 FPGA and ASIC Design with VHDL

MULTIOPERAND ADDITION1. Carry-save adders

2. Wallace and Dadda Trees

3. Adding multiple unsigned and signed numbers

ECE 448 FPGA and ASIC Design with VHDL

Unsigned Integers Signed Integers Fixed-point real numbers Floating-point real numbers Elements of the Galois Field GF(2n)NUMBER REPRESENTATIONS

ECE 448 FPGA and ASIC Design with VHDL

LONG INTEGER ARITHMETICModular Exponentiation

Montgomery Multipliers and Exponentiation Units

ECE 448 FPGA and ASIC Design with VHDL

MULTIPLICATION1. Tree and array multipliers

2. Sequential multipliers

3. Multiplication of signed numbers and squaring

4. Multiplication in Xilinx and Altera FPGAs - using distributed logic - using embedded multipliers - using DSP blocks

5. Multiple clock systems

ECE 448 FPGA and ASIC Design with VHDL

DIVISIONBasic restoring and non-restoring sequential dividers

2. SRT and high-radix dividers

3. Array dividers

4. Division by Convergence

ECE 448 FPGA and ASIC Design with VHDL

FLOATING POINT AND GALOIS FIELD ARITHMETICFloating-point units

2. Galois Field GF(2n) units

ECE 448 FPGA and ASIC Design with VHDL

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