measurement and analysis of weather phenomena progress in
TRANSCRIPT
Measurement and Analysis of Weather Phenomena with K-Band Rain Radar
Jun-Hyeong Park Dept. of Electrical Engineering
KAIST DaeJeon, Republic of Korea
Ki-Bok Kong Development team Kukdong Telecom
Nonsan, Republic of Korea [email protected]
Seong-Ook Park Dept. of Electrical Engineering
KAIST DaeJeon, Republic of Korea
Abstract—To overcome blind spots of an ordinary weather radar which scans horizontally at a high altitude, a weather radar which operates vertically, so called an atmospheric profiler, is needed. In this paper, a K-band radar for observing rainfall vertically is introduced, and measurement results of rainfall are shown and discussed. For better performance of the atmospheric profiler, the radar which has high resolution even with low transmitted power is designed. With this radar, a melting layer is detected and some results that show characteristics of the meting layer are measured well.
Keywords—K-band; FMCW; rain radar; low transmitted power; high resolution; rainfall; melting layer
I. INTRODUCTION A weather radar usually measures meteorological
conditions of over a wide area at a high altitude. Because it observes weather phenomena in the area, it is mainly used for weather forecasting. However, blind spots exist because an ordinary weather radar scans horizontally, which results in difficulties in obtaining information on rainfall at higher and lower altitudes than the specific altitude. Therefore, a weather radar that covers the blind spots is required.
A weather radar that scans vertically could solve the problem. This kind of weather radar, so called an atmospheric profiler, points towards the sky and observes meteorological conditions according to the height [1]. Also, because the atmospheric profiler usually operates continuously at a fixed position, it could catch the sudden change of weather in the specific area.
In this paper, K-band rain radar which has low transmitted power and high resolutions of the range and the velocity is introduced. The frequency modulated continuous wave (FMCW) technique is used to achieve high sensitivity and reduce the cost of the system. In addition, meteorological results are discussed. Reflectivity, a fall speed of raindrops and Doppler spectrum measured when it rained are described, and characteristics of the melting layer are analyzed as well.
II. DEVELOPMENT OF K-BAND RAIN RADAR SYSTEM
A. Antenna To suppress side-lobe levels and increase an antenna gain,
offset dual reflector antennas are used [2]. Also, separation
wall exists between the transmitter (Tx) and receiver (Rx) antennas to improve isolation between them. With these methods, leakage power between Tx and Rx could be reduced. Fig. 1 shows manufactured antennas and the separation wall.
B. Design of Tranceiver Fig. 2 shows a block diagram of the K-band rain radar.
Reference signals for all PLLs in the system and clock signals for every digital chip in baseband are generated by four frequency synthesizers. In the Tx baseband module, a field programmable gate array (FPGA) controls a direct digital synthesizer (DDS) to generate an FMCW signal which decreases with time (down-chirp) and has a center frequency of 670 MHz. The sweep bandwidth is 50 MHz which gives the high range resolution of 3 m. Considering the cost, 2.4 GHz signal used as a reference clock input of the DDS is split and used for a local oscillator (LO). the FMCW signal is transmitted toward raindrops with the power of only 100 mW. Beat frequency which has data of the range and the radial velocity of raindrops is carried by 60 MHz and applied to the input of the Rx baseband module. In the Rx baseband module, quadrature demodulation is performed by a digital down converter (DDC). Thus, detectable range can be doubled than usual. Two Dimensional-Fast Fourier Transform (2D-FFT) is performed by two FPGAs. Because the 2D FFT is performed with 1024 beat signals, the radar can have high resolution of the radial velocity. Finally, data of raindrops are transferred to a PC with local LAN via the an UDP protocol. TABLE I. shows main specification of the system.
Fig. 1. Manufactured antenna and separation wall.
2016 URSI Asia-Pacific Radio Science Conference August 21-25, 2016 / Seoul, Korea
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Progress in SKA Central Signal Processing
John D Bunton,
CSIRO Astronomy and Space Science
Sydney, Australia
Abstract—The SKA phase 1 correlator, beamformers, and
pulsar processing systems will be the largest built for radio
astronomy. Just the raw correlation processing is close to 5 Tera
arithmetic operation per second, with beamforming and pulsar
search each being a similar order of magnitude.
The work on these is being undertaken by the Central Signal
Processing element of SKA and is broken up into a number of
different sub-element each with its own consortium doing the
development. All sub-elements have completed their Preliminary
Design Reviews and now are proceed to the Critical Design
Reviews (CDRs) which will take place next year. A greater
emphasis is now being put on Systems Engineering. At CDR all
requirements and interface definitions will be in place. These
together with a reference design will form the basis for tenders
for construction. Work on system availability, logistics,
operations, power estimates, cost estimates etc will feed into the
inter-government agreements need to finally build the instrument.
The hardware is a combination of GPU and FPGA processing.
The GPU systems will rely on continued progress in GPU
technology. Two correlators and beamformers are being designed
by two different consortia and both will have working next
generation FPGA hardware by the end of the year. This
hardware, in the first place, is meant to mitigate risk.
Unfortunately at this time it is highlighting a risk that has been
realized. This will necessitate redesigns. Work also continues on
modeling to verify the algorithms and software and firmware to
verify the validity of the design
Keywords—Introduction
Central Signal Processing (CSP) for the SKA [1] covers all of the backend processing except station beamforming for the Low Frequency Aperture Array. The scale of the task is an order of magnitude more than current systems such as the EVLA correlator while at the same time sacrificing nothing in the way of functionality (eg [2] which has the 2011 requirements), which unfortunately for the designer continues to grow.
CSP element comprises two separate correlator and beamformer systems together pulsar search and pulsar timing engines. One system, CSP.Mid, is for the 0.35 to 13.8 GHz dish array to be built in South Africa and the other, CSP Low, is for the 50 to 350 MHz low frequency telescope to be built in Australia. The receptors for Low are stations composed of 256 dual polarisation Log-periodic antennas that are beamformed in the Low Frequency Aperture Array (LFAA) element.
The CSP element is broken up into a set of sub-elements that actually implement the hardware system and is overseen
by the Canadian consortium. The sub-elements and main consortia members working on them are:
Low.CBF Low correlator and beamformer CSIRO (Aus.), ASTRON (Netherlands) and AUT (NZ)
Mid.CBF Mid correlator and beamformer, NRC and MDA (Canada) PSS Pulsar Search, The University of Manchester (UK) PST Pulsar Timing, Swinburne University (Aus.) LMC Local monitor and control, NRC (Canada) Over the life of CSP more than thirty organisation have contributed.
I. BASIC SPECIFICATION
The two correlator have a lot of similarity as can be seen from their basic specification.
Table 1 Basic correlator specifications MID LOW
Dishes/Stations 197 512
Processed bandwidth 0.7 GHz (band 1)
2 x 2.5 GHz (band 5)
0.35 GHz
Maximum baseline 150 km 80 km
Frequency Channels
(standard)
65 k 65 k
Full Stokes Correlator yes yes
Frequency Resolution (standard)
11 kHz (band 1) 76 kHz (band 5)
4.6 kHz
Number of zoom bands 4 4
Channels per zoom band 16 k 16 k
Zoom Frequency resolutions
250 Hz to 16 kHz 250 to 2 kHz
Subarrays 16 16
Correlation Processing
load
3.1 Peta arithmetic
ops/s
1.26 Peta arithmetic
ops/s
Output data rate 3.0 Tbps 3.1 Tbps
Compared to Mid is seen that Low is a high input count system with lower bandwidth. Functionally the main difference is Mid must handle data from 5 separate feed system with four different sample rate and pulsar binning. For Low each station can form beams in up to 8 different direction. The total bandwidth is shared between the beams. Multibeaming together with subarrays allows for up to 128 simultaneous look directions in Low.
For pulsar timing the data from the dish or stations is beamformed by Low and Mid CBF and the voltage data passed to the PST processing engines. In the PST processing engines the voltage data is coherently de-dispersed and then
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the signal power folded to determine the pulse profile and the timing of the pulse.
Table 2 Basic specifications for Pulsar Timing Mid Low
Number of beams 16 500
Bandwidth per beam 2.5 GHz 300 MHz
Impulse Response 200ns 2 s
In addition Mid forms 4 VLBI voltage beams
For pulsar search the CBF sub-element forms beams from a subset of the dishes or station that are close to the compact core. The beam data is converted to polarised power and sent to the PSS processing engine. Each beam is searched for pulsars over a range of dispersions and accelerations.
Table 3 Basic specifications for Pulsar Search Mid Low
Number of beams 1500 500
Bandwidth per beam 300 MHz 120 MHz
Number of dispersion
measures per beam
500 500
Acceleration Searches 0 to 350 ms-1 0 to 350 ms-1
As well detecting pulsar PSS detect single pulse events such as FRBs
II. HARDWARE
The pulsar search and timing systems are based on GPU enhanced servers with each server processing a number of beams. Appropriate code is well developed with work continuing on the algorithms. There is also a need to reduce power, cost and rack space. For example the pulsar search engine in Low occupies 14 racks and uses 157kW of power. The Mid pulsar search engine is approximately 3 times larger.
The correlator and beamformers for Mid and Low are both FPGA base. Mid is well advanced in developing their PowerMX hardware platform [3]. Its basis is the Heron motherboard which has space for 4 FPGA Mezzanine boards. Power supplies are on the mother board and can provide up to 288A of current to each FPGA. The motherboard also provides 8 sockets per FPGA for off board electrical or optical high speed connections.
Figure 1 Completed Heron board showing sites for four
mezzanine boards (Credit NRC Canada).
A number of FPGA mezzanine board designs are need for
the full system. The first to be built being the Altera Arria 10 P32S-A10 board, with a Stratix 10 board expected latter this
year. The mezzanine boards contain only the FPGA and memory either HMC, for speed, or DRAM, for memory depth.
Compared to the Mid team, who have been progressing their design for three years, the current Low team has been together for just one. Even so in July the first prototype FPGA board, Gemini, went out for manufacture.
Figure 2 Gemini Board routing layout. The board in now
out for production. It has four A VU9P FPGA centre, 4
HMC, 3 24-fibre ribbon optical I/O and 4 QSFP+ sockets.
(Credit A Brown, G Schoonderbeek)
The prototype will use a Virtex Ultrascale+ VU9P FPGA.
The Gemini concept is a standalone single FPGA board that include all memory, I/O, power supplies and command and control interfaces. All Low CSP processing will take place on the final version of the Gemini board. The Gemini board is water cooled and four are mounted in a standard 1U chassis, other mounting options are being explored
III. A RISK REALISED AND THE SOLUTION
The main task of the first Gemini board is to remove or reduce risks and unfortunately one risk was quickly realised: the HMC memory used in the design went end of life. This has necessitated a complete redesign. But as many major decisions have been taken, after appropriate analysis and documentation, this will be much faster.
The first major function implemented on the input data is a set of filterbank together with delay and fringe stopping. In the original design a separate system was dedicated to these functions. The input data rate was 135Gbps comprising 384 frequency channels (781 kHz) from 12 dual polarisation stations. The filterbanks could not process all 9,216 channels at once so the data must be stored to external memory. Only HMC memory has R/W data rate sufficient to meet this. But the available parts now have insufficient memory depth.
A solution to the problem is to amalgamate the filterbank and correlator functions into a single FPGA. In the original system there were many more correlator FPGAs than filterbanks. The input data rate is reduced by spreading the input data over many more FPGAs. Doing this reduces the input data rate per FPGA to 45Gbps. The total memory I/O read and write is 95Gbps. DRR4 memory how has sufficient
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bandwidth to handle the data rate. In the next version of Gemini much of the HMC will be converted to DDR4. The change in the distribution of functions to FPGAs now allows DRR4 to handle all external memory accesses prior to correlation and beamforming
IV. SYSTEMS ENGINEERINGS AND MODELLING
In parallel with hardware and architecture developments is the work on systems engineering and modelling. Radio telescopes are increasingly the work of many contributors so that there be no misunderstanding a rigorous set of requirements and interface definitions is required. The system requirement are now at revision 8 and the vast majority have now flowed down through the elements to sub-element such as the Low Correlator and Beamformer. Draft interface definitions are in place and the last of these will be signed off in the coming months. This information will be the basis the tenders for the building of the SKA1. Work is starting on Reliability, Failure modes, Effects, Criticality of Faults, and Integrated Logistics. The outputs from this work is an estimate of system availability and together with power usage estimates the cost of and effort needed to run the telescope.
The final piece of the puzzle is modelling. Pulsar Search and timing can implement their algorithms, for a single beam, on existing hardware. The correlator and beamformers in CSP require next generation FPGAs to fully realise the some functions. For example in Low the target FPGA, available next year, will form all one half million visibilities for a single frequency channel at a single time. So currently only part functionality can be modelled. But in the meantime an important question is do the algorithms meet SKA requirements such as a maximum correlator loss (2%), uniformity of response to spectral lines, and pulsar data impulse response.
This is tackled by building “golden” models of the algorithms. These are floating point implementations of the algorithms and they are now in place for both Mid and Low correlator and beamformer. Sinusoids are used as test inputs.
The phase of the sinusoid is varied to model the varying delay between antennas. A single sinusoid can probe the transfer function of the system, and a set of closely spaced sinusoids model broadband noise and allow correlator efficiency measurements. Results from both Mid and Low confirm the validity of the algorithms. The next step is to model the quantisation of data as it flows through the system. This will measure the quantisation losses and will test for non-linearities.
V. CONCLUSION
All sub-elements of CSP are on track to deliver all inputs required for a critical design review next year. This is the culmination of the preconstruction phase of SKA1. The document set will comprise a reference design, a detailed design document, requirements, interface definitions, estimates of cost, power, availability and models to validate the design. Prototyping work in preconstruction will aim to mitigate all major risks.
This documentation will feed into the tender process, which starts at the end of 2017, as well as the inter-government agreements that will control and fund the instrument. Construction will start a year later.
References
[1] CSP on the SKA website https://www.skatelescope.org/csp/
[2] W. Turner, “SKA PHASE 1 SYSTEM (LEVEL 1) REQUIREMENTS SPECIFICATION”, http://www.academia.edu/download/42601433/SKA-TEL-SKO-0000008-AG-REQ-SRS-Rev05-SKA1_Level_1_System_Requirement_Specification-signed.pdf
[3] LBG Knee, “Current Developments in the NRC Correlator Program”, ALMA developers workshop, Chalmers University, 26 May 2016, https://www.chalmers.se/en/centres/GoCAS/Events/ALMA-Developers-Workshop/Documents/Knee%20-%20Current%20developments%20in%20the%20NRC%20correlator%20program.pdf
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