mdsv lesson plan 2015 revised

7/23/2019 MDSV Lesson Plan 2015 Revised

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Dept. of Electronics & Communication Engineering NMAMIT, Nitte

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Course Plan

Semester: 1st Semester, M.Tech, VLSI Design and Embedded sstems

Course Title:

Modeling o! Digital

Sstems using V"DL

Course Code:

1#VDE111

Total Contact Hours: 5 Duration of !EE: "# $ours

!EE Mar%s: 5" CIE Mar%s: 5"

esson 'lan Aut$or: Mr. 'rad(umna ).*. Date: +-"-"+5

C$ec%ed (: Mr. 'rad(umna ).*. Date: +-"-"+5

Prere$uisites

+. Digital Electronics.

. Ver "igh S%eed Integrated Circuit "ard&are Descri%ti'e Language

Course Learning (b)ecti'es *CL(+:

After stud(ing t$is Course, t$e student s$ould /e a/le to:

+ )et an insig$t to t$e !undamentals o! digital logic using 0er( Hig$!peed Integrated Circuit Hard1are Descripti2e anguage 30HD4.

or% on 2arious programs starting 1it$ design of /asic gates to design of

se$uential circuits as 1ell as combinational logic circuits using 0HD.

# Design net1or%s in2ol2ing arithmetic o%erations using 0HD language.

6 Anal(7e and design standard combinational modules.

5 )et an insig$t to t$e specification, organi7ation and Im%lementation o!

TL s(stems.

8 9nderstand data and control subsstems and design it.

Anal(7e t$e specifications and im%lement a microcom%uter s(stem.

; earn to design a TL s(stem for t$e specifications mentioned.




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Course Content

Course Code: 1#VDE111 L-T-P: -/-/

Course Title: M(DELI0 (2 DIIT3L S4STEMS 5SI0 V"DL CIE: #/Teaching "ours: #6"rs SEE: #/

50IT- I

I0SIDE V"DL: Introduction to 0HD, !pecification of com/inational s(stems using 0HD,

asic language element of 0HD, 0HD description of gates, e$a2ioral Modeling, Data flo1

modeling, structural modeling, !u/programs 1/ "rs

50IT -II

DESI0 (2 0ET7(8S 2( 3IT"METIC (PE3TI(0S: Design of a !erial Adder 1it$ Accumulator, !tate )rap$ for Control Net1or%, Design of a inar( Multiplier,

Multiplication of a !igned inar( Num/er, and Design of a inar( Di2ider 1it$ 0HD

Codes . /9 "rs

50IT-III

ST30D3D C(MI03TI(03L M(D5LES: inar( decoder, inar( encoder, multiple<ers

and de-multiple<ers, s$ifters.

EISTE-T30S2E LEVEL S4STEMS: E<ecution )rap$, =rgani7ation of !(stem,

Implementation of *T !(stems, Anal(sis of *T !(stems, and Design of *T!(stems. 16 "rs

50IT-IV

D3T3 30D C(0T(L S5S4STEM: Data !u/s(stems, !torage Modules, >unctional

Modules, Data pat$s, Control !u/s(stems, Micro programmed Controller, !tructure of a micro

programmed controller, Micro instruction >ormat, Micro instruction se?uencing, Micro

instruction timing 1/ "rs

50IT-V

!'ECI>ICATI=N AND IM'EMENTATI=N => A MIC*=C=M'9TE*: asic component of

a micro s(stem, memor( su/s(stem, I@= su/s(stem, 'rocessors, =peration of t$e computer and

c(cle time. 16 "rs

Te;t oo<s:




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T+. M. Ercego2ac, T. ang and .. Moreno, =Introduction to Digital Sstems>, ile(, """

T. C. H. *ot$, BDigital Sstem Design using V"DL, T$omson earning, ""+

T#. . $as%ar, B3 V"DL Primer, Addison esle(, +

e!erence oo<s:

*+. o$n.>.a%erl(, =Digital Design-Princi%les and Practices>, 'HI, #rd Edition updated,

""5

*. Douglas 'err(, BV"DL: Programming b E;am%le, TMH, ""

*#. Mic$ae o$n !e/astian !mit$, B3%%lication-S%eci!ic Integrated Circuits, Addison-

esle(, +

E'aluation Scheme

CIE Scheme

Assessment Weightage in Marks

Mid !emester E<am + "

Mid !emester E<am "

Tas% +: !imulation using 0HD "5

Tas% : Implementation on >')A using

0HD3Mini 'roect4

"5

Total 5"

!emester End E<amination 3!EE4 is a 1ritten e<amination, of t$ree $ours duration of

+"" mar%s, 1it$ 5" 1eig$tage.

e read &ith la%to% &ith ?ilin; installed in it.

Sometimes ou ma ha'e to sho& the out%ut.

Course 5tili@ation !or Mid Semester E;ams and Semester End E;amination




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9nit C$apter Teac$ing

Hours

No. of Fuestions in

No. of

Fuestionsin !EE

Mid

!emester E<am +

Mid

!emester E<am

I + Inside 0HD +"

"6

--

II

Design of net1or%s

for arit$metic

operations

";

III#

!tandard

com/inational

modules

*egister-transfer

le2el s(stems

+

--

-- "6

I0 6Data and control

su/s(stem+"

0 8

!pecification and

implementation of a

microcomputer

+ -- --

0ote:

• Eac$ ?uestion carries " mar%s and ma( consist of su/-?uestions.

• Mi<ing of su/-?uestions from different c$apters 1it$in a unit is allo1ed in Mid !emester

E<am I, II and !EE.

•Ans1er 5 full ?uestions of " mar%s eac$ /( selecting one ?uestion from eac$ unit out of +" in !EE.

50IT A I




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Cha%ter 7ise Plan

!u/ect Code: 1#VDE111 Course Title: Modeling o! Digital Sstems

using V"DL

C$apter Num/er: "+ C$apter Title: Inside V"DL

'lanned Hours: +"

Cha%ter Learning (b)ecti'es:

After stud(ing t$is c$apter, t$e student s$ould /e a/le to:

+. Gno1 t$e /asics of 0er( Hig$ !peed Integrated Circuit Hard1are Descripti2e

anguage 30HD4+,,#

. rite t$e coding in different st(les of modeling for an( e<ample gi2en.6

#. !ol2e digital com/inational circuits and also 1rite t$e 0HD code for t$e designed

circuits.5

6. !ol2e se?uential circuits and also 1rite t$e 0HD code for t$e designed circuits.85. Design >!M and 1rite t$e 0HD code for t$e designed circuit.

8. 9nderstand t$e concept of su/programs .;

. rite codes in 0HD for an( circuits as%ed to design.,+"

Lesson Schedule

Class No. Portion covered per hour

+. Introduction to 0HD

. 0arious language elements in 0HD and designing using t$ese concepts.

#. 0arious language elements in 0HD and designing using t$ese concepts.

6 *e2ie1 t$e /asic st(les of modeling in2ol2ed in 0HD5. Anal(sis of com/inational logic circuits 1it$ design concept.

8. Anal(sis of se?uential logic circuits 1it$ design concept.

. Designing finite state mac$ines.

;. !u/programs description for t$e gi2en pro/lem definitions.

. 0HD code to /e 1ritten for all t$e a/o2e mentioned topics

+". 0HD code to /e 1ritten for all t$e a/o2e mentioned topics

e'ie& Buestions:

+. E<plain t$e t$ree t(pes of AIT statements a2aila/le in 0HD also gi2e e<amples.




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. it$ an e<ample, e<plain /inding /et1een a li/rar( and a component ta%ing full

adder as an e<ample.

#. Design an >!M for a CD up counter.

6. rite a 0HD code for a full adder using procedures.5. Design a digital s(stem 1$ic$ ta%es serial dataJs as inputs and outputs a K+J

1$ene2er consecuti2e t$ree num/ers of ones appear. =2erlapping also s$ould /e

considered. rite t$e code for t$e same.

50IT-II




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!u/ect Code: 1#VDE111 Course Title: : Modeling o! Digital Sstems

using V"DL

C$apter Num/er: /6 C$apter Title: Design o! net&or<s !or

arithmetic o%erations

'lanned Hours: /9

Cha%ter Learning (b)ecti'es


+. 9nderstand t$e concept state grap$ and state mac$ines.++

. Design serial adder circuits for an( n /it mentioned.+,+#

#. Design of /inar( multiplier for an( n /it mentioned.+6,+56. Design of /inar( di2ider for an( n /it mentioned.+8

5. rite 0HD codes for all t$e a/o2e mentioned designs.+,+;

esson !c$edule


++. Concept of state grap$+. Design of serial adder 1it$ accumulator

+#. !tate and control grap$s

+6. Design of a signed /inar( multiplier

+5. Design of a unsigned /inar( multiplier+8. Design of a /inar( di2ider signed and unsigned.

+. Design an( arit$metic net1or%s 1it$ 0HD codes.

+;. Design an( arit$metic net1or%s 1it$ 0HD codes.

e'ie& Buestions:

+. Illustrate 1it$ a state grap$ and /loc% diagram $o1 an ; /it num/er can /e di2ided

/( a 6 /it num/er.. Design a 6 /it arra( multiplier.




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9!N

0M3M I0STIT5TE (2 TEC"0(L(4, 0ITTE

(An Autonomous Institution affiliated to VTU, Belgaum

I Semester M.Tech. *EC+ Mid Semester E;aminations-I

Sam%le Pa%er

1#VDE111-M(DELI0 (2 DIIT3L S4STEMS 5SI0 V"DL

Duration: + Hour Ma<. Mar%s: "

Note! " Ans#er any one full $uestion from each unit

5nit A I

+.

a4

rite a procedure to add -6 /it /inar( num/ers

"5

/4

$at are t$e 2arious o/ects in 0HD e<plain t$em 1it$ e<amples

"5




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.

a4

rite a code in 0HD for a !*->> using structural st(le and /e$a2ioral st(le .

"5

/4

rite $o1 /inding ta%es place /et1een components and t$e entit( 1it$ a 0HD code.

"5

5nit A II

#.

a4

Design a t1oJs compliment multiplier /( gi2ing t$e state grap$ and t$e /loc% diagram

"6

/4

rite a 0HD code for t$e a/o2e mentioned statement

"8




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6.

a4

it$ t$e $elp of a state grap$ and state ta/le design a /inar( di2ider

"8

/4

T1o constraints t$at $a2e to /e placed on t$e input la/els to $a2e a completel( specified proper

state grap$. ustification for t$e statements 1it$ an e<ample

"6

50IT-III*i+


using V"DL

C$apter Num/er: "# C$apter Title: Standard combinational

modules

'lanned Hours: "8




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+. Design decoders 1it$ 2arious decoding net1or%s.+

. Design /inar( encoders 1it$ appropriate applications .",+

#. 9nderstand multiple<er tree structures.,#

6. Design s$ifters and implement t$em in2arious modules.6Lesson Schedule


+. inar( decoders and tree structures.

". ". inar( encoders 1it$ applications+. 'riorit( encoders.

. Multiple<er design 1it$ tree structures.

#. De multiple<ers design 1it$ 2arious tree structures.6. !$ifters designs to /e co2ered.

.

e'ie& Buestions:

+. Implement t$e follo1ing multiple output function using #:; decoder and e<ternal gates.

>+ 3a,/,c4Lm3+,6,5,4 > 3a,/,c4L M3,#,8,4


using V"DL

C$apter Num/er: "# C$apter Title: * egister-trans!er le'el

sstems

'lanned Hours: "8




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After studying this chapter, the student should be able to:

5. *elate and find $o1 e<ecutions grap$s can /e dra1n for t$e e?uation gi2en5,8

8. >ind $o1 t$e s(stems are organi7ed.

. Gno1 $o1 an *T s(stem can /e designed using 0HD.;,;. Anal(7e t$e *T design.#"

esson !c$edule

Class No.-'ortion co2ered per $our

5. Implementation of 2arious modules 1it$ s$ifting properties.

8. E<ecutions grap$s for different mat$ematical e?uations.. Design of se?uential, group se?uential, concurrent s(stem.

;. !pecification of *T s(stems.

. Data and control su/s(stem designs.#". 0HD code for *T designs.

e'ie& Buestions:

i. Design a unimodule data su/s(stem for e2aluating t$e pol(nomial

'53<4 ¿∑i=0

5

p xi

50IT IV


using V"DL

C$apter Num/er: "# C$apter Title: Data and Control Subsstem




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'lanned Hours: +"



+. Design !torage modules, functional modules and data pat$.#+, #

. Design an o2erall data su/s(stem.##, #6#. Design of control su/s(stem.#5, #8

6. )et an Insig$t to Micro programmed controller operations#, #;

5. rite 0HD code for t$e a/o2e mentioned topics.#, 6"

Lesson Schedule

Class No.%Portion covered per hour

#+. !torage modules

#. >unctional modules

##. Design of data su/s(stem 1it$ 0HD code.

#6. Design of data su/s(stem 1it$ 0HD code

#5. Design of control su/s(stem 1it$ 0HD code

#8. Design of control su/s(stem 1it$ 0HD code#. Micro programmed controller.

#;. E<amples of micro programmed s(stems

#. An( design e<ample 1it$ 0HD code.

6". An( design e<ample 1it$ 0HD code.

e'ie& Buestions:

+. it$ t$e $elp of a /loc% diagram e<plain micro programmed controller.

. it$ t$e $elp of /loc% and timing diagram e<plain t$e se?uence of e2ents in data

Sub system for arithmetic and logic instructions during the

execution of the instruction.

9!N






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I Semester M.Tech. *EC+ Mid Semester E;aminations-II

Sam%le Pa%er

1#VDE111-M(DELLI0 (2 DIIT3L S4STEMS 5SI0 V"DL

Duration: + Hour Ma<. Mar%s: "

Note! " Ans#er any one full $uestion from each unit

5nit A I

+.

a4

Implement t$e follo1ing multiple output function using #:; decoder and e<ternal gates

>+ 3a,/,c4Lm3+,6,5,4 > 3a,/,c4L M3,#,8,4

"5

/4

Implement a si< input decoder using coincident and tree decoder net1or%s and gi2e t$e

comparison /et1een t$e t1o in terms of decoder modules and AND gates

"5

.




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a4

Design a /it rig$t s$ifter using multiple<er.

"5

/4

Implement a su/tractor using #:; decoder and e<ternal gates

"5

5nit A II

#.

a4




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>ig #.a

rite a 0HD code for t$e data su/s(stem s$o1n in figure#.a

"8

/4

rite an( four c$aracteristics of *T le2el s(stem.

"6

6.

a4

rite a 0HD code for 6 /it serial parallel multiplier.




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"8

/4

!$o1 $o1 t$e 1or%ing of t$e serial parallel multiplier can /e traced

"6

50IT AV

Cha%ter &ise Plan

Course Code: 1#VDE111 Course Title: Modeling o! Digital Sstemsusing V"DL

C$apter Num/er: 1/ C$apter Title: S%eci!ication and

Im%lementation o! a Microcom%uter

'lanned Hours: 16




-------------------------------------------------------------------------------------------------------------------------------



+. Implement a memor( su/s(stem.6+-66

. Implement a 'rocessor of gi2en specifications.#. =ptimi7e t$e memor( su/s(stem design.

6. Implement t$e data !u/s(stem.

5. Implement a simple microcomputer s(stem 5"-5

Lesson Schedule


6+. asic concept of a computer

6. !pecification of t$e memor( su/s(stem, data !u/s(stem, I@= su/s(stem.

6#. !pecification of t$e memor( su/s(stem, data !u/s(stem, I@= su/s(stem

66. !pecification of t$e memor( su/s(stem, data !u/s(stem, I@= su/s(stem65. Implementation of memor( su/s(stem, data !u/s(stem, I@= su/s(stem

68. Implementation of memor( su/s(stem, data !u/s(stem, I@= su/s(stem

6. Implementation of memor( su/s(stem, data !u/s(stem, I@= su/s(stem6;. Implementation of memor( su/s(stem, data !u/s(stem, I@= su/s(stem

6. =peration of t$e computer and c(cle.

5". 0HD codes for t$e design of memor( su/s(stem, data !u/s(stem.5+. 0HD codes for t$e design of memor( su/s(stem, data !u/s(stem.

5. 0HD codes for t$e design of memor( su/s(stem, data !u/s(stem.

e'ie& Buestions:

+. Dra1 t$e /loc% diagram, internal organi7ation and timing diagram for a memor(

su/s(stem suita/le for a microcomputer.

. rite t$e 0HD entit( declaration and a /e$a2ioral description for t$e a/o2e memor(

su/s(stem.

9!N



65-6




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I Semester M.Tech *EC+ *Credit Sstem+ Degree E;aminations

Model Buestion %a%er

1#VDE111-M(DELLI0 (2 DIIT3L S4STEMS 5SI0 V"DL

Duration: # Hours Ma<. Mar%s: +""

Note! " Ans#er one question from each unit

50IT I

+.

a4

rite a 0HD code for ;:+ M9O using /e$a2ioral, Dataflo1 and structural st(le of modeling

"

/4

it$ e<amples e<plain t$e 2arious data o/ects present in 0HD.

"8

c4

Design using a 6:+ multiple<er for t$e follo1ing function

E3<,<+,<"4 Lm3+,,6,8,4

"5

.




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a4

E<plain 0HD data o/ects 1it$ e<amples and also gi2e t$e general s(nta< for t$e same.

"8

/4

Design a 6-/it up counter using structural st(le of modeling and also 1rite t$e code

";

c4

rite a 0HD function to con2ert integer to /inar(.

"8

50IT II

#.

a4

Design a 6 /it serial parallel multiplier 1it$ e<ample.

"8

/4

rite t$e 0HD code for a 6 /it serial parallel multiplier for data and control su/s(stem

+6




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6.

a4

Design a /loc% diagram for signed /inar( fast multiplier.

"#

/4

it$ t$e $elp of a state grap$ 1rite a 0HD code for signed /inar( fast multiplier.

";

c4

rite a /loc% Diagram of signed di2ider and e<plain 1it$ an e<ample $o1 o2erflo1 is detected

in case of signed di2ision.

"8

d4

rite t$e state grap$ for signed di2ider control net1or%.

"#

50IT III

5.

a4

>or t$e pol(nomial of degree se2en gi2en /elo1 ,Design a s(stem 1it$ non-s$aring functional

units and decentrali7ed control




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";

/4

Design a data su/s(stem and control su/s(stem for t$e s(stem specified .rite a generali7ed

0HD code for data and control su/s(stem.

+

8.

a4

it$ neat /loc% diagram e<plain structure of *T s(stems

+"

/4

rite a 0HD code for t$e register transfers for t$e a/o2e e<plained *T s(stem

+"




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.

a4

Dra1 a /loc% diagram of a t(pical /loc% diagram of a t(pical microprogrammed controller and

/riefl( descri/e its modules.

";

/4

ring out t$e ad2antages of a microprogrammed controller 1it$ respect to a controller implemented as a fi<ed net1or%.

"

c4

E<plain microinstruction formats and microinstruction se?uencing.

+"

;.

a4

Define register file used in a data su/s(stem. rite 0HD description for a register file t$at can

perform t1o read and one 1it$ operation onl( 1rite control signal. *ead operations are

performed 1$ene2er address applied to *A and *A* inputs.

+




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/4

rite t$e structure of cross /ar data pat$ and e<plain /riefl(. rite a 0HD code for t$e same.

";

.

a4

E<plain t$e se?uence of e2ents in data su/s(stems for arit$metic logic instruction

"6

/4

rite t$e /loc% diagram for t$e se?uence of e2ents in data su/s(stems

";

c4

rite t$e timing diagram in data su/s(stems for arit$metic logic instruction

";

+".




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a4

)i2e a description of $o1 t$e operation of t$e computer and its c(cle time calculations are

performed.

+"

/4

Dra1 t$e /loc% diagram, internal organi7ation and timing diagram for a memor( su/s(stem

suita/le for t$e design of a microcomputer s(stem.

+"

mdsv lesson plan 2015 revised

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