Mcu And Fpga-based Digital Storage Oscilloscope SimpleDesign

L Introduction Along With conventional analog Oscilloscopes Compared. Digital StorageOscilloscope not only can be stored waveform, little size, lower power consumption andstraightforward use, but additionally has potent real-time signal processing analysis. Inside the fieldof electronic measurement, digital storage oscilloscope will be gradually replacing analogoscilloscope. However, China using high-performance digital storage oscilloscopes rely mainly uponforeign products, but inside addition expensive. Therefore the research offers crucial value digitalstorage oscilloscope. By Simply this, a simple kind of digital storage oscilloscope, tested as well asoutstanding performance.

2 simple principle associated with digital storage oscilloscope

Digital storage oscilloscope with the analog signal into the oscilloscope oscilloscope distinction is theextremely fact that right away following the high-speed Any / D converter sampling GatedCommunity Homes Sale Penn Quarter DC the particular analog signal front-end quickly, retailertheir digital signal. As Well As use associated with digital signal processing technology pertaining toreal-time data stored fast processing, waveform as well as its parameters obtained from theoscilloscope display, that features analog oscilloscope, and also higher precision. Can Easily retailerthe signal, thus, digital storage oscilloscope could shop as well as call the particular present acertain period signal.

3 System Demonstration 3.1 Any / D Real-Time Sampling

According in order to Nyquist sampling Gated Community Penn Quarter DC theorem, the samplingrate has to always be able to be more than two times the highest frequency signal components. WithRegard To sinusoidal signals, during the week there should be two sampling points. Within order torevive the actual measured signal just isn't distorted, typically throughout the week have to testgreater than 8 points. Within order in order to satisfy the high-speed ADC, making use of FPGAmanage M / D converter sampling rate, to be able in order to achieve high-speed real-time sampling.Real-time sampling allows sampling the actual band with total speed, the actual system selectedADI's 12-bit high-speed a / D converter AD9220, the utmost sampling charge approximately 10MHz.

3.2 Double-trace display Your dual track system style based on high-speed switching analog displaymodule Swap Gated sampling circuit in to 2 signals, two-way waveform will be stored inside amemory using odd as well as address bits. Dual trace display, scan address information bit odd, andthen scan even address information bit. Analog Change As an alternative associated with an ADC,for you to steer clear of both high-speed The / D converter mutual interference, reduced systemdebugging difficult, and also the system functions.

3.3 trigger Use FPGA internal computer software trigger, trigger level set by simply software, theactual Schmitt trigger parameter set easily modified in order to inhibit the comparator glitch. Whenthe sample is actually higher compared to trigger level, then develop a trigger. The Actual approachtends to make better use regarding FPGA resources, decrease the external circuit, getting rid of theinterference generated hardware glitch, simple to adjust your trigger voltage.

3.4 Regulation in the waveform display position

3.4.1 Range Scan regulation

By governing the FPGA internal dual-port RAM (1KB) with the beginning address offset to managethe actual waveform to appear with regard to the movement. The Particular certain method isusually to slide rheostat R on the degree can be transformed in order to digital signals by simplyanalog transmission towards the FPGA, then a first degree digital signal (reset if the displayposition, sliding rheostat R, degree test values) in contrast decide your beginning address ADR0offsets. the technique could be easily implemented as well as automatic full screen waveformdisplay.

3.4.2 Regulation regarding Row

MAXl97 sample A, B channel Situation Potentiometers Value, the worth obtained by the FPGAexamples sent for the 16-bit serial D / a converter, MAX542 generated DC level, the actual DCdegree along with column sum sent to the analog oscilloscope scan waveform display, waveform upor as any outcome of achieve. Pertaining To the separation regarding A, B channel, some time whenA-channel waveform data, FPGA has to be sent PositionA potentiometer value D / Any converter;although studying the actual B-channel waveform data, it has to be sent PositionB potentiometerworth D / The converter, it can easily modify the potentiometer, the realization regarding the relatedchannel wave progress as well as down.

3.5 waveform data storage Digital oscilloscope waveform information storage may use an externaldual-port static RAM, or perhaps general-purpose RAM, although FPGA may manage your RAMaddress lines, thereby achieving waveform data storage. Dual-port RAM can be simultaneously studyalong with write operations, as the system style utilizing FPGA, thus help make better use associatedwith FPGA logic array and embedded array, dual-port RAM can be created for the internal FPGA,getting rid of the need for external RAM, to lessen hardware, boost the actual reliability of simpledigital oscilloscope.

4 system style Your system block diagram demonstrated within Figure 1. The Actual total product isaccording to FPGA core, including your front-end analog signal processing modules, single chipmodule, display module as well as keyboard module. The Actual signal processing module in additionincludes pre-class shot-class follower, programmable amplifier, shaping circuit. A, B channel signalprocessing from the former class directly into O ~ 4V, AD9220 its sampling. Waveform taste storagecontrol module to create information for you to FPGA internal RAM, then a waveform displaymanage module to end up being able to display. FPGA programming set to end up being able toattain by simply measuring frequency, keyboard scanning, display drivers, waveform memorymanage functions. MCU AT89S52 manage the keyboard and in addition the complete system LatticeLCD module with regard to human-computer interaction. Panel buttons may be effortlessly adjustedfrom the waveform display.

5 hardware style 5.1 Programmable Amplifier Analog switches CD4051, broadband operationalamplifier AD844 as well as Precision Potentiometer 10mV/div ~ 2V/div vertical resolution of multi-file. FPGA module together with channel select register, write the channel number via the actualMCU to control the actual analog swap strobe different feedback resistor, to always be able toaccomplish various magnification, the particular signal conditioning to satisfy the AD9220 within therange of 0 ~ 4V, your specific circuit proven inside Figure two .

5.2 data Acquisition Module The Particular system uses ADI's AD9220 high-speed ADCs toaccomplish waveform signal acquisition, AD9220 maximum sampling charge approximately 10MHz,having an external crystal Oscillator 8MHz, FPGA realization involving internal waveform memorythrough sampling. AD9220 offers a couple of DC-coupled and also AC-coupled input. This particularsystem uses DC-coupled, 0 ~ 5V input mode. using your internal 2.5V reference voltage. Since theactual system only 255 vertical resolution, therefore it's substantial 8-bit AD9220. data acquisitioncircuit shown in Figure 3.

5.3 FPGA Style System makes use of VerilogHDL language computer software in QuartusIIconducted below your FPGA logic description regarding programming versatility and controlcircuitry required in order to achieve your system module.

5.3.1 Trigger Module

Single chip FPGA module will be created initial for you to set your trigger voltage, FPGA internalcomparison