mcp6n16 · mcp6n16-100 100 17 60 112 110 0.027 35 0.93 45 note 1: gmin is the minimum stable gain...

MCP6N16Zero-Drift Instrumentation Amplifier

Features:

• High DC Precision:

- VOS: ±17 µV (maximum, GMIN = 100)

- TC1: ±60 nV/°C (maximum, GMIN = 100)

- CMRR: 112 dB (minimum, GMIN = 100, VDD = 5.5V)

- PSRR: 110 dB (minimum, GMIN = 100, VDD = 5.5V)

- gE: ±0.15% (maximum, GMIN = 10, 100)

• Flexible:

- Minimum Gain (GMIN) Options:1, 10 and 100 V/V

- Rail-to-Rail Input and Output

- Gain Set by Two External Resistors

• Bandwidth: 500 kHz (typical, Gain = GMIN = 1, 10)

• Power Supply:

- VDD: 1.8V to 5.5V

- IQ: 1.1 mA (typical)

- Power Savings (Enable) Pin: EN

• Enhanced EMI Protection:

- Electromagnetic Interference Rejection Ratio (EMIRR): 111 dB at 2.4 GHz

• Extended Temperature Range: -40°C to +125°C

Typical Applications:

• High-Side Current Sensor

• Wheatstone Bridge Sensors

• Difference Amplifier with Level Shifting

• Power Control Loops

Design Aids:

• SPICE Macro Model

• Microchip Advanced Part Selector (MAPS)

• Application Notes

Description:

Microchip Technology Inc. offers the single Zero-DriftMCP6N16 instrumentation amplifier (INA) with Enablepin (EN) and three minimum gain options (GMIN). Theinternal offset correction gives high DC precision: it hasvery low offset and offset drift, and negligible 1/f noise.

Two external resistors set the gain, minimizing gainerror and drift over temperature. The reference voltage(VREF) shifts the output voltage (VOUT).

The MCP6N16 is designed for single-supply operation,with rail-to-rail input (no common mode crossoverdistortion) and output performance. The supply voltagerange (1.8V to 5.5V) is low enough to support manyportable applications. All devices are fully specifiedfrom -40°C to +125°C. Each part has EMI filters at theinput pins, for good EMI rejection (EMIRR).

These parts have three minimum gain options (1, 10and 100 V/V). This allows the user to optimize the inputoffset voltage and input noise for different applications.

Typical Application Circuit

Package Types

VOUT

20 kΩ

100Ω

2.49 kΩ

68.1Ω RTD

4.99 kΩ

VDD

MCP6N16-100

10 µF

100Ω

EN

100Ω

RTD Temperature Sensor

4.99 kΩ 4.99 kΩ

MCP6N16MSOP

VIP

VIM

VSS

VOUT

VFG

1

2

3

4

8

7

6

5 VREF

VDDEN

MCP6N163×3 DFN *

VIP

VIM

VSS

VOUT

VFG

1

2

3

4

8

7

6

5 VREF

VDDEN

* Includes Exposed Thermal Pad (EP); see Table 3-1.

EP9

2014 Microchip Technology Inc. DS20005318A-page 1

MCP6N16

Minimum Gain Options

Table 1 shows key specifications that differentiatebetween the different minimum gain (GMIN) options.See Section 1.0 “Electrical Characteristics”,Section 6.0 “Packaging Information” and ProductIdentification System for further information on GMIN.

Figures 1 to 3 show input offset voltage versustemperature for the three gain options (GMIN = 1, 10,100 V/V).

FIGURE 1: Input Offset Voltage vs. Temperature, with GMIN = 1.



TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS

Part No.GMIN(V/V)Nom.

VOS(±μV)Max.

TC1(±nV/°C)

Max.TA = -40 to +125°C

CMRR(dB)Min.

VDD = 5.5V

PSRR(dB)Min.

VDMH(V)

Min.

GBWP(MHz)Typ.

Eni(μVP-P)

Typ.f = 0.1 to 10 Hz

eni(nV/√Hz)

Typ.f < 500 Hz

MCP6N16-001 1 85 1800 89 91 2.7 0.50 19 900

MCP6N16-010 10 22 180 103 104 0.27 5.0 2.2 105

MCP6N16-100 100 17 60 112 110 0.027 35 0.93 45

Note 1: GMIN is the minimum stable gain (GDM), for a given part option. In other words, GDM ≥ GMIN.

-10

0

10

20

30

40

Offs

et V

olta

ge (µ

V)

-40

-30

-20

0

-50 -25 0 25 50 75 100 125

Inpu

tO

Ambient Temperature (°C)

GMIN = 128 SamplesVDD = 5.5VVCM = VDD/2NPBW = 3 mHz

3

4

2

3

e (µ

V)

1

Volta

ge

-1

0

Offs

etV

-2

nput

O

GMIN = 1028 SamplesV 5 5V

4

-3

I VDD = 5.5VVCM = VDD/2NPBW = 3 mHz

-4-50 -25 0 25 50 75 100 125


3

4

2

3

e (µ

V)1

Volta

ge

-1

0

Offs

etV

-2

nput

O

GMIN = 10028 SamplesV = 5 5V

4

-3

I VDD = 5.5VVCM = VDD/2NPBW = 3 mHz

-4-50 -25 0 25 50 75 100 125


DS20005318A-page 2 2014 Microchip Technology Inc.

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1.

1.

VD ........................................................ 6.5V

Cu ..................................................... ±2 mA

An .......................VSS – 1.0V to VDD + 1.0V

All .......................VSS – 0.3V to VDD + 0.3V

Dif ............................................. |VDD – VSS|

Ou ............................................. Continuous

Cu ................................................... ±30 mA

Sto ..................................... -65°C to +150°C

Ma ....................................................+150°C

ES ........................................... ≥ 4 kV, 400V

N

† is is a stress rating only and functionalop n is not implied. Exposure to maximumra

0 ELECTRICAL CHARACTERISTICS

1 Absolute Maximum Ratings †

D – VSS ....................................................................................................................................................................................

rrent at Input Pins (Note 1) ......................................................................................................................................................

alog Inputs (VIP and VIM) (Note 1) ...........................................................................................................................................

Other Inputs and Outputs ........................................................................................................................................................

ference Input Voltage ................................................................................................................................................................

tput Short-Circuit Current .........................................................................................................................................................

rrent at Output and Supply Pins ...............................................................................................................................................

rage Temperature ....................................................................................................................................................................

ximum Junction Temperature ..................................................................................................................................................

D protection on all pins (HBM, MM)..........................................................................................................................................

ote 1: See Section 4.3.1.2 “Input Voltage Limits” and Section 4.3.1.3 “Input Current Limits”.

Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Theration of the device at those or any other conditions above those indicated in the operational listings of this specificatioting conditions for extended periods may affect device reliability.

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= 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ

GMIN Conditions

1 TA = +25°C

10

100

1 TA = -40°C to +125°C (Note 2)

10

100

1 TA = -40°C to +125°C

10

100

1 408 hr Life Test at +150°C, measured at +25°C10

100

1

10

100

all

all

TA = +85°C

TA = +125°C

ad).

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM

to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

Parameters Sym. Min. Typ. Max. Units

Input Offset

Input Offset Voltage VOS -85 — +85 µV

-22 — +22

-17 — +17

Input Offset Voltage Drift –Linear Temp. Co.

TC1 -1800 — +1800 nV/°C

-180 — +180

-60 — +60

Input Offset Voltage Drift –Quadratic Temp. Co.

TC2 — ±560 — pV/°C2

— ±63 —

— ±69 —

Input Offset Aging ∆VOS — ±1.0 — µV

— ±0.8 —

— ±0.7 —

Power Supply Rejection Ratio PSRR 91 109 — dB

104 122 —

110 128 —

Output Offset

Output Offset Voltage VOSO 0 µV

Input Current and Impedance (Note 3)

Input Bias Current IB -100 ±2 +100 pA

Across Temperature — 20 —

Across Temperature 0 250 2000

Note 1: VCM = (VIP + VIM)/2, VDM = (VIP – VIM) and GDM = 1 + RF/RG.2: For Design Guidance only; not tested.3: These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF inste4: This specification applies to the VIP, VIM, VREF and VFG pins individually.5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.6: See Section 1.5 “Explanation of DC Error Specifications”.

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In all

TA = +85°C

TA = +125°C

C

D

In

In all

C 1 VCM = VIVL to VIVH, VDD = 1.8V

10

100

1 VCM = VIVL to VIVH, VDD = 5.5V

10

100

C 1 VREF = 0.2V to VDD – 0.2V,VDD = 1.8V10

100

1 VREF = 0.2V to VDD – 0.2V,VDD = 5.5V10

100

TA

El , VREF = VDD/2, VL = VDD/2, RL = 10 kΩ

to

MIN Conditions

N

put Offset Current IOS -800 ±300 +800 pA

Across Temperature — ±320 —

Across Temperature -1500 ±350 +1500

ommon Mode Input Impedance ZCM — 1013||10 — Ω||pF

ifferential Input Impedance ZDIFF — 1013||4 —

put Common Mode Voltage (VCM or VREF) (Note 3)

put Voltage Range (Note 4, Note 5) VIVL — VSS – 0.25 VSS – 0.15 V

VIVH VDD + 0.15 VDD + 0.30 —

ommon Mode Rejection Ratio CMRR 80 98 — dB

94 112 —

103 121 —

89 107 —

103 121 —

112 130 —

ommon Mode Rejection Ratio at VREF CMRR2 83 101 — dB

98 116 —

102 120 —

94 112 —

109 127 —

115 133 —

BLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

ectrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V

VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

Parameters Sym. Min. Typ. Max. Units G

ote 1: VCM = (VIP + VIM)/2, VDM = (VIP – VIM) and GDM = 1 + RF/RG.2: For Design Guidance only; not tested.3: These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).4: This specification applies to the VIP, VIM, VREF and VFG pins individually.5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.6: See Section 1.5 “Explanation of DC Error Specifications”.

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10

100


10

100

all VDD ≥ 2.9V, VREF = VDD,VOUT within ±0.2%

VDD ≥ 2.9V, VREF = 0V,VOUT within ±0.2%

1 VDD = 1.8V, VREF = VDD/2,VDM = ±(0.7V)/GMIN10, 100

1 VDD = 5.5V, VREF = VDD/2,VDM = ±(2.55V)/GMIN10, 100

1 VDD = 5.5V, VREF = 0.2V,VDM = 0 to (2.7V)/GMIN10, 100

1 VDD = 5.5V, VREF = 5.3V,VDM = 0 to (-2.7V)/GMIN10, 100


GMIN Conditions

ad).

Common Mode Nonlinearity (Note 6) INLCM -550 — +550 ppm

-75 — +75

-20 — +20

-310 — +310

-35 — +35

-10 — +10

Input Differential Voltage (VDM) (Note 3)

Differential Input Voltage Range (Note 5) VDML — -3.4/GMIN -2.7/GMIN V

VDMH +2.7/GMIN +3.4/GMIN —

Differential Gain Error (Note 6) gE — ±0.03 — %

— ±0.02 — %

— ±0.03 —

— ±0.02 —

-0.25 ±0.04 +0.25 %

-0.15 ±0.02 +0.15 %

-0.25 ±0.04 +0.25 %

-0.15 ±0.02 +0.15 %

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)





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D all VDD = 1.8V, VREF = VDD/2,VDM = ±(0.7V)/GMIN

VDD = 5.5V, VREF = VDD/2,VDM = ±(2.55V)/GMIN

VDD = 5.5V, VREF = 0.2V,VDM = 0 to (2.7V)/GMIN

VDD = 5.5V, VREF = 5.3V,VDM = 0 to (-2.7V)/GMIN

D all VDD = 1.8V, VREF = VDD/2,VDM = ±(0.7V)/GMIN

VDD = 5.5V, VREF = VDD/2,VDM = ±(2.55V)/GMIN

VDD = 5.5V, VREF = 0.2V,VDM = 0 to (2.7V)/GMIN

VDD = 5.5V, VREF = 5.3V,VDM = 0 to (-2.7V)/GMIN

D 1 VDD = 1.8V,VOUT = 0.2V to 1.6V10

100

1 VDD = 5.5V,VOUT = 0.2V to 5.3V10

100

TA

El , VREF = VDD/2, VL = VDD/2, RL = 10 kΩ

to

MIN Conditions

N

ifferential Gain Drift (Note 6) ∆gE/∆TA — ±3 — ppm/°C

— ±4 —

— ±4 —

— ±3 —

ifferential Nonlinearity (Note 6) INLDM — ±300 — ppm

— ±150 —

— ±300 —

— ±300 —

C Open-Loop Gain AOL 84 102 — dB

100 118 —

108 126 —

95 113 —

111 129 —

119 137 —

BLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

ectrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V

VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

Parameters Sym. Min. Typ. Max. Units G

ote 1: VCM = (VIP + VIM)/2, VDM = (VIP – VIM) and GDM = 1 + RF/RG.2: For Design Guidance only; not tested.3: These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).4: This specification applies to the VIP, VIM, VREF and VFG pins individually.5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.6: See Section 1.5 “Explanation of DC Error Specifications”.

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all RL = 10 kΩ, VDD = 1.8V,VDM = -VDD/(2GMIN),VREF = VDD/2 – 0.9V

RL = 10 kΩ, VDD = 5.5V,VDM = -VDD/(2GMIN),VREF = VDD/2 – 1V

RL = 1 kΩ, VDD = 5.5V,VDM = -VDD/(2GMIN),VREF = VDD/2 – 1V

RL = 10 kΩ, VDD = 1.8V,VDM = VDD/(2GMIN),VREF = VDD/2 + 0.9V

RL = 10 kΩ, VDD = 5.5V,VDM = VDD/(2GMIN),VREF = VDD/2 + 1V

RL = 1 kΩ, VDD = 5.5V,VDM = VDD/(2GMIN),VREF = VDD/2 + 1V

VDD = 1.8V

VDD = 5.5V

all

IO = 0


GMIN Conditions

ad).

Output

Minimum Output Voltage Swing VOL — VSS + 3 — mV

— VSS + 6 —

— VSS + 60 VSS + 250

Maximum Output Voltage Swing VOH — VDD – 3 — mV

— VDD – 6 —

VDD – 250 VDD – 60 —

Output Short-Circuit Current ISC — ±10 — mA

— ±35 —

Power Supply

Supply Voltage VDD 1.8 — 5.5 V

Quiescent Current per Amplifier IQ 0.5 1.1 1.6 mA

POR Trip Voltage VPRL 0.9 1.27 — V

VPRH — 1.33 1.6 V

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)





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TA

El V, VREF = VDD/2, VL = VDD/2,

R

onditions

A

G

P

O

Po

C

St

S

St 0.1% VOUT settling (Note 3, Note 4)

O – 1V (or VIVL – 0.5V to 1V),A) (Note 4)

O to 0V (or GMINVDML – 0.5V to 0V), of VOUT change (Note 4)

O V to 0V), of VOUT change (Note 4)

N

e at DC, a residual tone at 100 Hz and

BLE 1-2: AC ELECTRICAL SPECIFICATIONS

ectrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0

L = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.

Parameters Sym. Min. Typ. Max. Units GMIN C

C Response

ain-Bandwidth Product GBWP — 0.5 — MHz 1

— 5 — 10

— 35 — 100

hase Margin PM — 70 — ° all

pen-Loop Output Impedance ROL — 1.6 — kΩ

wer Supply Rejection Ratio PSRR — 80 — dB 1 f = 1 kHz

— 98 — 10

— 123 — 100

ommon Mode Rejection Ratioat VCM and VREF

CMRR, CMRR2 — 83 — dB 1 f = 10 kHz

— 80 — 10

— 140 — 100

ep Response (see Section 4.1.4 “AC Performance”)

lew Rate SR Note 1 V/µs all

art-Up Time tSTR — 2 — ms 1 GDM = 1000, VDD power up to

— 0.3 — 10

— 0.2 — 100

verdrive Recovery,Input Common Mode

tIRC — 1 — µs all VIP =VIM = VIVH + 0.5V to VDD90% of VOUT change (IB ≤ 2 m

verdrive Recovery,Input Differential Mode

tIRD — 10 — GMINVDM = GMINVDMH + 0.5VVREF = 1V (or VDD – 1V), 90%

verdrive Recovery, Output tOR — 180 — GDMVDM = 1.5V to 0V (or -1.5VREF = VDD – 1V (or 1V), 90%

ote 1: The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.

2: These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tonother IMD tones and clock tones.

3: High gains behave differently; see Section 4.4.4 “Offset at Power-Up”.

4: tSTR, tSTL, tIRC, tIRD and tOR include some uncertainty due to clock edge timing.

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100 Hz

z

z

Hz

Hz

= 0V, VREF = VDD/2, VL = VDD/2,

Conditions

idth.

D tone at DC, a residual tone at 100 Hz and

Noise

Input Noise Voltage Density eni — 900 — nV/√Hz 1 f = 500 Hz

— 105 — 10

— 45 — 100

Input Noise Voltage Eni — 19 — µVP-P 1 f = 0.1 Hz to 10 Hz

— 2.2 — 10

— 0.93 — 100

— 5.9 — 1 f = 0.01 Hz to 1 Hz

— 0.69 — 10

— 0.30 — 100

Input Current Noise Density ini — 7 — fA/√Hz all f = 1 kHz

Output Noise Voltage Density eno 0 nV/√Hz

Output Noise Voltage Eno 0 µVP-P

Amplifier Distortion (Note 2)

Intermodulation Distortion (AC) IMD — 5 — µVPK all VCM tone = 100 mVPK at

EMI Protection

EMI Rejection Ratio EMIRR — 103 — dB all VIN = 0.1 VPK, f = 400 MH

— 106 — VIN = 0.1 VPK, f = 900 MH

— 106 — VIN = 0.1 VPK, f = 1800 M

— 111 — VIN = 0.1 VPK, f = 2400 M

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS (CONTINUED)


RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.

Parameters Sym. Min. Typ. Max. Units GMIN

Note 1: The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandw

2: These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMother IMD tones and clock tones.

3: High gains behave differently; see Section 4.4.4 “Offset at Power-Up”.

4: tSTR, tSTL, tIRC, tIRD and tOR include some uncertainty due to clock edge timing.

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TAB

Elec VREF = VDD/2, VL = VDD/2,

RL =

Conditions

EN L

EN L

EN I

GND

Amp

EN H

EN L

EN I

EN D

EN I

EN I

EN L 0.1(VDD/2), VL = 0V

EN H DD to VOUT = 0.9(VDD/2), VL = 0V

DD to VOUT = 0.9(VDD/2), VL = 0V

EN L eleasing EN (Note 1)

EN H xerting EN (Note 1)

POR

VDD VPRL – 0.1V step, 90% of VOUT change

VDD PRH + 0.1V step, 90% of VOUT change

Note

LE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

trical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,

10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.

Parameters Sym. Min. Typ. Max. Units GMIN

ow Specifications

ogic Threshold, Low VIL — — 0.2VDD V all

nput Current, Low IENL — -10 — pA EN = 0V

Current ISS -8 -2 — µA EN = 0V, VDD = 5.5V

lifier Output Leakage IO(LEAK) — -1 — nA EN = 0V

igh Specifications

ogic Threshold, High VIH 0.8VDD — — V all

nput Current, High IENH — 10 — pA EN = VDD

ynamic Specifications

nput Hysteresis VHYST— 0.16VDD

— V all

nput Resistance RPD— 1013 — Ω

ow to Amplifier Output High Z Turn-Off Time tOFF — 0.1 2 µs EN = 0.2VDD to VOUT =

igh to Amplifier Output On Time tON — 12 100 VDD = 1.8V, EN = 0.8V

— 30 100 VDD = 5.5V, EN = 0.8V

ow to EN High hold time tENLH 50 — — Minimum time before r

igh to EN Low setup time tENHL 50 — — Minimum time before e

Dynamic Specifications

↓ to Output Off tPHL — 10 — µs all VL = 0V, VDD = 1.8V to

↑ to Output On tPLH — 100 — VL = 0V, VDD = 0V to V

1: For design guidance only; not tested.

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Units Conditions

°C

Note 1

°C/W

TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = 1.8V to 5.5V, VSS = GND.

Parameters Sym. Min. Typ. Max.

Temperature Ranges

Specified Temperature Range TA -40 — +125

Operating Temperature Range TA -40 — +125

Storage Temperature Range TA -65 — +150

Thermal Package Resistances

Thermal Resistance, 8L-DFN (3×3) θJA — 57 —

Thermal Resistance, 8L-MSOP θJA — 211 —

Note 1: Operation must not cause TJ to exceed the Absolute Maximum Junction Temperature specification (+150°C).

MCP6N16

1.3 Timing Diagrams

FIGURE 1-1: Amplifier Start-Up Timing Diagram.

FIGURE 1-2: Common Mode Input Overdrive Recovery Timing Diagram.

FIGURE 1-3: Differential Mode Input Overdrive Recovery Timing Diagram.

FIGURE 1-4: Output Overdrive Recovery Timing Diagram.

FIGURE 1-5: POR Timing Diagram.

FIGURE 1-6: EN Timing Diagram.

VDD

VOUT

1.001 VREF

0.999 VREF

0V1.8V to 5.5V1.8V

tSTR

VOUT

tIRC

VCMVIVH + 0.5V

VDD – 1V

VREFtIRC

VIVL – 0.5V1V

VREF

VOUT

tIRD

VREF

GDMVDM

1V

0V

VREF

GMINVDMH + 0.5V

VOH

tIRD

VDD – 1V

0V

VREF

GMINVDML – 0.5V

VOL

VOUT

tOR

VREF

GMINVDM

VDD – 1V

0V

VREF

1.5V

VOH

tOR

1V

0V

VREF

-1.5V

VOL

VOUT

tPHL

VDDVPRL – 0.1V

High Z

1.8V

tPLH

VPRH + 0.1V

0V

High Z

VOUT

tOFF

EN

High Z

tON

tENLH tENHL

High Z


MCP6N16

1.4 DC Test Circuits

1.4.1 INPUT OFFSET TEST CIRCUIT

Figure 1-7 is a simple circuit that can test the INA’sinput offset errors and input voltage range (VE, VIVL andVIVH; see Section 1.5.1 “Input Offset RelatedErrors” and Section 1.5.2 “Input Offset CommonMode Nonlinearity”). U2 is part of a control loop thatforces VOUT to equal VCNT; U1 can be set to any biaspoint.

FIGURE 1-7: Simple Test Circuit for Common Mode (Input Offset).

When MCP6N16 is in its normal range of operation, theDC output voltages are (where VE is the sum of inputoffset errors and gE is the gain error):

EQUATION 1-1:

Table 1-5 shows the resulting behavior for differentGMIN options.

1.4.2 DIFFERENTIAL GAIN TEST CIRCUIT

Figure 1-8 is a simple circuit that can test the INA’sdifferential gain error, nonlinearity and input voltagerange (gE, INLDM, VDML and VDMH; see Section 1.5.3“Differential Gain Error and Nonlinearity”). RF andRG are 0.01% for accurate gain error measurements.

The output voltages are (where VE is the sum of inputoffset errors and gE is the gain error):

EQUATION 1-2:

FIGURE 1-8: Simple Test Circuit for Differential Mode.

For different values of VREF, VDM sweeps over differentranges to keep VREF, VFG and VOUT within their ranges.

Table 1-6 shows the recommended RF and RG; theyproduce a 10 kΩ load. VL can usually be left open.

1.4.3 DYNAMIC TESTING OF INPUT BEHAVIOR

The circuit in Figure 1-8 can test the input’s dynamicbehavior (i.e., IMD, tSTR, tSTL, tIRC, tIRD and tOR);measure the output at VOUT, instead of at VM.

TABLE 1-5: RESULTS

GMIN(V/V)Nom.

RF(kΩ)Typ.

GDM(kV/V)Typ.

GDMVOS(±mV)Max.

BW(kHz)Typ.

at VOUT

BW(Hz)Typ.at VM

1 100 1.00 85 0.50 0.50

10 402 4.02 88 1.2

100 68 8.7

RG RF

RL

100 nF

VDD

2.2 µF

VREF

VL

31.6 kΩVM

10 µF CCNT

U1

MCP6N16

U2

MCP6H01

VCNT

31.6 kΩ

RCNT31.6 kΩ

VOUT

2.2 nF

100Ω

100Ω

VCM

2.2 nF

100Ω

GDM 1 RF RG+=

VOUT VCNT=

VM VREF GDM 1 gE+ VE+=

TABLE 1-6: SELECTING RF AND RG

GMIN(V/V)Nom.

RF(kΩ)Nom.

RG(kΩ)Nom.

GDM(V/V)Nom.

1 0 Open 1.0000

10 10.0 || 90.9 1.00 10.009

100 10.0 || 1000 100 100.01

GDM 1 RF RG+=

VM VREF G+DM

1 gE+ VDM VE+ =

VOUT VREF GDM 1 gE+ VDM VE+ +=

RL

63.4 kΩ

100Ω

100Ω

VCM + VDM/2

1.0 µF

VOUT

RF

RG

VM

100 nF

VDD

2.2 µF

VREF

VL

VCM – VDM/2

U1

MCP6N16


MCP6N16

1.5 Explanation of DC Error Specifications

1.5.1 INPUT OFFSET RELATED ERRORS

The input offset error (VE) is extracted from input offsetmeasurements (see Section 1.4.1 “Input Offset TestCircuit”), based on Equation 1-1:

EQUATION 1-3:

VE has several terms, which assume a linear responseto changes in VDD, VSS, VCM, VOUT and TA (all of whichare in their specified ranges):

EQUATION 1-4:

Equation 1-2 shows how VE affects VOUT.

1.5.2 INPUT OFFSET COMMON MODE NONLINEARITY

The input offset error (VE) changes nonlinearly withVCM. Figure 1-9 shows VE vs. VCM, as well as a linearfit line (VE_LIN) based on VOS and CMRR. The INA is instandard conditions (∆VOUT = 0, VDM = 0, etc.). VCM isswept from VIVL to VIVH. The test circuit is inSection 1.4.1 “Input Offset Test Circuit” and VE iscalculated using Equation 1-3.

FIGURE 1-9: Input Offset Error vs. Common Mode Input Voltage.

Based on the measured VE data, we obtain thefollowing linear fit:

EQUATION 1-5:

The remaining error (∆VE) is described by the CommonMode Nonlinearity spec:

EQUATION 1-6:

The same common mode behavior applies to VE whenVREF is swept, instead of VCM, since both input stagesare designed the same:

EQUATION 1-7:

VE VM VREF– GDM 1 gE+ =

Where:

PSRR, CMRR, CMRR2 and AOL are in units of V/V

∆TA is in units of °C

TC1 is in units of V/°C

VDM = 0

VE VOS

VDD VSS–PSRR

---------------------------------VCM

CMRR-----------------

VREF

CMRR2--------------------+ + +=

VOUT

AOL----------------- TA TC1+ +

V1

V3

VE, VE_LIN (V)

VCM (V)

VIVL VIVHVDD/2

V2

VE_LIN

VE

VE

Where:VE_LIN VOS VCM VDD 2– CMRR+=

VOS V2=

1 CMRR V3 V1– VIVH VIVL– =

Where:

INLCMH max VE VIVH VIVL– =

VE VE VE_LIN–=

INLCML min VE VIVH VIVL– =

INLCM INLCMH INLCMH INLCML=

INLCML otherwise=

VE_LIN2 VOS VREF VDD 2– CMRR2+=

INLCMH2 max VE2 VIVH VIVL– =

INLCML2 min VE2 VIVH VIVL– =

Where:VE2 VE VE_LIN2–=

INLCM2 INLCMH2 INLCMH2 INLCML2=

INLCML2 otherwise=


MCP6N16

1.5.3 DIFFERENTIAL GAIN ERROR AND NONLINEARITY

The differential errors are extracted from differentialgain measurements (see Section 1.4.2 “DifferentialGain Test Circuit”), based on Equation 1-2. Theseerrors are the differential gain error (gE) and the inputoffset error (VE, which changes nonlinearly with VDM):

EQUATION 1-8:

These errors are adjusted for the expected output, thenreferred back to the input, giving the differential inputerror (VED) as a function of VDM:

EQUATION 1-9:

Figure 1-10 shows VED vs. VDM, as well as a linear fitline (VED_LIN) based on VED and gE. The INA is instandard conditions (∆VOUT = 0, etc.). VDM is sweptfrom VDML to VDMH.

FIGURE 1-10: Differential Input Error vs. Differential Input Voltage.

Based on the measured VED data, we obtain thefollowing linear fit:

EQUATION 1-10:

Note that the VE value measured here is not asaccurate as the one obtained in Section 1.5.1 “InputOffset Related Errors”.

The remaining error (∆VED) is described by theDifferential Nonlinearity spec:

EQUATION 1-11:

GDM 1 RF RG+=

VM GDM 1 gE+ VDM V+E

=

VED VM GDM VDM–=

V1

V3

VED, VED_LIN (V)

VDM (V)

VDML VDMH0

V2

VED_LIN

VED

VED

Where:VED_LIN 1 gE+ VE gEVDM+=

gE V3 V1– VDMH VDML– 1–=

VE V2 1 gE+ =

Where:

INLDMH max VED VDMH VDML– =

VED VED VED_LIN–=

INLDML min VED VDMH VDML– =INLDM INLDMH INLDMH INLDML=

INLDML otherwise=


MCP6N16

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.

2.1 DC Precision

FIGURE 2-1: Input Offset Voltage, with GMIN = 1.



FIGURE 2-4: Input Offset Voltage Drift, with GMIN = 1.



Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

30%

s

GMIN = 128 Samples

25%

renc

es

28 SamplesTA = +25°CNPBW = 3 mHz

20%

Occ

urr

V = 1 8V

10%

15%

age

of O VDD = 1.8V

VDD = 5.5V

5%

10%

erce

nta

0%

5%Pe

0%-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12

Input Offset Voltage (µV)

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0

Perc

enta

ge o

f Occ

urre

nces


GMIN = 1028 SamplesTA = +25°CNPBW = 3 mHz

VDD = 5.5VVDD = 1.8V

0%

10%

20%

30%

40%

50%

60%

-1.0 -0.6 -0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0

Perc

enta

ge o

f Occ

urre

nces


GMIN = 10028 SamplesTA = +25°CNPBW = 3 mHz


35%

40%

s

GMIN = 128 Samples

30%

35%

renc

es

28 SamplesTA = -40 to +125°CNPBW = 3 mHz

25%

Occ

urr

VDD = 1.8VV = 5 5V

15%

20%

age

of O VDD = 5.5V

10%

%

erce

nta

0%

5%Pe

0%-600 -400 -200 0 200 400 600

Input Offset Voltage Drift; TC1 (nV/°C)

35%

40%

s

GMIN = 1028 Samples

30%

35%

renc

es


25%

Occ

urr

VDD = 5.5VV = 1 8V

15%

20%

age

of O VDD = 1.8V

10%

%

erce

nta

0%

5%Pe

0%-40 -30 -20 -10 0 10 20 30 40


35%

40%

s

GMIN = 10028 Samples

30%

35%

renc

es


25%

Occ

urr

15%

20%

age

of O


10%

%

erce

nta

0%

5%Pe

0%-16 -12 -8 -4 0 4 8 12 16



MCP6N16


FIGURE 2-7: Quadratic Input Offset Voltage Drift, with GMIN = 1.



FIGURE 2-10: Input Offset Voltage vs. Output Voltage, with GMIN = 1.



50%55%

es

GMIN = 128 Samples

40%45%

rren

ce


30%35%

f Occ

u

VDD = 1.8VV = 5 5V

20%25%

tage

of VDD = 5.5V

10%15%

Perc

ent

0%5%

1200 800 400 0 400 800 1200

P

-1200 -800 -400 0 400 800 1200Quadratic Input Offset Voltage Drift;

TC2 (pV/°C2)

30%

es

GMIN = 1028 Samples

20%

25%

rren

ce


15%

20%

f Occ

u

VDD = 1.8V

10%

15%

tage

of VDD 1.8V

VDD = 5.5V

5%

Perc

ent

0%160 120 80 40 0 40 80 120 160

P

-160 -120 -80 -40 0 40 80 120 160Quadratic Input Offset Voltage Drift;

TC2 (pV/°C2)

40%

45%

es

GMIN = 10028 Samples

30%

35%

40%

rren

ce

pTA = -40 to +125°CNPBW = 3 mHz

25%

30%

f Occ

u


15%

20%

tage

of

5%

10%

Perc

ent

0%

5%

120 100 80 60 40 20 0 20 40

P

-120 -100 -80 -60 -40 -20 0 20 40Quadratic Input Offset Voltage Drift;

TC2 (pV/°C2)

2530

Representative PartGMIN = 1

1520

e (µ

V)

GMIN 1NPBW = 2 Hz

510

Volta

ge

-50

Offs

etV

20-15-10

nput

O

VDD = 1.8V VDD = 5.5V

30-25-20In

-300.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

2530


1520

e (µ

V)

GMIN 10NPBW = 2 Hz

510

Volta

ge

-50

Offs

etV

VDD = 1.8V VDD = 5.5V

20-15-10

nput

O

30-25-20In

-300.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

2530


1520

e (µ

V)

GMIN 100NPBW = 2 Hz

510

Volta

ge

-50

Offs

etV

VDD = 1.8V VDD = 5.5V

20-15-10

nput

O

30-25-20In

-300.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)


MCP6N16


FIGURE 2-13: Input Offset Voltage vs. Power Supply Voltage, with VCM = 0V and GMIN = 1.



FIGURE 2-16: Input Offset Voltage vs. Power Supply Voltage, with VCM = VDD and GMIN = 1.



-100

1020304050

Offs

et V

olta

ge (µ

V)

Representative PartVCM = VSSGMIN = 1NPBW = 2 Hz

-50-40-30-20

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Inpu

tO

Power Supply Voltage (V)

+125°C+85°C+25°C-40°C

2530

Representative PartVCM = VSS

1520

e (µ

V)

CM SSGMIN = 10NPBW = 2 Hz

510

Volta

ge

10-50

Offs

etV

20-15-10

nput

O

+125°C+85°C

30-25-20I 85 C

+25°C-40°C

-300.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5


2530

Representative PartVCM = VSS

1520

e (µ

V)

CM SSGMIN = 100NPBW = 2 Hz

510

Volta

ge

10-50

Offs

etV

20-15-10

nput

O

+125°C+85°C

30-25-20I 85 C

+25°C-40°C

-300.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5


4050

Representative PartVCM = VDD

2030

e (µ

V)

CM DDGMIN = 1NPBW = 2 Hz

1020

Volta

ge

-100

Offs

etV

-30-20

nput

O

+125°C+85°C

50-40

I +85°C+25°C-40°C

-500.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5


2530


1520

e (µ

V)


510

Volta

ge

10-50

Offs

etV

20-15-10

nput

O

+125°C

30-25-20I +85°C

+25°C-40°C

-300.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5


2530


1520

e (µ

V)


510

Volta

ge

10-50

Offs

etV

20-15-10

nput

O

+125°C+85°C

30-25-20I +85°C

+25°C-40°C

-300.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5



MCP6N16


FIGURE 2-19: Input Offset Voltage vs. Common Mode Voltage, with VDD = 1.8V and GMIN = 1.






-100

1020304050

Offs

et V

olta

ge (µ

V)

Representative PartVDD = 1.8VGMIN = 1NPBW = 2 Hz

-50-40-30-20

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

Inpu

tO

Input Common Mode Voltage (V)

+125°C+85°C+25°C-40°C

4050

Representative PartVDD = 1.8V

2030

e (µ

V)

DD 8GMIN = 10NPBW = 2 Hz

1020

Volta

ge

-100

Offs

etV

-30-20

nput

O

+125°C+85°C

50-40

I +85 C+25°C-40°C

-50-0.5 0.0 0.5 1.0 1.5 2.0 2.5


4050


2030

e (µ

V)

DD 8GMIN = 100NPBW = 2 Hz

1020

Volta

ge

-100

Offs

etV

-30-20

nput

O

+125°C+85°C

50-40

I +85 C+25°C-40°C

-50-0.5 0.0 0.5 1.0 1.5 2.0 2.5


4050


2030

e (µ

V)

DDGMIN = 1NPBW = 2 Hz

1020

Volta

ge

-100

Offs

etV

-30-20

nput

O

+125°C+85°C

50-40

I 85 C+25°C-40°C

-50-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0


4050


2030

e (µ

V)


1020

Volta

ge

-100

Offs

etV

-30-20

nput

O

+125°C+85°C

50-40

I +85 C+25°C-40°C

-50-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0


4050


2030

e (µ

V)


1020

Volta

ge

-100

Offs

etV

-30-20

nput

O

+125°C+85°C

50-40

I 85 C+25°C-40°C

-50-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0



MCP6N16


FIGURE 2-25: Input Offset Voltage vs. Reference Voltage, with GMIN = 1.



FIGURE 2-28: CMRR, with GMIN = 1.



-30-25-20-15-10

-505

1015202530

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Inpu

t Offs

et V

olta

ge (µ

V)

Reference Voltage (V)

Representative PartGMIN = 1TA = +25°CNPBW = 2 Hz

VDD = 1.8V VDD = 5.5V

-30-25-20-15-10

-505

1015202530

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Inpu

t Offs

et V

olta

ge (µ

V)



VDD = 1.8V VDD = 5.5V

-30-25-20-15-10

-505

1015202530

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Inpu

t Offs

et V

olta

ge (µ

V)



VDD = 1.8V VDD = 5.5V

0%5%

10%15%20%25%30%35%40%45%50%55%60%

-12 -8 -4 0 4 8 12

Perc

enta

ge o

f Occ

urre

nces

1/CMRR (µV/V)

410 SamplesTA = +25°CGMIN = 1NPBW = 2.5 Hz

VDD = 5.5V

VDD = 1.8V

0%5%

10%15%20%25%30%35%40%45%50%

-5 -4 -3 -2 -1 0 1 2 3 4 5

Perc

enta

ge o

f Occ

urre

nces

1/CMRR (µV/V)


VDD = 5.5V

VDD = 1.8V

0%5%

10%15%20%25%30%35%40%45%50%55%60%65%70%

-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0

Perc

enta

ge o

f Occ

urre

nces

1/CMRR (µV/V)


VDD = 5.5V

VDD = 1.8V


MCP6N16


FIGURE 2-31: CMRR2, with GMIN = 1.



FIGURE 2-34: PSRR, with GMIN = 1.



0%5%

10%15%20%25%30%35%40%45%50%55%

-10 -8 -6 -4 -2 0 2 4 6 8 10

Perc

enta

ge o

f Occ

urre

nces

1/CMRR2 (µV/V)


VDD = 5.5V

VDD = 1.8V

50%55%

310 SamplesTA = +25°C

40%45%

renc

es

TA = +25 CGMIN = 10NPBW = 2.5 Hz

30%35%

%

Occ

urr

20%25%30%

age

of O VDD = 5.5V

10%15%20%

erce

nta

0%5%

10%

Pe VDD = 1.8V

0%-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8

1/CMRR2 (µV/V)

80%

90%410 SamplesTA = +25°C

70%

80%

renc

es

TA = +25 CGMIN = 100NPBW = 2.5 Hz

50%

60%

Occ

urr

40%

age

of O VDD = 5.5V

20%

30%

erce

nta

V 1 8V

0%

10%Pe VDD = 1.8V

0%-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8

1/CMRR2 (µV/V)

18%20%


14%16%18%

renc

es

TA +25 CVDD = 1.8V to 5.5VGMIN = 1NPBW = 2.5 Hz

12%14%

Occ

urr NPBW 2.5 Hz

8%10%

age

of O

4%6%

erce

nta

0%2%%

Pe

0%-5 -4 -3 -2 -1 0 1 2 3 4 5

1/PSRR (µV/V)

18%20%


14%16%18%

renc

es


12%14%

Occ

urr NPBW 2.5 Hz

8%10%

age

of O

4%6%

erce

nta

0%2%%

Pe

0%-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

1/PSRR (µV/V)

20%22%


16%18%

renc

es


12%14%

Occ

urr NPBW 2.5 Hz

8%10%12%

age

of O

4%6%8%

erce

nta

0%2%4%

Pe

0%0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

1/PSRR (µV/V)


MCP6N16


FIGURE 2-37: DC Open-Loop Gain, with GMIN = 1.



FIGURE 2-40: CMRR vs. Ambient Temperature.

FIGURE 2-41: CMRR2 vs. Ambient Temperature.

FIGURE 2-42: PSRR vs. Ambient Temperature.

0%5%

10%15%20%25%30%35%40%45%50%55%

-10 -8 -6 -4 -2 0 2 4 6 8 10

Perc

enta

ge o

f Occ

urre

nces

1/AOL (µV/V)


VDD = 5.5V

VDD = 1.8V

50%55%


40%45%

renc

es

TA = +25 CGMIN = 10NPBW = 2.5 Hz

30%35%

%

Occ

urr

20%25%30%

age

of O VDD = 5.5V

10%15%20%

erce

nta

0%5%

10%

Pe VDD = 1.8V

0%-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8

1/AOL (µV/V)

80%

90%410 SamplesTA = +25°C

70%

80%

renc

es

TA = +25 CGMIN = 100NPBW = 2.5 Hz

50%

60%

Occ

urr

40%

age

of O VDD = 5.5V

20%

30%

erce

nta

V 1 8V

0%

10%Pe VDD = 1.8V

0%-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8

1/AOL (µV/V)

145150

GMIN = 100, VDD = 5.5VVDD = 1.8V

135140

DD 8

125130

(dB

)

110115120

CM

RR

100105110C

9095

100GMIN = 10, VDD = 5.5V

VDD = 1.8VGMIN = 1, VDD = 5.5V

VDD = 1.8V90

-50 -25 0 25 50 75 100 125Ambient Temperature (°C)

145150

135140

125130

2 (d

B)

110115120

CM

RR

2

100105110C

GMIN = 100, VDD = 5.5VVDD = 1.8V

9095

100GMIN = 10, VDD = 5.5V

VDD = 1.8VGMIN = 1, VDD = 5.5V

VDD = 1.8V90


145150

GMIN = 100

135140

MIN

125130

(dB

) GMIN = 10

110115120

PSR

R

GMIN = 1

100105110

9095

100VDD = 1.8V to 5.5V

90-50 -25 0 25 50 75 100 125



MCP6N16


FIGURE 2-43: DC Open-Loop Gain vs. Ambient Temperature.

FIGURE 2-44: Input Bias and Offset Currents vs. Common Mode Input Voltage, with TA = +85°C.

FIGURE 2-45: Input Bias and Offset Currents vs. Common Mode Input Voltage, with TA = +125°C.

FIGURE 2-46: Input Bias and Offset Currents vs. Ambient Temperature, with VDD = 5.5V.

FIGURE 2-47: Input Bias Current Magnitude vs. Input Voltage (below VSS).

FIGURE 2-48: Gain Error vs. Ambient Temperature.

9095

100105110115120125130135140145150

-50 -25 0 25 50 75 100 125

DC

Ope

n-Lo

op G

ain;

AO

L(d

B)


GMIN = 10, VDD = 5.5VVDD = 1.8V

GMIN = 1, VDD = 5.5VVDD = 1.8V

GMIN = 100, VDD = 5.5VVDD = 1.8V

500600

A) Representative Part

TA = +85°C

300400

ents

(pA TA 85 C

VDD = 5.5V

100200

t Cur

re

-1000

Offs

et IB

400-300-200

t Bia

s,

600-500-400

Inpu IOS

-6000.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Common Mode Input Voltage (V)

8001,000

A) Representative Part

TA = +125°C

400600

ents

(pA TA 125 C

VDD = 5.5V

200400

t Cur

re IB

-2000

Offs

et

-600-400

t Bia

s,

IOS

1 000-800600

Inpu

-1,0000.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0


1000

A)

ents

(pA

| IOS |

100

t Cur

re

10

Offs

et

10

t Bia

s, IB

1

Inpu

125 45 65 85 105 125


1.E-11

1.E-10

1.E-9

1.E-8

1.E-7

1.E-6

1.E-5

1.E-4

1.E-3

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Inpu

t Bia

s C

urre

nt M

agni

tude

(A)

Input Voltage (V)

-40°C+25°C+85°C

+125°C

1m

10p

100µ

10µ

1µ

100n

10n

1n

100p

0.080.10

GMIN = 100;VDD = 1.8V

Representative Parts

0 040.06

VDD 1.8VVDD = 5.5V

0.020.04

ror (

%)

-0.020.00

ain

Err

-0.06-0.04G

a

0 10-0.080.06

GMIN = 1;VDD = 1.8VVDD = 5.5V

GMIN = 10;VDD = 1.8VVDD = 5.5V

-0.10-50 -25 0 25 50 75 100 125



MCP6N16


FIGURE 2-49: Gain Error, with GMIN = 1.



14%

16%es

405 SamplesGMIN = 1

12%

14%

rren

ce

MIN

VDD = 1.8V VDD = 5.5V

8%

10%

f Occ

u

6%

8%

tage

of

2%

4%

Perc

ent

0%

2%

4 2 0 8 6 4 2 0 2 4 6 8 0 2 4

P

-0.1

4-0

.1-0

.1-0

.0-0

.0-0

.04

-0.0 0.0

0.02

0.04

0.0

0.0

0.1

0.12

0.14

Gain Error (%)

16%

18%

es

306 SamplesGMIN = 10

12%

14%

rren

ce

MIN

10%

12%

f Occ

u

6%

8%

tage

of

2%

4%

Perc

ent

VDD = 1.8V VDD = 5.5V

0%

2%

4 2 0 8 6 4 2 0 2 4 6 8 0 2 4

P

-0.1

4-0

.1-0

.1-0

.0-0

.0-0

.04

-0.0 0.0

0.0

0.04

0.0

0.0

0.1

0.1

0.14

Gain Error (%)

16%

18%

es

386 SamplesGMIN = 100

12%

14%

rren

ce

MIN

10%

12%

f Occ

u

6%

8%

tage

of

2%

4%

Perc

ent

VDD = 1.8V VDD = 5.5V

0%

2%

4 2 0 8 6 4 2 0 2 4 6 8 0 2 4

P

-0.1

4-0

.1-0

.1-0

.0-0

.0-0

.04

-0.0 0.0

0.02

0.04

0.0

0.0

0.1

0.12

0.14

Gain Error (%)


MCP6N16


2.2 Other DC Voltages and Currents

FIGURE 2-52: Input Voltage Range Headroom vs. Ambient Temperature.

FIGURE 2-53: Normalized Differential Input Voltage Range vs. Ambient Temperature.

FIGURE 2-54: Output Voltage Headroom vs. Output Current Magnitude.

FIGURE 2-55: Output Voltage Headroom vs. Ambient Temperature.

FIGURE 2-56: Supply Current vs. Power Supply Voltage.

FIGURE 2-57: Supply Current vs. Common Mode Input Voltage.

0 3

0.4

om

1st Wafer Lot

0.2

0.3

eadr

oo VIVH – VDD

0.1

nge

He

)

-0.1

0.0

age

Ran (V)

-0.2

ut V

olta VIVL – VSS

0 4

-0.3Inpu

-0.4-50 -25 0 25 50 75 100 125


4.04.2

ut )

1st Wafer LotGMINVDMH = -GMINVDML

3 63.8

al In

puV D

MH

(V) GMINVDMH GMINVDML

RTO

3.43.6

fere

ntia

; GM

INV

GMIN = 1, 10, 100

3.03.2

ed D

iffR

ange

; MIN , ,

2.62.8

rmal

ize

olta

geR

2 22.4N

o Vo

2.2-50 -25 0 25 50 75 100 125


100V) 100

om (m

V

VDD = 1.8V

Hea

droo

VDD – VOH VDD = 5.5V

10

ltage

Hpu

t Vol

VOL – VSS

1

Out

p

10.1 1 10

Output Current Magnitude (mA)

90100

V)

VDD = 5.5VRL = 1 k

7080

om (m

V

VDD – VOH

L

6070

Hea

droo

4050

ltage

H

VOL – VSS

2030

put V

ol

010O

utp

0-50 -25 0 25 50 75 100 125


1.11.2

0.91.0

mA

)+125°C

0.70.8

rent

(m+125°C+85°C+25°C40°C

0.50.6

ly C

urr -40 C

0 20.30.4

Supp

0 00.10.2

0.00.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5


1.11.2

0.91.0

mA

) VDD = 1.8VVDD = 5.5V

0.70.8

rent

(m

0 40.50.6

ply

Cur

0 20.30.4

Supp

0 00.10.2

0.0-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0



MCP6N16


FIGURE 2-58: Output Short-Circuit Current vs. Power Supply Voltage.

FIGURE 2-59: Power-On Reset Trip Voltages.

FIGURE 2-60: Power-On Reset Trip Voltages vs. Temperature.

4050

mA

)

203040

rren

t (m

1020

uit C

ur

+125°C+85°C

-100

rt-C

ircu +85 C

+25°C-40°C

-30-20

ut S

hor

50-4030

Out

pu

-500.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5


15%20%25%30%35%40%45%50%

tage

of O

ccur

renc

es

VPRHVPRL

103 Samples1 Wafer LotTA = +25°C

0%5%

10%15%

1.20

1.22

1.24

1.26

1.28

1.30

1.32

1.34

1.36

1.38

1.40

Perc

ent

Power-On Reset Trip Voltages (V)

1 501.551.60

(V) 1 Wafer Lot

1.401.451.50

ltage

s

V

1.301.351.40

Trip

Vo VPRH

1 151.201.25

Res

etT

VPRL

1.051.101.15

er-O

nR

0 900.951.00

Pow

e

0.90-50 -25 0 25 50 75 100 125



MCP6N16


2.3 Frequency Response

FIGURE 2-61: CMRR vs. Frequency.

FIGURE 2-62: PSRR vs. Frequency.

FIGURE 2-63: Open-Loop Gain vs. Frequency.

FIGURE 2-64: Normalized Gain-Bandwidth Product vs. Ambient Temperature.

FIGURE 2-65: Phase Margin vs. Ambient Temperature.

FIGURE 2-66: Closed-Loop Output Impedance vs. Frequency.

120130

100110

8090

(dB

)

06070

CM

RR

304050C

G 100

102030 GMIN = 100

GMIN = 10GMIN = 1

101.E+04 1.E+05 1.E+06

Frequency (Hz)10k 100k 1M

110120

90100

7080

(dB

)

405060

PSR

R

203040

G 100

01020 GMIN = 100

GMIN = 10GMIN = 1

01.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)1k 10k 100k 1M

240

-210

-180

-150

-120

-90

-60

0

20

40

60

80

100

120

p G

ain

Phas

e;

AO

L(°

)

op G

ain

Mag

nitu

de;

|AO

L| (d

B)

AOL;GMIN = 100

-330

-300

-270

-240

-60

-40

-20

0

1.E+3 1.E+4 1.E+5 1.E+6 1.E+7

Ope

n-Lo

op

Ope

n-Lo

o

Frequency (Hz)

GMIN = 10GMIN = 1

|AOL|;GMIN = 100GMIN = 10GMIN = 1

1k 10k 100k 1M 10M

500

h

VDD = 5.5V

450

dwid

thN

(kH

z)

400

in B

and

WP/

GM

IN

300

350

zed

Gai

t; G

BW

250

300

orm

aliz

rodu

ct

G 1

200

250No Pr GMIN = 1

GMIN = 10GMIN = 100 VDD = 1.8V

200-50 -25 0 25 50 75 100 125


85VDD = 5.5V

80°)

75

argi

n (°

65

70

ase

Ma

60

65

Pha

G = 1

55

60 GMIN = 1GMIN = 10GMIN = 100VDD = 1.8V

55-50 -25 0 25 50 75 100 125


1.E+3

1.E+4

ed-L

oop

Out

put

mpe

danc

e (

)

10k

1k

GMIN = 1, 10, 100

1.E+1

1.E+2

1.E+3 1.E+4 1.E+5 1.E+6

Clo

se Im

Frequency (Hz)

100

10

GDM/GMIN = 1GDM/GMIN = 10GDM/GMIN = 100

1k 10k 100k 1M


MCP6N16


FIGURE 2-67: Gain Peaking vs. Normalized Capacitive Load.

FIGURE 2-68: EMIRR vs. Frequency, with VIN = 100 mVPK.

FIGURE 2-69: EMIRR vs. Input Voltage, with f = 400 MHz.




910

78

B)

GMIN = 1

67

ing

(dB

G = 10

GMIN = 1GDM = 1

45

n Pe

ak

GMIN = 100G = 100

GMIN = 10GDM = 10

= 20= 50

23G

ain GDM = 100

= 200= 500

= 50

012

010 100 1,000

Normalized Capacitive Load; CL GMIN/GDM (pF)

130

140VIN = 100 mVPK, at VIP or VREFVDD = 5.5V

120

130 DD 5 5

100

110

R (d

B)

80

90

EMIR

R

GMIN = 1G 10

70

80E GMIN = 10GMIN = 100

50

60

501.E+07 1.E+08 1.E+09 1.E+10

Frequency (Hz)10M 100M 1G 10G

130

140f = 400 MHzVDD = 5.5V

120

130 DD

at VREF

100

110

R (d

B)

80

90

EMIR

R

70

80E

GMIN = 1GMIN = 10G = 100

at VIP

50

60GMIN = 100

500.01 0.1 1

Input Voltage (VPK)2

130

140f = 900 MHzVDD = 5.5V

120

130 DD

at VIP

100

110

R (d

B)

IP

80

90

EMIR

R

70

80E

GMIN = 1GMIN = 10G = 100

at VREF

50

60GMIN = 100

500.01 0.1 1


130

140f = 1800 MHzVDD = 5.5V

120

130 DD

at VREF

100

110

R (d

B)

REF

80

90EM

IRR

70

80E

GMIN = 1GMIN = 10G = 100

at VIP

50

60GMIN = 100

500.01 0.1 1


130

140f = 2400 MHzVDD = 5.5V

120

130 DD

at VREF

100

110

R (d

B)

80

90

EMIR

R

t V

70

80E

GMIN = 1G = 10

at VIP

50

60GMIN = 10GMIN = 100

500.01 0.1 1



MCP6N16


2.4 Noise

FIGURE 2-73: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency.

FIGURE 2-74: Input Noise Voltage Density vs. Input Common Mode Voltage.

FIGURE 2-75: Intermodulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-8).

FIGURE 2-76: Intermodulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-8).

FIGURE 2-77: Input Noise Voltage vs. Time, with 1 Hz and 10 Hz Filters and GMIN = 1.


1.E+5

1.E+6

1.E+3

1.E+4

d In

put N

oise

Vol

tage

(VP-

P)

ise

Volta

ge D

ensi

ty(V

/H

z)

eni;GMIN = 1GMIN = 10GMIN = 100

1µ

20µ

1m

20m10µ 10mEni(0 Hz to f);

GMIN = 1GMIN = 10GMIN = 100

1.E+3

1.E+4

1.E+1

1.E+2

1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5In

tegr

ated

Inpu

t No

Frequency (Hz)0.1 1 10 100 1k 10k 100k

100n

10n

100µ

10µ

1E+3

y

1µ

Den

sity

G = 1f = 100 Hz

ltage

DH

z)


1E+2

ise

Vol

(V/

H 100n

put N

o

1E+1

Inp

10n1E+1-0.50.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0


10n

1

10

100

ectr

um, R

TI (µ

V PK) Residual

100 HzTone

60 HzHarmonics

VCM tone = 100 mVPK, f = 100 Hz

IMDToneat DC GMIN = 1

GMIN = 10

0.1

1

1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5

IMD

Spe

Frequency (Hz)

MIN

GMIN = 100

1 10 100 1k 100k10k

100

R id l

VDD tone = 100 mVPK, f = 100 Hz

(µV P

K) Residual

100 HzTone

IMDToneat DC GMIN = 1

10

m, R

TI (

1ectr

um

GMIN = 101

MD

Spe MIN

0 1

IM

GMIN = 1000.1

1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5Frequency (Hz)

1 10 100 1k 100k10k

oise

Vol

tage

; eni

(t)(5

µV/

div)

GMIN = 1

NPBW = 10 Hz

0 20 40 60 80 100 120 140 160 180 200

Inpu

t No

Time (s)

NPBW = 1 Hz

GMIN = 10

; eni

(t)Vo

ltage

;V/

div)

oise

Vo(0

.5 µ

V

NPBW = 10 Hz

nput

N NPBW = 10 Hz

In

NPBW = 1 Hz

0 20 40 60 80 100 120 140 160 180 200Time (s)


MCP6N16



GMIN = 100

e ni(t

)lta

ge;e

div)

ise

Vol

0.2

µV/d

put N

o ( 0 NPBW = 10 Hz

Inp

NPBW = 1 Hz

0 20 40 60 80 100 120 140 160 180 200Time (s)


MCP6N16


2.5 Time Response

FIGURE 2-80: Input Offset Voltage vs. Time with Temperature Change.

FIGURE 2-81: Input Offset Voltage vs. Time at Power-Up.

FIGURE 2-82: The MCP6N16 Shows No Phase Reversal vs. Common Mode Input Overdrive, with VDD = 5.5V.

FIGURE 2-83: The MCP6N16 Shows No Phase Reversal vs. Differential Input Overdrive, with VDD = 5.5V.

FIGURE 2-84: The MCP6N16 Shows No Phase Reversal vs. Output Overdrive to VSS.

FIGURE 2-85: The MCP6N16 Shows No Phase Reversal vs. Output Overdrive to VDD.

100125

90100

NPBW = 1.3 Hz

5075

7080

e (°

C)

e (µ

V)

025

5060

erat

ure

Volta

ge GMIN = 1GMIN = 10GMIN = 100

TSEN

-50-25

3040

rTem

pe

Offs

etV MIN

125-100-75

01020

Sens

or

nput

O

VOS

175-150-125

20-10

0 SIn

-175-200 20 40 60 80 100 120 140 160 180

Time (s)

150

200

25

30GDM = 1000

100

150

20

25

e (µ

V)

ge (V

)

GMIN = 1GMIN = 10G 100

50

100

15

20

Volta

ge

y Vo

ltag GMIN = 100

010

Offs

etV

Supp

ly VOS

-505

nput

O

Pow

erS

150

-100

5

0 IP

VDD

-150-50.0 0.5 1.0 1.5 2.0 2.5 3.0

Time (ms)

2.7

2.8

2.9

3.0

3.1

3.2

2

3

4

5

6

7

put V

olta

ge (V

)

Mod

e In

put V

olta

ge (V

) VDD = 5.5V

VCM

2.4

2.5

2.6

2.7

-1

0

1

2

0 1 2 3 4 5 6 7 8 9 10

Out

p

Com

mon

M

Time (ms)

VOUT;GMIN = 1GMIN = 10GMIN = 100

6

7

4

5

e

VDD = 5.5V

5

6

3

4

V)al M

ode

DM

(V) VDM

42

ltage

(V

eren

tia G

DMV D

2

3

0

1

put V

ol

ed D

iffe

olta

ge;

1

2

-1

0

Out

p

rmal

ize

nput

Vo

VOUT;G = 1

1

0

3

-2Nor In GMIN = 1

GMIN = 10GMIN = 100

-1-30 1 2 3 4 5 6 7 8 9 10

Time (ms)

2.02.2

0.00.2

1.61.8

-0.4-0.2

V)ntia

lD

M(V

) GDMVDM

1 21.4

-0 8-0.6

ltage

(V

Diff

eren

GD

MV D VOUT;

GMIN = 1GMIN = 10

0 81.01.2

-1 2-1.00.8

put V

ol

aliz

edD

olta

ge; GMIN = 100

0 40.60.8

1 6-1.4-1.2

Out

p

Nor

ma

nput

Vo

0 00.20.4

2 0-1.8-1.6N In

0.0-2.00 1 2 3 4 5 6 7 8 9 10

Time (ms)

5.35.5

1.82.0

4.95.1

1.41.6

V)ntia

lD

M(V

)

4.54.7

1.01.2

ltage

(V

Diff

ere

; GD

MV D

4 14.34.5

0 60.81.0

put V

o

aliz

edD

olta

ge; VOUT;


3 73.94.1

0 20.40.6

Out

p

Nor

ma

nput

Vo

G V

GMIN = 100

3 33.53.7

0 20.00.2In GDMVDM

3.3-0.20 1 2 3 4 5 6 7 8 9 10

Time (ms)


MCP6N16


FIGURE 2-86: Small Signal Step Response.

FIGURE 2-87: Large Signal Step Response.

FIGURE 2-88: Differential Input Overdrive Recovery vs. Time.

FIGURE 2-89: Differential Input Overdrive Recovery Time vs. Normalized Gain.

FIGURE 2-90: Output Overdrive Recovery vs. Time.

FIGURE 2-91: Output Overdrive Recovery Time vs. Normalized Gain.

V/di

v)e

(10

m


Volta

ge GMIN = 100

utpu

tVO

u

0 5 10 15 20 25 30 35 40 45 50Time (µs)

5.05.5

4.04.5

V)

3.03.5

ltage

(V

GMIN = 1GMIN = 10

2 02.53.0

put V

ol GMIN = 100

1 01.52.0

Out

p

0 00.51.0

0.00 5 10 15 20 25 30 35 40 45 50

Time (µs)

2 02.53.03.54.04.55.05.5

put V

olta

ge (V

)


VDD = 5.5V

0.00.51.01.52.0

0 50 100 150 200 250

Out

p

Time (µs)

1

10

100

1000

1 10

Diff

eren

tial I

nput

Ove

rdriv

eR

ecov

ery

Tim

e (µ

s)

Normalized Gain; GDM/GMIN


VDD = 5.5V

5.05.5

4.04.5

V)3.03.5

ltage

(VGMIN = 1

2 02.53.0

put V

ol MINGMIN = 10GMIN = 100

1 01.52.0

Out

p

0 00.51.0

0.00 50 100 150 200 250 300 350 400 450 500 550 600

Time (µs)

100

1000

1 10

Out

put O

verd

rive

Rec

over

yTi

me

(µs)

Normalized Gain; GDM/GMIN


VDD = 5.5VRecovery from VSS and VDD


MCP6N16


FIGURE 2-92: Power Supply On and Off and Output Voltage vs. Time.

1.82.0

(V) VL = 0V

1.41.6

olta

ge

G = 1

1.01.2

utpu

t Vo GMIN = 1

GMIN = 10GMIN = 100

0 60.81.0

ply,

Ou

VDD

On

0 20.40.6

er S

upp VDD

VOUT

0 20.00.2

Pow

e

Off Off-0.2

0 20 40 60 80 100 120 140 160 180 200Time (ms)


MCP6N16


2.6 Enable Response

FIGURE 2-93: Enable and Output Voltages vs. Time, with VDD = 1.8V.

FIGURE 2-94: Enable and Output Voltages vs. Time, with VDD = 5.5V.

FIGURE 2-95: Normalized Enable Input Trip and Hysteresis Voltages vs. Ambient Temperature.

FIGURE 2-96: Enable Turn-On Time vs. Ambient Temperature.

FIGURE 2-97: Power Supply Current in Shutdown vs. Power Supply Voltage.

FIGURE 2-98: Output Leakage Current in Shutdown vs. Output Voltage.

1.82.0

)

VDD = 1.8VVL = 0V

1.41.6

ges

(V)

INAturns on

INAturns off

L

1.01.2

t Vol

tag

EN VOUT

turns on turns off

0.60.8

Out

put

GMIN = 100

0 20.40.6

nabl

e,O MIN

GMIN = 10GMIN = 1

0 20.00.2

En

-0.20 20 40 60 80 100 120 140 160 180 200

Time (µs)

5.56.0

)

VDD = 5.5VVL = 0V

4 04.55.0

ges

(V)

INA INA

L

3.03.54.0

t Vol

tag

turns on turns off

2.02.53.0

Out

put

ENVOUT

1.01.5

nabl

e,O

GMIN = 1GMIN = 10

0 50.00.5En

GMIN 10GMIN = 100

-0.50 20 40 60 80 100 120 140 160 180 200

Time (µs)

0 6

0.7

V/V) VDD = 1.8VVIH_TRIP/VDD

0 5

0.6

Inpu

tag

es (V

0.4

0.5

nabl

eis

Vol

ta

VIL_TRIP/VDD

0.3

lized

Est

eres

i

VHYST/VDD

0.2

Nor

mal

and

Hys

0 0

0.1NTr

ip a

VDD = 5.5V0.0


05

101520253035404550

-50 -25 0 25 50 75 100 125

Enab

le T

urn-

On

Tim

e (µ

s)



VDD = 1.8V

VDD = 5.5V


2.02.5

EN = 0V

1 01.5

rent

A)

0.51.0

ply

Cur

own

(µA

-40°C+25°C

IDD

-0.50.0

r Sup

pSh

utdo

+25 C+85°C

+125°CI

-1.5-1.0

Pow

erIn

S ISS

2 5-2.0-2.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0Power Supply Voltage (V)

1.E-7

)

EN = 0VVDD = 5.5V

100n

1.E-8

ent (

A) DD

+125°C10n

1.E-9

e C

urre

+85°C1n

1.E-10

Leak

age

100p

1.E-11utpu

tL

10p

1 E 12

Ou

+25°C

1p

p

1.E-120.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Output Voltage (V)

1p


MCP6N16

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

3.1 Digital Enable Input (EN)

This input (EN) is a CMOS, Schmitt-triggered input.When it is low, it puts the part in a low-power state.When high, the part operates normally. The EN pinmust not be left floating.

3.2 Analog Signal Inputs (VIP, VIM)

The non-inverting and inverting inputs (VIP and VIM) arehigh-impedance CMOS inputs with low bias currents.

3.3 Power Supply Pins (VSS, VDD)

The positive power supply (VDD) is 1.8V to 5.5V higherthan the negative power supply (VSS). For normaloperation, the other pins are between VSS and VDD.

Typically, these parts are used in a single (positive)supply configuration. In this case, VSS is connected toground and VDD is connected to the supply; VDD willneed bypass capacitors.

3.4 Analog Reference Input (VREF)

The analog reference input (VREF) is the non-invertinginput of the second input stage; it shifts VOUT to itsdesired range. The external gain resistor (RG) isconnected to this pin. It is a high-impedance CMOSinput with low bias current.

3.5 Analog Feedback Input (VFG)

The analog feedback input (VFG) is the inverting inputof the second input stage. The external feedbackcomponents (RF and RG) are connected to this pin. It isa high-impedance CMOS input with low bias current.

3.6 Analog Output (VOUT)

The analog output (VOUT) is a low impedance voltageoutput. It represents the differential input voltage(VDM = VIP – VIM), with gain GDM and is shifted byVREF. The external feedback resistor (RF) is connectedto this pin.

3.7 Exposed Thermal Pad (EP)

There is an internal connection between the exposedthermal pad (EP) and the VSS pin; they must beconnected to the same potential on the printed circuitboard (PCB).

This pad can be connected to a PCB ground (VSS)plane region to provide a larger heat sink. Thisimproves the package thermal resistance (θJA).

TABLE 3-1: PIN FUNCTION TABLE

MCP6N16Symbol Description

MSOP DFN

1 1 EN Enable Input

2 2 VIM Inverting Input

3 3 VIP Non-inverting Input

4 4 VSS Negative Power Supply

5 5 VREF Reference Input

6 6 VFG Feedback Input

7 7 VOUT Output

8 8 VDD Positive Power Supply

— 9 EP Exposed Thermal Pad (EP); must be connected to VSS.


MCP6N16

4.0 APPLICATIONS

The MCP6N16 instrumentation amplifier (INA) ismanufactured using Microchip’s state of the art CMOSprocess. Its low cost, low power and high speed makeit ideal for battery-powered applications.

4.1 Basic Performance

4.1.1 STANDARD CIRCUIT

Figure 4-1 shows the standard circuit configuration forthese INAs. When the inputs and output are in theirspecified ranges, the output voltage is approximately:

EQUATION 4-1:

FIGURE 4-1: Standard Circuit.

For normal operation, keep:

• VIP, VIM, VREF and VFG between VIVL and VIVH

• VIP – VIM (i.e., VDM) between VDML and VDMH

• VOUT between VOL and VOH

4.1.2 ANALOG ARCHITECTURE

Figure 4-2 shows the block diagram for these INAs,without details on chopper-stabilized operation.

FIGURE 4-2: MCP6N16 Block Diagram.

The input signal is applied to GM1. Equation 4-2 showsthe relationships between the input voltages (VIP andVIM) and the common mode and differential voltages(VCM and VDM).

EQUATION 4-2:

The negative feedback loop includes GM2, RM4, RF andRG. These blocks set the DC open-loop gain (AOL) andthe nominal differential gain (GDM):

EQUATION 4-3:

AOL is very high, so I4 is very small and I1 + I2 ≈ 0. Thismakes the differential inputs to GM1 and GM2 equal inmagnitude and opposite in polarity. Ideally, this gives:

EQUATION 4-4:

For an ideal part, changing VCM, VSS or VDD producesno change in VOUT. VREF shifts VOUT as needed.

The different GMIN options change GM1, GM2 and theinternal compensation capacitor. This results in theperformance trade-offs shown in Table 1.

4.1.3 DC ERRORS

Section 1.5 “Explanation of DC ErrorSpecifications” defines some of the DC errorspecifications. These errors are internal to the INA, andcan be summarized as follows:

EQUATION 4-5:

VOUT VREF + GDMVDM

Where:

GDM = 1 + RF / RG

VOUT

VIP

VDD

VIM

VREF

VFGRF

RG

U1

MCP6N16

VSSVDD

VIP

VIM

GM1VIP

VIM

RFVFG

VOUTVOUT

VREF

RM4

GM2

ΣI2

VREF

I4

RGI1

MCP6N16 RR

EN

VIP VCM VDM 2+=

VIM VCM VDM 2–=

VCM VIP VIM+ 2=

VDM VIP VIM–=

AOL GM2RM4=

GDM 1 RF RG+=

VFG VREF– VDM=

VOUT VDMGDM VREF+=

Where:

VOUT VREF GDM 1 gE+ VDM VED+ +=

GDM 1 gE+ VE VE+ +

Where:

PSRR, CMRR, CMRR2 and AOL are in units of V/V

∆TA is in units of °C

TC1 is in units of V/°C

VDM = 0

VE VOS

VDD VSS–PSRR

---------------------------------VCM

CMRR-----------------

VREF

CMRR2--------------------+ + +=

VOUT

AOL----------------- TA TC1+ +

VED INLDM VDMH VDML– VE INLCM VIVH VIVL–


MCP6N16

The nonlinearity specifications (INLCM and INLDM)describe errors that are nonlinear functions of VCM andVDM, respectively. They give the maximum excursionfrom linear response over the entire common modeand differential ranges.

The input bias current and offset current specifications(IB and IOS), together with a circuit’s external inputresistances, give an additional DC error. Figure 4-3shows the resistors that set the DC bias point.

FIGURE 4-3: DC Bias Resistors.

The resistors at the main input (RIP and RIM) and itsinput bias currents (IBP and IBM) give the followingchanges in the INA’s bias voltages:

EQUATION 4-6:

The change in VCM (∆VCM) can affect the input range,for large RIP or RIM. The best design results when RIPand RIM are equal and small:

EQUATION 4-7:

The resistors at the feedback input (RR, RF and RG)and its input bias currents (IBR and IBF) give thefollowing changes in the INA’s bias voltages:

EQUATION 4-8:

The change in VREF (∆VREF) can affect the input range,for large RR or RF. The best design results whenGDMRR and RF are equal (i.e., RR = RF||RG) and small:

EQUATION 4-9:

4.1.4 AC PERFORMANCE

The bandwidth of these amplifiers depends on GDMand GMIN:

EQUATION 4-10:

The bandwidth at the maximum output swing is calledthe Full Power Bandwidth (fFPBW). It is limited by theSlew Rate (SR) for many amplifiers, but is close to fBWfor these parts:

EQUATION 4-11:

VOUT

VIP

VDD

VIM

VREF

RF

RG

RIP

RIM

RR

IBP

IBM VFG

IBF

IBR

U1

MCP6N16

Where:

CMRR is in units of V/V

VIP IBPRIP– IB IOS 2+ – RIP= =

VIM IBMRIM– IB IOS 2– – RIM= =

VCM VIP VIM+ 2=

I– B RIP RIM+ 2 I– OS RIP RIM– 4=

VDM VIP VIM–=

IB– RIP RIM– IOS RIP RIM+ 2–=

VOUT GDM VDM VCM CMRR+ =

Where:

RIP = RIM

RTOL = tolerance of RIP and RIM

VOUT GDMVDM GDM 2IBRTOL IOS– RIP

VFG VREF VOUT IB2 RF GDMR

R– IOS2 RF GDMR

R+ 2+

due to high AOL

VREF IBRRR– IB2 IOS2 2+ – RR= =

IB2 meets the IB specificationIOS2 meets the IOS specificationIB2 ≠ IB, in generalIOS2 ≠ IOS, in general

Where:

GDMRR = RF

RTOL = tolerance of RR, RF and RG

VOUT 2IB2RTOL IOS2+ RF

Where:

fBW = -3 dB bandwidth

fGBWP = Gain-Bandwidth product

fBW fGBWP GDM 0.50 MHz GMIN GDM , 0.35 MHz GMIN GDM ,

GMIN = 1, 10

GMIN = 100

Where:

VO = Maximum output voltage swing

VOH – VOL

fFPBW SR VO fBW , for these parts

Where:


MCP6N16

4.1.5 NOISE PERFORMANCE

As shown in Figure 2-73, the noise density is white atlow frequencies; the 1/f noise is negligible for almost allapplications. As a result, the time domain data inFigures 2-77, 2-78 and 2-79 is well behaved.

4.2 Overview of Zero-Drift Operation

Figure 4-4 shows a simplified diagram of the MCP6N16zero-drift INAs. This diagram will be used to explainhow low voltage errors are reduced in this architecture(much better VOS, TC1 (∆VOS/∆TA), CMRR, CMRR2,PSRR, AOL and 1/f noise).

FIGURE 4-4: Simplified Zero-Drift INA Functional Diagram.

4.2.1 BUILDING BLOCKS

The Main Amplifiers (GM1 and GM2) are designed forhigh gain and bandwidth, with a differential topology.The main input pairs (+ and - pins at the top left) are forthe higher frequency portion of the input signal. Theauxiliary input pair (+ and - pins at the bottom left ofGM1) is for the low frequency portion of the input signaland corrects the INA’s input offset voltage. Both inputsare added together internally.

The Auxiliary Amplifiers (GA1 and GA2), the ChopperInput Switches and the Chopper Output Switchesprovide a high DC gain to the input signal. DC errorsare modulated to higher frequencies and white noise tolow frequencies.

The Low-Pass Filter reduces high-frequency content,including harmonics of the Chopping Clock.

The Output Buffer (RM4) converts current to voltageand drives external loads at the VOUT pin.

The Oscillator runs at fCLK = 200 kHz. Its output isdivided by 8, to produce the Chopping Clock rate offCHOP = 25 kHz.

The internal POR part starts the part in a known goodstate, protecting against power supply brown-outs. TheDigital Control block outputs clocks and POR events.

4.2.2 CHOPPING ACTION

Figure 4-5 shows the amplifier connections for the firstphase of the Chopping Clock and Figure 4-6 showsthem for the second phase. The slow voltage errorsalternate in polarity, making the average error small.

FIGURE 4-5: First Chopping Clock Phase; Simplified Diagram.

VIP

VIM GM1

VOUTRM4

GA1

ChopperInput

Switches

ChopperOutput

Switches

Oscillator

Low-PassFilter

Digital Control

VFG

VREF

GA2

ChopperInput

Switches

POR

GM2

VIP

VIM

GA1

VFG

VREF

GA2

Low-PassFilter


MCP6N16

FIGURE 4-6: Second Chopping Clock Phase; Simplified Diagram.

4.2.3 INTERMODULATION DISTORTION (IMD)

These INAs will show intermodulation distortion (IMD)products when an AC signal is present.

The signal and clock can be decomposed into sinewave tones (Fourier series components). These tonesinteract with the zero-drift circuitry’s nonlinear responseto produce IMD tones at sum and differencefrequencies. Each of the square wave clock’sharmonics has a series of IMD tones centered on it.See Figures 2-75 and 2-76.

4.3 Other Functional Blocks

4.3.1 RAIL-TO-RAIL INPUTS

Each input stage uses one PMOS differential pair at theinput. The output of each differential pair is processedusing current mode circuitry. The inputs show nocrossover distortion vs. common mode voltage.

With this topology, the inputs (VIP and VIM) operatenormally down to VSS – 0.15V and up to VDD + 0.15Vat room temperature (see Figure 2-52). The input offsetvoltage (VOS) is measured at VCM = VSS – 0.15V andVDD + 0.15V (at +25°C) to ensure proper operation.

4.3.1.1 Phase Reversal

The input devices are designed to not exhibit phaseinversion when the input pins exceed the supplyvoltages. Figure 2-82 shows an input voltageexceeding both supplies with no phase inversion.

The input devices also do not exhibit phase inversionwhen the differential input voltage exceeds its limits;see Figure 2-83.

4.3.1.2 Input Voltage Limits

In order to prevent damage and/or improper operationof these amplifiers, the circuit must limit the voltages atthe input pins (see Section 1.1 “Absolute MaximumRatings †”). This requirement is independent of thecurrent limits discussed later on.

The ESD protection on the inputs can be depicted asshown in Figure 4-7. This structure was chosen toprotect the input transistors against many (but not all)overvoltage conditions, and to minimize input biascurrent (IB).

FIGURE 4-7: Simplified Analog Input ESD Structures.

The input ESD diodes clamp the inputs when they tryto go more than one diode drop below VSS. They alsoclamp any voltages that go too far above VDD; theirbreakdown voltage is high enough to allow normaloperation, but not low enough to protect against slowover-voltage (beyond VDD) events. Very fast ESDevents (that meet the specification) are limited so thatdamage does not occur.

VIP

VIM

GA1

VFG

VREF

GA2

Low-PassFilter

BondPad

BondPad

BondPad

VDD

VIP

VSS

InputStage

BondPad

VIM

ofINA Input


MCP6N16

In some applications, it may be necessary to preventexcessive voltages from reaching the INA inputs.Figure 4-8 shows one approach to protecting theseinputs. D1 and D2 may be small signal silicon diodes,Schottky diodes for lower clamping voltages ordiode-connected FETs for low leakage.

FIGURE 4-8: Protecting the Analog Inputs Against High Voltages.

4.3.1.3 Input Current Limits

In order to prevent damage and/or improper operationof these amplifiers, the circuit must limit the currentsinto the input pins (see Section 1.1 “AbsoluteMaximum Ratings †”). This requirement isindependent of the voltage limits previously discussed.

Figure 4-9 shows one approach to protecting theseinputs. The resistors R1 and R2 limit the possiblecurrent in or out of the input pins (and into D1 and D2).The diode currents will dump onto VDD.

FIGURE 4-9: Protecting the Analog Inputs Against High Currents.

It is also possible to connect the diodes to the left of theresistor R1 and R2. In this case, the currents throughthe diodes D1 and D2 need to be limited by some othermechanism. The resistors then serve as in-rush currentlimiters; the DC current into the input pins (VIP and VIM)should be very small.

A significant amount of current can flow out of theinputs (through the ESD diodes) when the commonmode voltage (VCM) is below ground (VSS); seeFigure 2-47.

4.3.1.4 Input Voltage Ranges

Figure 4-10 shows possible input voltage values(VSS = 0V). Lines with a slope of +1 have constant VDM(e.g., the VDM = 0 line). Lines with a slope of -1 haveconstant VCM (e.g., the VCM = VDD/2 line).

For normal operation, VIP and VIM must be kept withinthe region surrounded by the thick blue lines. Thehorizontal and vertical blue lines show the limits on theindividual inputs. The blue lines with a slope of +1 showthe limits on VDM; the larger GMIN is, the closer they areto the VDM = 0 line.

The input voltage range specifications (VIVL and VIVH)change with the supply voltages (VSS and VDD,respectively). The differential input range specifications(VDML and VDMH) change with minimum gain (GMIN).Temperature also affects these specifications.

FIGURE 4-10: Input Voltage Ranges.

To take full advantage of VDML and VDMH, set VREF(see Figures 1-7 and 1-8) so that the output (VOUT) iscentered between the supplies (VSS and VDD). Also setthe gain (GDM) to keep VOUT within its range.

VDD

V1

D1

V2

D2

U1

MCP6N16

min(R1, R2) >VSS – min(V1, V2)

2 mA

VDD

V1

R1

D1

V2

R2

D2

U1

MCP6N16

min(R1, R2) >max(V1, V2) – VDD

2 mA

VIP

VIM

V DM=

0

VIVH

VIVL

0

VIV

H

VIV

L

0

V DM=

V DMH

VCM =

VDD /2

V DM=

V DML

VDD

VD

D


MCP6N16

4.3.2 ENABLE

This input (EN) is a CMOS, Schmitt-triggered input.When it is low, it puts the part in a low-power state andthe output is put into a high-impedance state. Whenhigh, the part operates normally.

If the EN pin is left floating, the amplifier will not operateproperly.

4.3.3 RAIL-TO-RAIL OUTPUT

The Minimum Output Voltage (VOL) and MaximumOutput Voltage (VOH) specifications describe thewidest output swing that can be achieved under thespecified load conditions.

The output can also be limited when VIP or VIM exceedsVIVL or VIVH or when VDM exceeds VDML or VDMH.

4.4 Applications Tips

4.4.1 INPUT OFFSET VOLTAGE OVER TEMPERATURE

Table 1 gives both the linear and quadratic temperaturecoefficients (TC1 and TC2) of input offset voltage. Theinput offset voltage can be estimated as follows:

EQUATION 4-12:

These specifications show these INA’s intrinsicperformance. The plots of input offset voltage versustemperature on the second page (Figures 1 to 3) showthe typical behavior for a few parts from the first waferlot.

In most designs, other effects will dominate the circuittemperature performance; see Section 4.4.13 “PCBDesign for DC Precision” for more details.

4.4.2 NOISE EFFECT ON OFFSET VOLTAGE

The input noise (eni) makes measured offset values(VOS) vary in a random manner. Lower noise requiresa lower noise power bandwidth (NPBW; see AN1228,mentioned in 5.3 “Application Notes”), whichincreases measurement time. In the offset-relatedspecifications (AOL, CMRR, CMRR2 and PSRR) andplots, the various values of NPBW were chosen totrade off time versus accuracy of results.

4.4.3 DC GAIN PLOTS

Figures 2-28 to 2-39 are histograms of the reciprocals(in units of µV/V) of CMRR, PSRR and AOL,respectively. They represent the change in input offsetvoltage (VOS) with a change in common mode inputvoltage (VCM), power supply voltage (VDD) and outputvoltage (VOUT).

The 1/AOL histogram is centered near 0 µV/V becausethe measurements are dominated by the INA’s inputnoise. The negative values shown represent noise andtester limitations, not unstable behavior. Productiontests make multiple VOS measurements, whichvalidates an INA's stability; an unstable part wouldshow greater VOS variability, or the output would stickat one of the supply rails.

4.4.4 OFFSET AT POWER-UP

When these parts power up, the input offset (VOS)starts at its uncorrected value (usually less than±10 mV). Circuits with high DC gain can cause theoutput to reach one of the two rails. In this case, thetime to a valid output is delayed by an output overdrivetime (like tODR), in addition to a start-up time (like tSTR).

It can be simple to avoid this extra start-up time.Reducing the gain is one method. Adding a capacitoracross the feedback resistor (RF) is another method.

4.4.5 SOURCE RESISTANCES

The input bias currents have two significantcomponents: switching glitches that dominate at roomtemperature and below, and input ESD diode leakagecurrents that dominate at +85°C and above.

Make the resistances seen by the inputs small andequal. This minimizes the output offset caused by theinput bias currents.

The inputs should see a resistance on the order of 10Ωto 1 kΩ at high frequencies (i.e., above 1 MHz). Thishelps minimize the impact of switching glitches, whichare very fast, on overall performance. In some cases, itmay be necessary to add resistors in series with theinputs to achieve this improvement in performance.

Small input resistances at the inputs may be needed forhigh gains. Without them, parasitic capacitances mightcause positive feedback and instability.

4.4.6 SOURCE CAPACITANCE

The capacitances seen by the inputs should be small.Large input capacitances and source resistances,together with high gain, can lead to positive feedbackand instability.

VOS TA VOS TC1T TC2T2

+ +=

Where:

TA = -40°C to +125°C

∆T = TA – 25°C

VOS(TA) = Input offset voltage at TA

VOS = Input offset voltage at +25°C

TC1 = Linear temperature coefficient

TC2 = Quadratic temperature coefficient


MCP6N16

4.4.7 MINIMUM STABLE GAIN

There are three options for different Minimum StableGains (1, 10 and 100 V/V; see Table 1). The differentialgain (GDM) needs to be greater than or equal to GMINin order to maintain stability.

Picking a part with higher GMIN has the advantages oflower input noise voltage density (eni), lower inputoffset voltage (VOS) and increased gain-bandwidthproduct (GBWP). The differential input voltage range(VDML and VDMH) is lower for higher GMIN, but supportsa reasonable output voltage range.

4.4.8 CAPACITIVE LOADS

Driving large capacitive loads can cause stabilityproblems for voltage amplifiers. As the loadcapacitance increases, the feedback loop’s phasemargin decreases and the closed-loop bandwidthreduces. This produces gain peaking in the frequencyresponse, with overshoot and ringing in the stepresponse. Lower gains (GDM) exhibit greater sensitivityto capacitive loads.

When driving large capacitive loads with theseinstrumentation amps (e.g., > 80 pF), a small seriesresistor at the output (RISO in Figure 4-11) improves thefeedback loop’s phase margin (stability) by making theoutput load resistive at higher frequencies. Thebandwidth will be generally lower than the bandwidthwith no capacitive load.

FIGURE 4-11: Output Resistor, RISO Stabilizes Large Capacitive Loads.

Figure 4-12 gives recommended RISO values fordifferent capacitive loads and gains. The x-axis is thenormalized load capacitance (CL GMIN/GDM), whereGDM is the circuit’s differential gain (1 + RF/RG) andGMIN is the minimum stable gain.

FIGURE 4-12: Recommended RISO Values for Capacitive Loads.

After selecting RISO for the circuit, double check theresulting frequency response peaking and stepresponse overshoot on the bench. Modify RISO’s valueuntil the response is reasonable.

4.4.9 GAIN RESISTORS

Figure 4-13 shows a simple gain circuit with the INA’sinput capacitances at the feedback inputs (VREF andVFG). These capacitances interact with RG and RF tomodify the gain at high frequencies. The equivalentcapacitance acting in parallel to RG is CG = CDM + CCMplus any board capacitance in parallel to RG. CG willcause an increase in GDM at high frequencies, whichreduces the phase margin of the feedback loop (i.e.,reduce the feedback loop’s stability).

FIGURE 4-13: Simple Gain Circuit with Parasitic Capacitances.

RISO

VOUT

CL

V1

VDD

V2

VREF

VFGRF

RG

U1

MCP6N16

2k

1,000

O(

)

1k

ded

RIS

Om

men

dR

ecom

10010p10010 100 1,000 10,000

Normalized Load Capacitance; CL GMIN/GDM (F)10p 100p 1n 10n

10p

VOUT

V1

VDD

V2

VREF

VFG

RF

RGCDMCCMCCM

U1

MCP6N16


MCP6N16

In this data sheet, RF + RG = 10 kΩ for most gains (0Ωfor GDM = 1); see Table 1-6. This choice gives goodphase margin. In general, RF (Figure 4-13) needs tomeet the following limits to maintain stability:

EQUATION 4-13:

4.4.10 EMI REJECTION RATIO (EMIRR)

Electromagnetic interference (EMI) can be coupled toan INA through electromagnetic induction or radiation,or by conduction. INAs are most sensitive to EMI attheir input pins.

EMIRR describes an INA’s EMI robustness. Internalpassive filters in these parts improve the EMIRR, whengood PCB layout techniques are used. EMIRR isdefined to be:

EQUATION 4-14:

4.4.11 REDUCING UNDESIRED NOISE AND SIGNALS

Reduce undesired noise and signals with:

• Low bandwidth signal filters:

- Minimizes random analog noise

- Reduces interfering signals

• Good PCB layout techniques:

- Minimizes crosstalk

- Minimizes parasitic capacitances and inductances that interact with fast switching edges

• Good power supply design:

- Isolation from other parts

- Filtering of interference on supply line(s)

4.4.12 SUPPLY BYPASS

With these INAs, the Power Supply pin (VDD for singlesupply) should have a local bypass capacitor (i.e.,0.01 µF to 0.1 µF) within 2 mm for good high-frequencyperformance. Surface mount, multilayer ceramiccapacitors, or their equivalent, should be used.

These INAs require a bulk capacitor (i.e., 1.0 µF orlarger) within 100 mm to provide large, slow currents.This bulk capacitor can be shared with other nearbyanalog parts as long as crosstalk through the suppliesdoes not prove to be a problem.

4.4.13 PCB DESIGN FOR DC PRECISION

In order to achieve DC precision on the order of ±1 µV,many physical errors need to be minimized. The designof the printed circuit board (PCB), the wiring, and thethermal environment have a strong impact on theprecision achieved. A poor PCB design can easily bemore than 100 times worse than the MCP6N16 opamps’ minimum and maximum specifications.

4.4.13.1 PCB Layout

Any time two dissimilar metals are joined together, atemperature dependent voltage appears across thejunction (the Seebeck or thermojunction effect). Thiseffect is used in thermocouples to measuretemperature. The following are examples ofthermojunctions on a PCB:

• Components (resistors, INAs, …) soldered to a copper pad

• Wires mechanically attached to the PCB

• Jumpers

• Solder joints

• PCB vias

Typical thermojunctions have temperature to voltageconversion coefficients of 1 to 100 µV/°C (sometimeshigher).

Microchip’s AN1258 (“Op Amp Precision Design: PCBLayout Techniques” – DS01258) contains in-depthinformation on PCB layout techniques that minimizethermojunction effects. It also discusses other effects,such as crosstalk, impedances, mechanical stressesand humidity.

4.4.13.2 Crosstalk

DC crosstalk causes offsets that appear as a largerinput offset voltage. Common causes include:

• Common mode noise (remote sensors)

• Ground loops (current return paths)

• Power supply coupling

Interference from the mains (usually 50 Hz or 60 Hz),and other AC sources, can also affect the DCperformance. Nonlinear distortion can convert thesesignals to multiple tones, including a DC shift in voltage.

Where:

0.25

GDM GMIN

fGBWP = Gain-Bandwidth Product

CG = CDM + CCM + (PCB stray capacitance)

RF 0=For GDM = 1:

RF

GDM2

2fGBWPCG------------------------------

For GDM > 1:

EMIRR dB 20VRF

VOS------------- log=

Where:

VRF = Peak Input Voltage of EMI (VPK)

∆VOS = Input Offset Voltage Shift (V)


MCP6N16

When the signal is sampled by an ADC, these ACsignals can also be aliased to DC, causing an apparentshift in offset.

To reduce interference:

- Keep traces and wires as short as possible

- Use shielding

- Use ground plane (at least a star ground)

- Place the input signal source near to the DUT

- Use good PCB layout techniques

- Use a separate power supply filter (bypass capacitors) for these zero-drift INAs

4.4.13.3 Miscellaneous Effects

Keep the resistances seen by the input pins as smalland as near to equal as possible, to minimize biascurrent-related offsets.

Make the (trace) capacitances seen by the input pinssmall and equal. This is helpful in minimizing switchingglitch-induced offset voltages.

Bending a coax cable with a radius that is too smallcauses a small voltage drop to appear on the centerconductor (the triboelectric effect). Make sure thebending radius is large enough to keep the conductorsand insulation in full contact.

Mechanical stresses can make some capacitor types(such as some ceramics) output small voltages. Usemore appropriate capacitor types in the signal path andminimize mechanical stresses and vibration.

Humidity can cause electrochemical potential voltagesto appear in a circuit. Proper PCB cleaning helps, asdoes the use of encapsulants.

4.5 Typical Applications

4.5.1 HIGH INPUT IMPEDANCE DIFFERENCE AMPLIFIER

Figure 4-14 shows the MCP6N16 used as a differenceamplifier. The inputs are high-impedance and givegood CMRR performance.

FIGURE 4-14: Difference Amplifier.

4.5.2 DIFFERENCE AMPLIFIER FOR VERY LARGE COMMON MODE SIGNALS

Figure 4-15 uses the MCP6N16 INA as a differenceamplifier for signals with a very large common modecomponent. The input resistor dividers (R1 and R2)ensure that the INA’s inputs are within their normalrange of operation. The capacitors (C1 and C2) set thesame voltage division ratio for high-frequency signals(e.g., a voltage step). C2 includes the INA’s CCM. R1and R2’s tolerances affect CMRR.

FIGURE 4-15: Difference Amplifier with Very Large Common Mode Component.

4.5.3 RTD TEMPERATURE SENSOR

Figure 4-16 shows an RTD temperature sensor circuit,which measures over the -55°C to +155°C range. Thesensor chosen changes from 78Ω to 159Ω over thisrange. The 2.49 kΩ and 4.99 kΩ resistors set thecurrent through the RTD and 68.1Ω resistor. The INAprovides a high-differential gain. The 10 µF capacitorfilters common mode interference on the bridge.

FIGURE 4-16: RTD Temperature Sensor.

VOUT

VIP

VDD

VIM

VREF

VFGRF

RG

U1

MCP6N16

VOUT

VDD

VREF

VFGRF

RGR2R1

V2

C1 C2

R2R1

V1

C1 C2U1

MCP6N16

VOUT

20 kΩ

100Ω

2.49 kΩ

68.1Ω RTD

4.99 kΩ

VDD

MCP6N16-100

10 µF

100Ω

EN

100Ω

4.99 kΩ 4.99 kΩ


MCP6N16

4.5.4 WHEATSTONE BRIDGE

Figure 4-17 shows the MCP6N16 INA used tocondition the signal from a Wheatstone bridge (e.g.,strain gage). The overall INA gain is set at 1001 V/V.The best GMIN option to pick, for this gain, is 100 V/V(MCP6N16-100).

FIGURE 4-17: Wheatstone Bridge Amplifier.

4.5.5 HIGH SIDE CURRENT DETECTOR

Figure 4-18 shows the MCP6N16 INA used to detectand amplify the high side current in a power supplydesign. U1’s low offset voltage makes it possible toreduce RSH, which saves power and minimizestemperature effects. U1’s supply current is included inthe measurement. The INA’s gain is set at 101 V/V, soVOUT changes 1.01V for every 1A change in IDD.

FIGURE 4-18: High Side Current Detector.

VOUT

VREF

VFG

RF100 kΩ

VDD

RW1RW2

RW2RW1 U1

MCP6N16-10010 µF

RN100Ω

RG100Ω

RSH

VL

IL

VPS = +1.8V to 5.5V

VOUT

VREF

VFG

RF

RG

10.0 kΩ

100Ω

U1

MCP6N16-100

VPS

IPS

IDD

IPS = IL + IDDIPS = (VPS – VL)/(10 mΩ)

= (VOUT – VREF)/((10 mΩ) (101 V/V))

10 mΩ


MCP6N16

5.0 DESIGN AIDS

Microchip provides the basic design aids needed forthe MCP6N16 instrumentation amplifiers.

5.1 Microchip Advanced Part Selector (MAPS)

MAPS is a software tool that helps efficiently identifyMicrochip devices that fit a particular designrequirement. Available at no cost from the Microchipwebsite at www.microchip.com/maps, the MAPS is anoverall selection tool for Microchip’s product portfoliothat includes Analog, Memory, MCUs and DSCs. Usingthis tool, a customer can define a filter to sort featuresfor a parametric search of devices and exportside-by-side technical comparison reports. Helpful linksare also provided for Data sheets, Purchase andSampling of Microchip parts.

5.2 Analog Demonstration Board

Microchip offers a broad spectrum of AnalogDemonstration and Evaluation Boards that aredesigned to help customers achieve faster timeto market. For a complete listing of these boardsand their corresponding user’s guides and technicalinformation, visit the Microchip web site atwww.microchip.com/analog tools.

5.3 Application Notes

The following Microchip Application Notes areavailable on the Microchip web site at www.microchip.com/appnotes and are recommendedas supplemental reference resources.

• AN884: “Driving Capacitive Loads With Op Amps”, DS00884

• AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990

• AN1177: “Op Amp Precision Design: DC Errors”, DS01177

• AN1228: “Op Amp Precision Design: Random Noise”, DS01228

• AN1258: “Op Amp Precision Design: PCB Layout Techniques”, DS01258

Some of these application notes, and others, are listedin the design guide:

• “Signal Chain Design Guide”, DS21825


http://www.microchip.com/maps/main.aspx

www.micro chip.com/analog tools

http://www.microchip.com/wwwcategory/TaxonomySearch.aspx?show=Application%20Notes&ShowField=no

http://www.microchip.com/wwwcategory/TaxonomySearch.aspx?show=Application%20Notes&ShowField=no

MCP6N16

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

Product Number Code

MCP6N16-001E/MF DADV

MCP6N16T-001E/MF DADV

MCP6N16-010E/MF DADW

MCP6N16T-010E/MF DADW

MCP6N16-100E/MF DADX

MCP6N16T-100E/MF DADX

DADV1423256

8-Lead MSOP (3x3 mm) Example

8-Lead DFN (3x3 mm) Example

N16010423256


MCP6N16

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging


MCP6N16




MCP6N16

APPENDIX A: REVISION HISTORY

Revision A (July 2014)

• Original Release of this Document.

MCP6N16


PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP6N16 Single Instrumentation AmplifierMCP6N16T Single Instrumentation Amplifier

(Tape and Reel)

Gain Option: 001 = Minimum gain of 1 V/V010 = Minimum gain of 10 V/V100 = Minimum gain of 100 V/V

Temperature Range: E = -40°C to +125°C

Package: MF = Plastic Dual Flat, no lead Package - 3×3x0.9 mm Body, 8-lead (DFN)

MS = Plastic Micro Small Outline Package, 8-lead (MSOP)

Examples:

a) MCP6N16T-001E/MF: Tape and Reel,Minimum gain = 1,Extended temperature, 8LD 3×3 DFN

b) MCP6N16-010E/MS: Minimum gain = 10, Extended temperature,8LD MSOP

PART NO. X /XX-XXX

Gain PackageTemperatureRange

DeviceOption

[X](1)

Tape and ReelOption

Note 1: Tape and Reel identifier only appears in the catalog part number description. This identi-fier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

2014 Microchip Technology Inc.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISO/TS 16949 ==

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 978-1-63276-377-8

Microchip received ISO/TS-16949:2009 certification for its worldwide

DS20005318A-page 57

headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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mcp6n16 · mcp6n16-100 100 17 60 112 110 0.027 35 0.93 45 note 1: gmin is the minimum stable gain...

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