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Corrections of Hardware Manual
MB91460
hm91460-v1.21-errata-x1-17
© Fujitsu Microelectronics Europe GmbH
Errata sheet, MB91460 Hardware Manual (hm91460-v1.21)
This is the errata sheet for the Hardware Manual hm91460-v1.21 of the MB91460
microcontroller series. It describes all known discrepancies and corrections of
the MB91460 microcontroller series Hardware Manual.
Ref. Number (Internal ref.
number)
Date Version
No.
Chapter/Page Description/Correction
(Text Link) dd.mm.yy
HWM91460001 18.01.06 V1.00 Transition to standby mode with
enabled prefetch mechanism
HWM91460002 20.02.06 V1.00
Timing requirement of the
PARALLEL programming mode of the
flash security
HWM91460003 19.04.06 V1.00 UART4 SOT4 is initialized by the
boot-ROM
HWM91460004 05.12.06 V1.0 10 Wake-up from stop mode, ext. IRQs
are not stored during blackout.
HWM91460005 17.07.06 V1.00 20.1
Watchdog Timer: Retriggered
/cleared automatically by DMA
(MB91V460A, MB91461)
HWM91460006 05.12.06 V1.00 Chip IDs
HWM91460007 18.06.08 V1.03 32.4.8 USART FIFO
HWM91460008 24.10.07 V1.00 17.0 Eva-device: Input frequency for
clock modulator
HWM91460009 01.11.07 V1.00 16, 9.2,
9.6.4/5,
13.4.1, 21
RC clock run mode after clock
supervisor reset cannot be left
with hardware watchdog reset
HWM91460010 04.04.08 V1.01 54.6 Flash access mode switching
HWM91460011 29.05.08 V1.02 6.3 Watchdog reset
HWM91460012 29.05.08 V1.02 36.7.1 USART; Status bits of register
SSR04
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HWM91460013 29.05.08 V1.02 44.3.4 A/D Converter; Sampling Timer
Setting Register (ADCT)
HWM91460014 24.07.08 V1.04 47.7.4 LCD: Enabling LCD even in the
Sub-STOP state
HWM91460015 24.07.08 V1.04 47.8 LCD: “Cautions” Corrections added
HWM91460016 24.07.08 V1.04 47.6 LCD: “Settings” Corrections added
HWM91460017 24.07.08 V1.04 47.4.1 LCD: Control Register, Note added
HWM91460018 25.07.08 V1.04 22.4.1 Main Clock Oscillation Stability
Wait Timer
HWM91460019 20.08.08 V1.05 30.1 Corrected I/O Signal description
for Pins 16_0 … Pin16_6
HWM91460020 24.09.08 V1.06 36.7.1 ICU interrupts: Corrected edge
polarity description
HWM91460021 23.10.08 V1.07 32.4.6
Correction of note regarding bits
of the Extended Communication
Control Register (ECCR04)
HWM91460022 05.07.10 V1.16 53.3 Registers modified by BootROM
HWM91460023 03.03.09 V1.09 54 Flash Memory write protection
limitations
HWM91460024 30.03.09 V1.10 54.6 Note added regarding Flash access
mode switching
HWM91460025 07.04.09 V1.11 29.3.2 Corrected EDSU Control Register
(BCTRL) description
HWM91460026 07.04.09 V1.11 29.3.2
Corrected EDSU Channel
Configuration Register (BCR)
description
HWM91460027 07.04.09 V1.11 29.3.2
EDSU; Corrected relationship of
BCR, BAD and BIRQ register
description.
HWM91460028 07.04.09 V1.11 29.4.1
EDSU; Corrected operand size and
operand address relations
description
HWM91460029 07.04.09 V1.11 29.4.3 EDSU; Corrected data value break
description
HWM91460030 07.04.09 V1.11 29.3.2 EDSU; Note regarding Instruction
Address Capture Register (BIAC)
HWM91460031 06.05.09 V1.12 32.4.6
Extended Communication Control
Register (ECCR04); Added function
description regarding Start/Stop
bit mode enable(bit3).
HWM91460032 09.06.09 V1.13 13 Corrected block diagram of clock
distribution
HWM91460033 08.10.09 V1.14 16 Corrected Chapter “Clock
Supervisor”
HWM91460034 20.10.09 V1.15
44.1,
44.3.4,
44.6.3
Corrected ADC input circuit and
sampling time calculation formula
HWM91460035 21.10.09 V1.15 23
The Sub Oscillation Stabilization
Timer operation enable bit
WPCRH.WEN is not available
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HWM91460036 21.10.09 V1.15 22,
23
Description of clearing the
counter of Main Oscillation
Stabilization Timer and Sub
Oscillation Stabilization Timer
is described precisely.
A difference to MB91460E series
is described.
HWM91460037 19.08.10 V1.17 32
Extended note on how to prevent
high pulse on SCK line when
performing software reset
(setting SMR:UPCL in master mode
2 with the mark level set to
„0‟).
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HWM91460001
Transition to standby mode with enabled prefetch mechanism
Affected devices: - MB91V460A (in flash mode only – not for debugging)
- MB91F467DA Revision 1, 2
- MB91F464AA Revision 1 (cache not specified)
- MB91F465KA Revision 1
- MB91F469GA Revision 1
- MB91F467RA Revision 1
Problem Description:
If the Flash I-Cache is enabled (FCHCR.ENAB == 1) and the Prefetch Mechanism is
enabled (FCHCR.PFEN == 1) and the device is set into the standby modes SLEEP or
STOP it can happen that an invalid entry into the Flash I-Cache is made which
can cause irregular program operation after recovering from the SLEEP or STOP
mode.
Problem Workaround:
It is mandatory to lock the Flash I-Cache (FCHCR.LOCK :=1) before setting the
device into SLEEP or STOP mode to avoid writing an invalid entry into the
Cache. After recovering from SLEEP or STOP mode the Flash I-Cache can be
unlocked again.
Please see the corresponding customer information for details:
CI-300008-MB91460_Flash_IF_Arbitration.pdf
HWM91460002
Timing requirement of the PARALLEL programming mode of the flash security.
Precondition:
CHIP ERASE COMMAND is performed with addresses of sectors secured with the
write protection bits and the write data DIN data changes while WEX=L.
Effect:
CHIP ERASE COMMAND might or might not be executed.
Workarounds:
1. Perform the CHIP ERASE COMMAND with addresses of sectors NOT secured with
the write protection bits.
OR
2. Change timing of write data DIN vs. write enable WEX
________________________ ___________________________
WEX |_____________|
____________ ______________________________________ ______________
DIN ____________X______________________________________X______________
timing || ||
to avoid changing while WEX=L.
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Remarks:
- This effect does not compromise the flash security!
- It does not affect programming operation and standard timing of an empty
flash
- It does not affect programming operation and standard timing of an unsecured
flash (read and write)
- It does not affect programming operation and standard timing of a read-only
secured flash
- It does not affect programming operation and standard timing with a chip
erase command addresses not inside write protected sectors
HWM91460003
Affected devices: - MB91V460A (UART0 instead of UART4)
- MB91F467DA Revision 1, 2
- MB91F464AA Revision 1
- MB91F465KA Revision 1
Precondition:
Initialization of UART4 by the boot ROM. (Security vectors are not set) and
UART4 is initialized after start-up for asynchronous data transmission.
Effect:
The boot ROM always initializes the UART4 SOT4. If nothing is transmitted by
the boot ROM, this results in a high level on SOT4 for the time of the active
boot ROM. At the end of the boot ROM, the registers of the UART4 are reset to
the initial values; hence after about 2 µs of low level is SOT4 high-impedance,
which may be interpret by a receiver as low level.
If the UART 4 is initialized immediately after start-up for asynchronous data
transmission by the application, a receiver may interpret the changes as a
valid signal.
Workarounds:
- Pull-up resistor on SOT4 to provide a high-level when SOT4 is high-impedance.
This reduces the time of low level to about 2 µs.
- Do not use UART4 in asynchronous mode immediately after start-up.
(UMa)
HWM91460004
Please see the corresponding customer information
CI-300012-MB91460_External_Interrupt.pdf
(MBo)
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HWM91460005
Watchdog Timer: Retriggered /cleared automatically by DMA (MB91V460A, MB91461)
Chapter 20.1, page 273
affected devices: MB91V460A and MB91461
The watchdog timer will be retriggered / cleared automatically by DMA during D-
bus access.
(NFl, MBo)
HWM91460006
Below, the chip-IDs of the different devices are listed.
Chip-ID location: 0xBFF4 Datecodes
---------------------------------------------------
MB91V460A 0x020DCC01
MB91F464AA Rev. 1 0x0205D048
Rev. 2 0x0205D049 from 0644-K00, K01, K02
Rev. 3 0x0205D04A
MB91F464AB 0x0205D04B
MB91F465BB 0x43000040
MB91F467BA Rev. 1 0x43000008 0646-Z00
Rev. 2 0x43000041
MB91F467BB 0x43000062
MB91F467CA 0x43000007
MB91F467CB 0x43000065
MB91F465DA Rev. 1 0x43000005
Rev. 2 0x43000063
MB91F467DA Rev. 1 0x0205D329
Rev. 2 0x0205D32A from 0616-Z11
Rev. 3 0x0205D32B from 0642-Z07
Rev. 4 0x0205D32C
MB91F467DB 0x0205D32D
MB91F469GA Rev. 1 0x0205D558
Rev. 2 0x0205D558 from 0643-Z03
Rev. 3 0x0205D55A
MB91F469GB 0x0205D55B
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Chip-ID location: 0xBFF4 Chip-ID Datecodes
---------------------------------------------------
MB91F465KA Rev. 1 0x0205D050
Rev. 2 0x0205D051
Rev. 3 0x0205D052
MB91F465KB 0x0205D053
MB91F467MA 0x43000021
MB91F465XA Rev. 1 0x43000006
Rev. 2 0x43000064
Chip-ID location: 0xB000 Chip-ID ---------------------------------------
------------
MB91461 0x00000100
MB91F463NA 0x4630100
MB91F463NB 0x4630200
MB91F467RA 0x00000100
MB91F467RB 0x00000200
MB91F467RC 0x00000200
(MBo, MVo)
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HWM91460007
Chapter 32.4.8 FIFO Control Register (FCR04), Page 631: Notes, Rx triggerlevel.
Incorrect:
"The RX triggerlevel sets the reception FIFO level where the reception
interrupt is activated. E.g. if the triggerlevel is at its default value of
RXL[3:0]=0000, the interrupt is activated if one reception is stored in the
FIFO. If the the triggerlevel is set to RXL[3:0]=1111, the interrupt is
activated if 16 receptions are stored in the FIFO. In general: a reception
interrupt is triggered if FSR[4:0] > FCR[7:4]."
Correct:
"The RX triggerlevel sets the reception FIFO level where the reception
interrupt is activated. E.g. if the triggerlevel is at its default value of
RXL[3:0]=0000, the interrupt is activated immediately. If the the triggerlevel
is set to RXL[3:0]=1111, the interrupt is activated if 15 receptions are stored
in the FIFO.
In general: a reception interrupt is triggered if FSR[4:0] >= FCR[7:4]."
Below listed devices are not affected. Please note that register setting
FCR[3] = 1 has to be done.
MB91F463CA
MB91F465CA
MB91F467SA
MB91F465PA
MB91F467PA
MB91F467TA
MB91F469TA
MB91F469QA
MB91FV460B
(UMa, MBo, MSt, MHz)
HWM91460008
Chapter 17 Clock Modulator
For the MB91V460A Eva device there is a restriction for the input frequency of
the clock modulator.
Input frequency of clock modulator is limited to the range: 16 MHz … 24 MHz.
(UMa, MBo, MHz)
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HWM91460009
RC clock run mode after clock supervisor reset cannot be left by hardware
watchdog reset
The clock supervisor function is used to detect a missing main clock or sub
clock signal. In case the clock supervisor detects a missing clock signal, it
switches to RC clock sources and issues a clock supervisor reset. MCU starts up
on RC clock now.
If you now ran into a hardware watchdog reset by not triggering HWWD_CL bit in
time, the bit CSVCR_MM (main clock missing) or CSVCR_SM (sub clock missing) is
not cleared which leads to another startup on RC clock. Even if the hardware
watchdog reset is an INITX reset type, it is not able to clear these bits.
To clear these bits and to startup on main clock again (only possible if
previous clock supervisor reset was caused by a short-time distortion of main
clock signal and not of a total loss of oscillator connection), you need power-
on reset or external reset input at INITX pin.
(MVo, MBo)
HWM914600010
Chapter 54.6 "Flash Access Mode Switching"
Note:
For availability of this function and its start address, please refer to the
datasheet of the device, section "Embedded Program/Data Memory (Flash)".
(PHu, MBo, MHz)
HWM91460011
Chapter 6 "Watchdog Reset (INIT: Settings Initialization Reset)"
Chapter 6.3 “Flag”
Incorrect:
When watchdog reset request is triggered, the watchdog timeout flag (RSRR.WDOG)
is set to “1”. (SWWD and HWWD)
Correct:
When watchdog reset request is triggered, the watchdog timeout flag (RSRR.WDOG)
is set to “1”. (SWWD)
(JWa, HSt, MHz)
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HWM91460012
Chapter 32 "USART (LIN/FIFO)"
Table 4-5 “Functions of each bit of status register 04 (SSR04)”; p. 627
Incorrect:
Correct:
(JWa, HSt, MHz)
HWM91460013
Chapter 44.3.4 “Sampling Timer Setting Register (ADCT)”
Change in the paragraph [bit9 to 0] for better legibility.
Before:
Tsamp = (200 * 103 + 2.52 * 103) * 10.7 * 10-12 * 7 = 15.17 [us]
Better:
Tsamp = (200 * 10
3 + 2.52 * 10
3) * 10.7 * 10
-12 * 7 = 15.17 [us]
(JWa, HSt, MHz)
TIE
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HWM91460014
Chapter 47.7.4 “How to enable LCD display even in the Sub-STOP state”
Incorrect:
According to hardware manual, the LCD continues working in "Sub-STOP" mode if
the control bit LCR0.LCEN is set.
Correct:
While the digital part continues working, the analog part is disabled in STOP
mode, regardless of LCR0.LCEN setting.
The outputs COM[3:0] and SEG[39:0] will output "L" level in STOP mode.
Workaround: Don't use STOP mode, or use MB91V460B.
(JFl, MHz)
HWM91460015
Chapter 47.8 “Caution”
Some statements in chapter 47.8 “Caution” are incorrect:
Incorrect:
Correct:
VRAM[0:19] can be written in byte, halfword and word access
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Incorrect:
Correct:
According to ref. number HWM914600014 the LCD it is disabled in any kind of
STOP state.
(JFl, MHz)
HWM91460016
Chapter 47.6 “Setting”
Table 6-4 “Required Setting to Enable LCD Display in Sub-STOP state”
Incorrect:
Correct:
The CPU does not need to be switched to Sub Clock. It is sufficient to switch
the LCD clock source to Sub Clock by setting LCR0.CSS.
(JFl, MHz)
HWM91460017
Chapter 47.4.1 “LCR0: LCDC Control Register 0”
Note:
The LCD can also be operated on RC-clock. This can be enabled by setting bit
CSCFG.CSC3 (switches to RC clock instead of 32kHz Sub Clock). Please see also
chapter 13.4.4 “Clock Source Configuration Register”.
(JFl, MHz)
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HWM91460018
Chapter 22.4.1 “OSCRH: Control Register for the Main Clock Oscillation
Stability Wait Timer”
Incorrect:
Correct:
(MBo, MHz)
(2.0 ms)
(65.5 ms)
(4.0 s)
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HWM91460019
Chapter 30.1 “I/O Ports function”
Corrected I/O Signal description for Pins 16_0 … Pin16_6 of Port 16
Incorrect:
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Correct:
(MVo, MHz)
P16_6
P16_5
P16_4
P16_3
P16_2
P16_1
P16_0
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HWM91460020
Chapter 36.7.1 “What are the types of active edge polarity for external input,
and how to select them?”
Corrected external input active edge polarity bit pattern.
Incorrect:
Correct:
(HGl, MHz)
„01“
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HWM91460021
Chapter 32.4.6 “Extended Communication Control Register (ECCR04)”
In Figure 4-6 a wrong note is given for bit TBI “Transmission bus idle”, bit
RBI “Reception bus idle” and bit BIE “Bus idle interrupt enable”.
Incorrect:
~ ~
Correct:
~ ~
(MVo, JFl, MHz)
Not useable in mode 2 when MS = “1”
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HWM91460022
Chapter 53.3 “Registers modified by BootROM”
The list which shows the RAM address of the individual devices where the
BootROM stores the RSRR is updated.
Before update:
After update:
MB91V460A 0x20500
MB91F460A 0x2E500
MB91F460B 0x2E500
MB91F460C 0x2E500
MB91F465D 0x2E500
MB91F467D 0x28500
MB91F460E 0x2E500
MB91F460G 0x28500
MB91F460K 0x2E500
MB91F460M 0x2E500
MB91F460P 0x2E500
MB91F460Q 0x2E500
MB91F460S 0x2E500
MB91F460T 0x2E500
MB91F460X 0x2E500
(RSc, MHz, JWa)
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HWM91460023
1. Limitations on the FLASH write protection function specifications
1.1 Affected products
MB91460 series:
MB91F464A, MB91F465B, MB91F467B, MB91F465C, MB91F467C
MB91F465D, MB91F467D, MB91F469G, MB91F464H, MB91F465K,
MB91F467M, MB91F463N, MB91F465P, MB91F467P, MB91F469Q,
MB91F467R, MB91F467S, MB91F467T, MB91F465X
1.2 Overview
The FLASH write protection function in the MB91460 series allows each sector to
be set as write-protected (writing prohibited). However, it has been discovered
that it may be possible to write to sectors that have been set as write-
protected depending on the usage method.
However, there are no problems if any of the following methods are used.
Please use the method shown in [1] below to write to the FLASH memory. For a
method of write protection other than method [1], please use method [2].
[1] Set the address used in the write sequence to a sector address that is
always written to.
[Example] Write 0xAAAA to address ((adr & 0xFFFC000) + 0x155n) // 1st unlock cycle Write 0x5555 to address ((adr & 0xFFFC000) + 0x2AAn) // 2nd unlock cycle Write 0xA0A0 to address ((adr & 0xFFFC000) + 0x155n) // 3rd unlock cycle Write the target data to address adr // Data write
Where the conditions are that adr is the address of the target sector and
n is set to be within the target sector.
[2] Set the write protection (writing prohibited) function on all sectors.
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2. List of FLASH memory commands for the MB91460 series (revised version)
(MBo, MHz)
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HWM91460024
Chapter 54.6 “Flash Access Mode Switching”
Note:
For the address of the switching routine in the Boot ROM, please refer to the
datasheet of the appropriate flash device.
(JWa, MBo, MHz)
HWM91460025
Chapter 29.3.2 “Explanations of Registers”
Corrected EDSU Control Register (BCTRL) description
Incorrect:
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Correct:
BIT
BIT
BIT
BIT
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(MSt, KGo, MHz)
HWM91460026
Chapter 29.3.2 “Explanations of Registers”
Corrected EDSU Channel Configuration register (BCR) description
Incorrect:
BIT
BIT
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Correct:
BIT
BIT
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BIT
BIT
BIT
BIT
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(MSt, KGo, MHz)
BIT
BIT
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HWM91460027
Chapter 29.3.2 “Explanations of Registers”
Corrected description in table 3-3.
Incorrect:
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Correct:
IA1 / OA1 DT1
IA0 / OA0 DT0
IA0 / OA0
IA1 / OA1
IA0 / OA0
IA1 / OA1 DT1
IA0 / OA0 DT0
IA1 / OA1
IA0 / OA0
IA1 / OA1 DT1
IA0 / OA0 DT0
IA1 / OA1
IA0 / OA0
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(MSt, KGo, MHz)
IA1 / OA1 DT1
IA0 / OA0 DT0
IA1 / OA1
IA0 / OA0
IA1 / OA1 DT1
IA0 / OA0 DT0
IA1 / OA1
IA0 / OA0
IA1 / OA1 DT1
IA0 / OA0 DT0
IA1 / OA1
IA0 / OA0
IA1 / OA1 DT1
IA0 / OA0 DT0
IA1 / OA1
IA0 / OA0
IA1 / OA1 DT1
IA0 / OA0 DT0
IA1 / OA1
IA0 / OA0
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HWM91460028
Chapter 29.4.2 “Operand address break”
Corrected description in table 4-3.
Incorrect:
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Correct:
(MSt, KGo, MHz)
BOAC
BOAC
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HWM91460029
Chapter 29.4.3 “Data value break”
Corrected description in table 4-3
Incorrect:
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Correct:
(MSt, KGo, MHz)
BAD1/0
BAD1
BAD1
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HWM91460030
Chapter 29.3.2 “Explanations of Registers”
Additional note regarding Instruction Address Capture Register (BIAC)
Note:
In case of Instruction Address (IA), Operand Address (OA) or Operand Data Value
Break (DT) the BIAC register keeps valid Instruction Address (IA) until
respective BIRQ.BD-bits are reset.
In case of Protection Violation Break (PV) the BIAC register keeps valid
Instruction Address (IA) until PV-bit is reset.
In case of multiple breaks PV along with e.g. IA, OA or DT the BIAC register
keeps valid Instruction Address (IA) until both PV-bit and respective BIRQ.BD-
bits are reset.
(MSt, KGo, MHz)
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HWM91460031
Chapter 32.4.6 “Extended Communication Control Register (ECCR04)”
Table 4-8, Added function description regarding Start/Stop bit mode enable
(bit3)
Incorrect:
~ ~
~ ~
Correct:
~ ~
~ ~
Setting SSM is only possible if operation mode is set to 2 (SMR04, MD bits)
(JWa, MHz)
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HWM91460032
Chapter 13 “Clock Control”
Corrected Figure 1-1: Block diagram of clock distribution
Incorrect:
CORRECT:
(NFl, MHz)
CLKMAIN
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HWM91460033
Chapter 16 “Clock Supervisor”
The whole chapter 16 “Clock Supervisor” is updated and corrected due to several
wrong and missing descriptions.
Correct:
Please refer to the following additional document for the complete reviewed and
corrected chapter 16 “Clock supervisor”.
>> hm91460-errata-clock-supervisor-x1.00.pdf
Please note, that this document completely replaces the chapter 16 of the
current MB91460 Hardware Manual hm91460-v1.21. All text parts marked by a red
change bar on the left side indicate differences to the current hm91460-v1.21.
The document is also valid for MB91FV460B and derived flash devices. Additional
features of these devices are marked by red text “new feature”.
All parts, which are marked with “new feature”, describe the intended behavior
for future devices. The current implementation of the “new feature” in
MB91FV460B1/2 and MB91F467PA shows partly faulty behavior.
JWa, JFl
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HWM91460034
Chapter 44 “A/D Converter (ADC)”
The description of the ADC input circuit and the appropriate formula for
sampling time calculation given in the current hardware manual v1.21 is
incomplete. Especially for high input impedance, the calculated sampling time
will be too short. The following lines will describe the wrong documentation
and will give the correction.
(1) Replacement circuit for analog input (chapter 44, section 1):
Incomplete:
The parasitic PCB and pin input capacitance of the MCU itself is missing in the
circuit.
Correct:
The equivalent circuit now also considers the external capacitance Cext (e.g.
PCB wiring capacitance) and the pin input capacitance of the MCU Cin.
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(2) Calculation formula for sampling time (chapter 44, section 3.4 and 6.3)
Considering the complete equivalent circuit, the formula for sampling time
calculation given in the current hardware manual is wrong.
Wrong:
The formula is valid for a single RC filter with . The real input circuit is two RC filters in series for which the calculation of the time
constant i.e. sampling time ( ) is more complex.
If the additional capacitance of Cext and Cin is not considered, the sampling
time will be too short. Especially for high input impedance circuits the ADC
sampling capacitance CADC is mainly charged by Cext and Cin. As these capacities
are normally in the same range as CADC, a charge exchange between Cext || Cin and
CADC will take place, resulting in a voltage drop. Then all three capacities
(Cext, Cin and CADC) must be charged by the source. Therefore the calculation
formula must comprise Cext and Cin also.
Correct:
The sampling time should be set to minimum . The following approximation formula for the replacement model above can be used:
If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF
to the analog input pin. In this case the internal sampling capacitance CADC
will be charged out of this external capacitance.
Note:
Please refer to the appropriate datasheet of your device to obtain the values
for the formula shown above. The pin input capacitance (Cin) can be found in
chapter “Electrical Characteristics”, section “3. DC characteristics”, referred
as “Input capacitance CIN”. The ADC values are located in section “4. A/D
converter characteristics”. The input resistance RADC is referred as “Input
resistance RIN” and the ADC sampling capacitance CADC as “Input capacitance CIN”.
JWa, JFl
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HWM91460035
Chapter 23 “Sub Oscillation Stabilization Timer”
The Timer operation enable bit for the Sub Oscillation Stabilization Timer
WPCRH.WEN (Bit5) is not available. The timer is always running. Reading this
bit returns „0‟.
Wrong: Correct:
Section 23.3
Register WPCRH
Bit5: WEN
Register WPCRH
Bit5: ---
Section 23.4.1
Register WPCRH
Bit5: WEN, Timer operation enable
Register WPCRH
Bit5-3: Reserved bit. Be sure to write
„0‟. The read value is „0‟.
Section 23.7.7
Sets with the timer operation enable
bit (WPCRH.WEN).
The timer is always running as long as
the Sub clock is available.
JWa, JFl
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HWM91460036
Chapter 22 “Main Oscillation Stabilization Timer”
Chapter 23 “Sub Oscillation Stabilization Timer”
The Main Oscillation Stabilization Timer and Sub Oscillation Stabilization
Timer provide a Timer clear bit WCL.
Timer clear bits:
Main Oscillation Stabilization Timer: OSCRH.WCL
Sub Oscillation Stabilization Timer: WPCRH.WCL
Writing „0‟ to these bits initiates to clear the appropriate timer counter. The
description given in the current version of the hardware manual (HWM) is not
complete.
Addendum to the explanation given in the current HWM:
After writing „0‟ to the WCL bit, the timer is not cleared immediately, it
stops counting only. To finally clear and restart the counter, a sub-sequent
access to an address within the R-Bus address area must be done. This can be
done by either writing or reading another register of a resource (connected to
the R-Bus) or simply read the RBSYNC address (0x03A).
Correct sequence example:
For Main Oscillation Stabilization Timer:
OSCRH_WCL = 0; // Initiate counter clearing
(counter will stop now)
RBSYNC; // Read access to R-bus to force timer
// to clear and restart
For Sub Oscillation Stabilization Timer:
WPCRH_WCL = 0; // Initiate counter clearing
(counter will stop now)
RBSYNC; // Read access to R-bus to force timer
// to clear and restart
Attention:
If no R-bus access follows the sequence of setting OSCRH_WCL/WPCRH_WCL = „0‟,
the appropriate counter will stop only. It will clear and restart not until
another R-bus access is done.
Note on MB91460E series:
The above described behavior is different for MB91460E series devices.
Writing WCL = „0‟ will immediately clear and restart the corresponding
timer (either Main Oscillation Stabilization Timer or Sub Oscillation
Stabilization Timer). This means on MB91F467E the Osci Stabi Timer
Interrupts may appear earlier then on other devices running the same
software.
JWa, JFl
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HWM91460037
Chapter 32 “USART (LIN / FIFO)”
Section 8. “Notes on using USART”
Note “Software reset of UART”
Problem:
In synchronous master mode (Mode 2 with SMR:SCKE=1) and with the SCK mark level
set to „0‟ (ESCR:SCES = '1'), there will be a high-pulse on the SCK line after
software reset (writing '1' to SMR:UPCL).
バスクロック
SCKO
ソフトウェアリセット
The connected slave device may consider this pulse on SCK line as a serial
clock.
Current description of note:
Extended description of note:
■ Software reset of UART
Perform the software reset (SMR: UPCL=1), when the TXE bit of the SCR register
is "0".
When performing software reset (writing '1' to SMR:UPCL) in master mode 2
(synchronous), with the mark level set to '0' (ESCR:SCES = '1'), special care
has to be taken to avoid pulses on SCK.
Please stick to the following precautions:
Once:
Set output data for the port function of the SCK pin to 0 by writing '0'
to the related PDR register bit and enable port output function for the
SCK pin by writing '1' to the related DDR register bit.
At every software reset:
Disable SCK output by writing '0' to the related PFR register bit before
performing software reset by writing '1' to SMR:UPCL. Then enable SCK
output again by writing '1' to the PFR register bit.
JFl,JWa
UPCL
Serial Clk