mb86r12 ’emerald-p’ mb86r12 ‘emerald-p’ register ......revised 26/8/11...

Revised 26/8/11 rd-mb86r12-emerald-p-rev0-04

Fujitsu Semiconductor Europe GmbH

MB86R12 ’Emerald-P’

Rev26/8/11

Version 0-04August 26, 2011

MB86R12 ‘Emerald-P’

Register Description

0 - 1 rd-mb86r12-emerald-p-rev0-04 Revised 26/8/11

Fujitsu Semiconductor Europe GmbH MB86R12 ’Emerald-P’

Preface

Intention and Target Audience of this DocumentThis document describes and gives you detailed insight to the stated Fujitsu semiconductor product.The MB86R12 ’Emerald-P’ device belongs to the Emerald SoC Family used for graphics applications.The target audience of this document is engineers developing products which will use the MB86R12 ’Em-erald-P’ device. It describes the function and operation of the device. Please read this document carefully.

TrademarksAPIX is a registered trademark of Inova Semiconductors GmbH, Grafinger Str. 26, 81671 Munich, GermanyARM is a registered trademark of ARM Limited in UK, USA and Taiwan. ARM is a trademark of ARM Limited in Japan and Korea. ARM Powered logo is a registered trademark of ARM Limited in Japan, UK, USA, and Taiwan.ARM Powered logo is a trademark of ARM Limited in Korea. PrimeCell: is owned by ARM Limited.

System names and product names which appear in this document are the trademarks of the respective company or organization.

LicensesUnder the conditions of Philips corporation I2C patent, the license is valid where the device is used in an I2C system which conforms to the I2C standard specification by Philips Corporation.The purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as de-fined by Philips.Please acquire license of MediaLB from SMSC and request the following document: OS62400 MediaLB De-vice Interface Macro Advanced Product Data Sheet.Please contact your FSEU Sales representative to acquire license for SD Card and request the following document: MB86R12 ’Emerald-P’ Hardware Manual - “Chapter 35: SDIO Host Controller”.

MB86R12 ’Emerald-P’ Fujitsu Semiconductor Europe GmbH

Document Revision History


Version Date Editor Comment

0-01 05.05.2011 A. v. Treuberg/R.v. Reitzenstein

1st. version (draft)


2nd. version (draft).All register reviewBase address added


Pixel engine updatedExt. Bus Controller updated

0-04 26.08.2011 R.v. Reitzenstein All register chapters reviewed and updated

Revised 26/8/11 rd-mb86r12-emerald-p-rev0-04 0 - 3



Blank for technical reasons



Registers Overview

Registers Overview Document Revision History................................................................................................................. 0-3

Register Description............................................................................................................................ 1-1

Clock Reset Generator (CRG) ............................................................................................................ 2-1

External Bus Interface......................................................................................................................... 4-1

DDR Memory Controller...................................................................................................................... 5-1

DMA Controller (HDMAC) ................................................................................................................... 6-1

General Purpose Input/Output (GPIO)................................................................................................ 8-1

Pulse Width Modulator (PWM)............................................................................................................ 9-1

Display Controller (DISP) .................................................................................................................. 11-1

Display Controller 2........................................................................................................................... 12-1

Writeback Processor ......................................................................................................................... 13-1

Video Capture ................................................................................................................................... 14-1

Shader............................................................................................................................................... 16-1

Pixel Engine ...................................................................................................................................... 17-1

Command Sequencer (CMDSEQ) .................................................................................................... 18-1

I2S ..................................................................................................................................................... 19-1

UART ................................................................................................................................................ 20-1

USART.............................................................................................................................................. 21-1

I2C..................................................................................................................................................... 22-1

Serial Flash Interface (SFI) ............................................................................................................... 23-1

Chip Controller (CCNT)..................................................................................................................... 25-1

External Interrupt Controller .............................................................................................................. 26-1

Signature Unit (SIG).......................................................................................................................... 29-1

Timing Controller (TCON) ................................................................................................................. 31-1

RLD................................................................................................................................................... 32-1

HS-SPI .............................................................................................................................................. 33-1

Power Management Unit (PMU) ....................................................................................................... 35-1

APIX TX ............................................................................................................................................ 37-1

APIX RX............................................................................................................................................ 38-1

APIX (PHY) ....................................................................................................................................... 39-1



Registers Overview



Chapter 1: Register DescriptionThis chapter describes the format and the meanig of the register tables, as well as the lock/unlockregisters of the MB86R12 ’Emerald-P’.

1.1 Format of Register Description

The register descriptions in the following sections use the format shown below to describe each bitfield of a register.

1.1.1 Meaning of Items and Sign

Register address:

Register address shows the address (Offset address) of the register.

Bit nummer:

Bit number shows bit position of the register.

Field name:

Field name shows bit name of the register.

R/W

R/W shows the read/write attribute of each bit field:

R: Read W: Write W1C: Writing a value of "1" clears the register. R0:Read value is always "0" R1: Read value is always "1" W0: Write value is always "0", and write access of "1" is ignored W1: Write value is always "1", and write access of "0" is ignored

Register name

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name

Read/Write

Reset value



Reset value:

Reset value indicates the value of each bit field immediately after reset.

0:Initial value is "0" 1:Initial value is "1" X:Undefined

Unused register fields are marked with a solid grey background.

Bit vectors are unsigned integers, if nothing else specified.

Global Address

For module base address refer to inter-module specification or global address map of the respectiveLSI.



Chapter 2: Clock Reset Generator (CRG)This chapter shows all Register of unit Clock Reset Generator (CRG)

Table 2-1: Register overviewBase Address Register Address Register Name Register Description

3E20_0000 (CRG-P)3B50_0000 (CRG_S)

Base address + 000h CRPLC PLL control registerBase address + 004h CRRDY PLL ready monitor registerBase address + 008h CRSTP Stop control registerBase address + 010h CRIMA Interrupt mask control registerBase address + 014h CRPIC Interrupt clear registerBase address + 020h CRRSC Reset control registerBase address + 024h CRSWR Software reset request registerBase address + 028h CRRRS Register controlled reset request registerBase address + 02Ch CRRSM Reset and monitor registerBase address + 030h CRCDC Clock divider control registerBase address + 100h CRDM0 Clock divider mode register of CLK0Base address + 104h CRLP0 Low power control register of CLK0Base address + 110h CRDM1 Clock divider mode register of CLK1Base address + 114h CRLP1 Low power control register of CLK1Base address + 120h CRDM2 Clock divider mode register of CLK2Base address + 124h CRLP2 Low power control register of CLK2Base address + 130h CRDM3 Clock divider mode register of CLK3Base address + 134h CRLP3 Low power control register of CLK3Base address + 140h CRDM4 Clock divider mode register of CLK4Base address + 144h CRLP4 Low power control register of CLK4Base address + 150h CRDM5 Clock divider mode register of CLK5Base address + 154h CRLP5 Low power control register of CLK5Base address + 160h CRDM6 Clock divider mode register of CLK6Base address + 164h CRLP6 Low power control register of CLK6Base address + 170h CRDM7 Clock divider mode register of CLK7Base address + 174h CRLP7 Low power control register of CLK7Base address + 180h CRDM8 Clock divider mode register of CLK8Base address + 184h CRLP8 Low power control register of CLK8Base address + 190h CRDM9 Clock divider mode register of CLK9Base address + 194H CRLP9 Low power control register of CLK9.Base address + 1A0H CRDMA Clock divider mode register of CLKA.Base address + 1A4H CRLPA Low power control register of CLKA.Base address + 1B0H CRDMB Clock divider mode register of CLKB.Base address + 1B4H CRLPB Low power control register of CLKB.Base address + 1C0H CRDMC Clock divider mode register of CLKC.Base address + 1C4H CRLPC Low power control register of CLKC.Base address + 1D0H CRDMD Clock divider mode register of CLKD.Base address + 1D4H CRLPD Low power control register of CLKD.Base address + 1E0H CRDME Clock divider mode register of CLKE.Base address + 1E4H CRLPE Low power control register of CLKE.Base address + 1F0H CRDMF Clock divider mode register of CLKF.Base address + 1F4H CRLPF Low power control register of CLKF.


file:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRLP9file:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRDMAfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRLPAfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRDMBfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRLPBfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRDMCfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRLPCfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRDMDfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRLPDfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRDMEfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRLPEfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRDMFfile:///P:\GCC\Emerald\HW_GROUP\70_Documentation\71_Reference\Spec_from_FML\collected_module_docu\html_view\crg11.component.gcc.sw.intern.html#CRLPF


2.1 Register Description

2.1.1 CRPLCPLL control register.

CRPLC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

PLLB

YPA

SS

Res

erve

d

LUW

MO

DE

Res

erve

d

PS

MO

DE

Res

erve

d

FBM

OD

E

Res

erve

d

RW

Res

erve

d

RW

Res

erve

d

RW

Res

erve

d

RW

-

PLLBYPASS

- 0xA - {3'b000,PSMODE} -

6'b000000(PLLBY-PASS=1)/

6'b111111(PLLBY-PASS=0)

Bit Position Bit Field Name Bit Description[31:25] Reserved

[24] PLLBYPASS PLL bypass mode. This bit is used to enter or exit PLL bypass mode. When this bit is set/cleared, the CRG unit enters/exits PLL bypass mode. This bit is initialized when a CRSTn port is asserted. The initial value is determined by the value of the PLLBYPASS pin. Note: Please do NOT change the PLLBYPASS bit while the FBMODE[5:0] bits are 6’b000000.NOBYPASS: 0, PLL clock is not bypassed.BYPASS: 1, PLL clock is bypassed.

[23:20] Reserved

[19:16] LUWMODE PLL lock-up wait time. These bits are used to set PLL lock-up wait time. The relation between the lock-up wait time and these bits is determined by the following tables. It is necessary to set an appropri-ate period according to the specification of PLL macro. These bits are initialized when a CRSTn port is assertedLUWMODE:: 0, TLUW (Time Lockup Wait) = 64*TREFCLKLUWMODE:: 1, TLUW (Time Lockup Wait) = 128*TREFCLKLUWMODE:: 2, TLUW (Time Lockup Wait) = 512*TREFCLKLUWMODE:: 3, TLUW (Time Lockup Wait) = 768*TREFCLKLUWMODE:: 4, TLUW (Time Lockup Wait) = 1024*TREFCLKLUWMODE:: 5, TLUW (Time Lockup Wait) = 1536*TREFCLKLUWMODE:: 6, TLUW (Time Lockup Wait) = 2048*TREFCLKLUWMODE:: 7, TLUW (Time Lockup Wait) = 3072*TREFCLKLUWMODE:: 8, TLUW (Time Lockup Wait) = 4096*TREFCLKLUWMODE:: 9, TLUW (Time Lockup Wait) = 6144*TREFCLKLUWMODE:: 10, TLUW (Time Lockup Wait) = 8192*TREFCLKLUWMODE:: 11, TLUW (Time Lockup Wait) = 12288*TREFCLKLUWMODE:: 12, TLUW (Time Lockup Wait) = 16384*TREFCLKLUWMODE:: 13, TLUW (Time Lockup Wait) = 24576*TREFCLKLUWMODE:: 14, TLUW (Time Lockup Wait) = 32768*TREFCLKLUWMODE:: 15, TLUW (Time Lockup Wait) = 49152*TREFCLK

[15:12] Reserved



[11:8] PSMODE Sets the dividing ratio of the PLL clock frequency.This bit is initialized when a CRSTn port is asserted.

n=1: 0000, Divider -> n = 1n=1(1*2): 0001, Divider -> n = 1 / (1 * 2)

[7:6] Reserved

[5:0] FBMODE Stops operation of the PLL clock.Note:Please be sure to set as PLL BYPASS mode before stopping PLL.PLLstop: 6'b00_0000, The PLL is stoppedPLLrun: 6'b11_1111, The PLL is activated

Bit Position Bit Field Name Bit Description



2.1.2 CRRDYPLL ready monitor register.

CRRDY

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

PS

RM

NT

Res

erve

d

PLLR

DY

Res

erve

d

R

Res

erve

d

R

- 0 - 0


[4] PSRMNT PSMODE monitor. The PSMODE bit indicates that the PSMODE bits setting (CRPLC register) have been used in the PLL clock frequency calculation. It is used to confirm that the PSMODE change operation was completed. This bit is initialized when a CRSTn port is asserted or the value of PSMODE bits is changed. Its initial value is 0. Write accesses to this (read-only) bit are ignored.PSMODENOTUSED: 0, PSMODE value is not used for the PLL clock frequency.PSMODEUSED: 1, PSMODE value is used for the PLL clock fre-quency.

[3:1] Reserved

[0] PLLRDY PLLREADY monitor. PLLRDY bit indicates an overflow of PLL lock-up wait time that is set by the LUWMODE[3:0] bits (CRPLC register). This bit does NOT indicate that the PLL is locked-up but only that the PLL lock-up wait time has expired. This bit is initialized when CRSTn port is asserted or the value of FBMODE bits is changed, and the ini-tial value is 0. Write accesses to this (read-only) bit are ignored.NOTREADY: 0, PLL is not ready.READY: 1, PLL is ready.



2.1.3 CRSTPStop control register.

CRSTP

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

STO

PM

NT

STO

PE

N

Res

erve

d

RW

0R

W

- 0 0


[1] STOPMNT The STOPMNT bit is used to monitor the Stop mode. If the CRG unit is in stop mode, this bit is set. This bit is initialized when a CRSTn port is asserted, and its initial value is 0. Write accesses with 1 are ignored. This bit is set only when CRG is in Stop mode.NOSTOP: 0, Not in Stop modeSTOPPED: 1, In Stop mode

[0] STOPEN The CRG unit enters stop mode when this bit is set and the STAND-BYWFI port is asserted. This bit is initialized when a CRSTn port is asserted, and its initial value is 0.STOPDISABLED: 0, Do not enter Stop mode.STOPENABLED: 1, Enter Stop mode when the STANDBYWFI port is asserted.



2.1.4 CRIMAInterrupt mask control register.

CRIMA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

RD

YIN

TM

Res

erve

d

RW

- 1


[0] RDYINTM This bit masks PLLRDYINT interrupt that indicates an overflow of the PLL lock-up wait time. If this bit is set, the interrupt doesn’t occur when the PLL lock-up wait time has expired. If not set, the interrupt occurs and the PLLRDYINT port is asserted. This bit is initialized when a CRSTn port is asserted, and its initial value is 1.NOMASK: 0, Don't mask the PLLRDYINT interrupt.MASK: 1, Mask the PLLRDYINT interrupt.



2.1.5 CRPICInterrupt clear register.

CRPIC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

PLL

RD

YIN

T

Res

erve

d

RW

0

- 0


[0] PLLRDYINT This bit is PLLRDYINT interrupt monitor that indicates an overflow of PLL lock-up wait time. When PLL lock-up wait time is completed and RDYINTM bit is set low, the PLLRDYINT port is asserted and this bit is set. This bit is also used to clear the interrupt via PLLRDYINT port. The PLLRDYINT port is deasserted and this bit is cleared by writing access (0 or 1) to this bit. This bit is initialized when CRSTn port is asserted, and the initial value is 0.The PLLRDYINT interrupt is not asserted.: 0, The PLLRDYINT interrupt is asserted.: 1,



2.1.6 CRRSCCRG Reset control register.

CRRSC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

SR

STM

OD

E

Res

erve

d

WD

RS

TMSW

RS

TM

Res

erve

d

AR

STM

OD

E

Res

erve

d

RW

Res

erve

d

RW

RW

Res

erve

d

RW

- F - 0 0 - 0xA


[19:16] SRSTMODE This bit is used to set pulse width of SRSToutn. It is necessary to set an appropriate reset time according to the specification of the debug-ging tool. TCCLK: CCLK cycle time. These bits are initialized when CRSTn port is asserted.8 x TCCLK.: 0, 12 x TCCLK.: 1, 16 x TCCLK.: 2, 24 x TCCLK.: 3, 32 x TCCLK.: 4, 48 x TCCLK.: 5, 64 x TCCLK.: 6, 96 x TCCLK.: 7, 128 x TCCLK.: 8, 192 x TCCLK.: 9, 256 x TCCLK.: 10, 384 x TCCLK.: 11, 512 x TCCLK.: 12, 768 x TCCLK.: 13, 1024 x TCCLK.: 14, 1536 x TCCLK.: 15,

[15:10] Reserved

[9] WDRSTM Watchdog reset mode. A watchdog reset occurs immediately after the WDRSTREQ port is asserted. The reset operation is determined by this bit. When high, CRG initializes the logic including this module. When low, CRG initializes the logic excluding this module and all reg-ister values of this module are preserved before and after reset. This bit is initialized when a CRSTn port is asserted and its initial value is 0.WDNOINITCRG: 0, CRG doesn’t initialize itself by asserting a watch-dog reset.WDINITCRG: 1, CRG initializes itself by asserting a watchdog reset.

[8] SWRSTM Software reset mode. A software reset occurs immediately after the SWRSTREQ bit is set. The reset operation is determined by this bit. When high, the CRG unit initializes the logic including this module. When low, CRG initializes the logic excluding this module and all reg-ister values of this module are preserved before and after reset. This bit is initialized when a CRSTn port is asserted and its initial value is 0.SWNOINITCRG: 0, CRG doesn’t initialize itself by asserting a soft-ware reset.SWINITCRG: 1, CRG initializes itself by asserting a software reset.



[7:4] Reserved

[3:0] ARSTMODE This bit is used to set the pulse width of the ARESETn signal (soft-ware reset pulse width). It is necessary to set an appropriate reset time according to the specification of the AMBA peripherals. After ARESETn has been asserted for the cycles shown in the following table, it is deasserted on the coincident edge of all clocks. Therefore the following table indicates the minimum width of the ARESETn pulse. TCCLK: CCLK Cycle time. These bits are initialized if a CRSTn port is asserted.8 x TCCLK.: 0, 12 x TCCLK.: 1, 16 x TCCLK.: 2, 24 x TCCLK.: 3, 32 x TCCLK.: 4, 48 x TCCLK.: 5, 64 x TCCLK.: 6, 96 x TCCLK.: 7, 128 x TCCLK.: 8, 192 x TCCLK.: 9, 256 x TCCLK.: 10, 384 x TCCLK.: 11, 512 x TCCLK.: 12, 768 x TCCLK.: 13, 1024 x TCCLK.: 14, 1536 x TCCLK.: 15,

Bit Position Bit Field Name Bit Description



2.1.7 CRSWRSoftware reset request register.

CRSWR

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

SW

RS

TRE

Q

Res

erve

d

RW

- 0


[0] SWRSTREQ This bit is used to assert a software reset. A software reset occurs immediately after this bit is set. The operation of the reset is deter-mined by SWRSTM bit (CRRSM register). This bit is initialized when CRSTn port is asserted and its initial value is 0. The value is always 0 when read access to this bit occurs.



2.1.8 CRRRSRegister controlled reset request register.

CRRRS

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RR

STR

EQR

W

0

Bit Position Bit Field Name Bit Description[31:0] RRSTREQ This bitfield is used to assert / deassert register-controlled resets

(RRESETn[31:0]). RRESETn[y] (active low) is asserted immediately after the RRSTREQ[y] bit is set to 0 or ARESETn is asserted. It is deasserted after the RRSTREQ[y] bit has been set to 1. This bit is ini-tialized when CRSTn port is asserted or software/watchdog reset occurs and its initial value is 0.ASSERT: 0, Assert requests for RRESETn[y]DEASSERT: 1, Deassert requests for RRESETn[y]



2.1.9 CRRSMReset and monitor register.

CRRSM

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

PO

RE

SET

SR

ST

SWR

STW

DR

ST

Res

erve

d

RW

RW

RW

RW

- 1 0 0 0


[3] PORESET This bit monitors a Power-On PORESETn reset. It is set only when a power on reset is asserted through PORESETn port. It is necessary to write 0 to clear this bit. This bit is initialized when PORESETn port is asserted and its initial value is 1. Writing 1 is ignored.NOTASSERTED: 0, PORESETn was not asserted.ASSERTED: 1, PORESETn was asserted.

[2] SRST This bit monitors a SRST reset from a debugging tool. It is set only when a SRST reset occurs through the XSRSTinn port. It is neces-sary to write 0 to clear this bit. This bit is initialized when PORESETn port is asserted and its initial value is 0. Writing 1 is ignored.NOTASSERTED: 0, XSRSTinn was not asserted.ASSERTED: 1, XSRSTinn was asserted.

[1] SWRST Software reset monitor. It is set only after a software reset has occurred. It is necessary to write 0 to clear this bit.NOTASSERTED: 0, Software reset was not asserted.ASSERTED: 1, Software reset was asserted.

[0] WDRST Watchdog reset monitor. This bit is set when a watchdog reset occurs. It is necessary to write 0 to clear this bit. This bit is initialized when PORESETn port is asserted and its initial value is 0. Writing 1 is ignored.NOTASSERTED: 0, Watchdog reset was not asserted.ASSERTED: 1, Watchdog reset was asserted.



2.1.10 CRCDCClock divider control register.

CRCDC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DC

HR

EQ

Res

erve

d

RW

- 0


[0] DCHREQ This bit updates the clock divider modes. If this bit is set after the CRDMx registers are set, the operation to change the clock divider modes begins and it is updated on the coincident edge of all CLKx[y] clocks. This bit is automatically cleared after the divider modes are updated. This bit is initialized when CRSTn port is asserted and its ini-tial value is 0.NOUPDATE: 0, Don't update clock divider mode.UPDATA: 1, Update clock divider mode.



2.1.11 CRDM0Clock divider mode register of CLK0.

CRDM0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0


[7:0] DIVMODEx These bits are used to set CLKx domain (gatedCLKx and CLKx[7:0]) divider modes. CLKx domain divider mode is determined using the following calcula-tion.

fCLKx = fCCLK X [(1/3)M X (1/2)N]

(where N=0~3 and M=0~3.)

fCLKx : clock frequency of CLKx domain ( gatedCLKx and CLKx[7:0]) fCCLK : clock frequency of CCLK Parameters M and N are determined according to the DIVMODEx bits. E.g. when the bitfield is set to 0x47 M = 2, N = 3 fCLKx = fCCLK X (1/72). These bits are initialized when a CRSTn port is asserted and their initial value is determined by the value of CRIDx[7:0] ports.

Note 1 : Writing access is ignored while the DCHREQ bit of the CRCDC regis-ter is high. Note 2 : When N = 0 and M = 1, 2, 3, the duty cycle of the ungatedCLKx and CLKx is NOT 50/50. Note 3 : N = 0..3, M = 0..3.

fCLKx = fCCLK x (1/1).: 0x00, fCLKx = fCCLK x (1/2).: 0x01, fCLKx = fCCLK x (1/4).: 0x03, fCLKx = fCCLK x (1/8).: 0x07, fCLKx = fCCLK x (1/16).: 0x0F, Initial valuefCLKx = fCCLK x (1/3).: 0x02, Not 50/50 duty cyclefCLKx = fCCLK x (1/6).: 0x05, fCLKx = fCCLK x (1/12).: 0x0B, fCLKx = fCCLK x (1/24).: 0x17, fCLKx = fCCLK x (1/9).: 0x08, Not 50/50 duty cyclefCLKx = fCCLK x (1/1).: 0x11, fCLKx = fCCLK x (1/36).: 0x23, fCLKx = fCCLK x (1/72).: 0x47, fCLKx = fCCLK x (1/27).: 0x1A, Not 50/50 duty cyclefCLKx = fCCLK x (1/54).: 0x35, fCLKx = fCCLK x (1/108).: 0x6B, fCLKx = fCCLK x (1/216).: 0xD7, Others: , reserved



2.1.12 CRLP0Low power control register of CLK0.

CRLP0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF

Bit Position Bit Field Name Bit Description[31:24] CENx These bits monitor the internal CENx[7:0] signal. CENx[y] is low when

CLKx[y] is stopped. These bits are initialized when CRSTn port is asserted, and the initial value is 8’b11111111. Write accesses are ignored. These are read-only bits.CLKx[y] is stopped.: 0, CLKx[y] is not stopped.: 1,

[23:16] CACTIVE_Cx These bits monitor internal CACTIVE_Cx[7:0] signals. These bits are set when the external CACTIVEx[y] port is high. These bits are initial-ized when CRSTn port is asserted, and the initial value is 8’h00. Write accesses are ignored. These are read-only bits.Low power active request is not asserted.: 0, Low power active request is asserted.: 1,

[15:8] LPOWERHSx These bits monitor internal LPOWERHSx[7:0] signals. These bits are set when the handshakes of low power interface (CSYSREQ and CSYSACK) between CRG and a peripheral on the CLKx[y] domain continues. These bits are initialized when CRSTn port is asserted, and the initial value is 8’b00000000. Write accesses are ignored. These are read-only bits.Writing access to CSYSREQ_Rx[y] is acceptable.: 0, Writing access to CSYSREQ_Rx[y] is ignored.: 1,

[7:0] CSYSREQ_Rx These bits control the clock gates of CLKx[7:0]. CLKx[y] is stopped / activated by writing access to the CSYSREQ_Rx[y] bit. CLKx[y] is also activated when a peripheral requests its clock through CACTIVE_Cx[y]. These bits are initialized when CRSTn port is asserted, and the initial value is 8’b11111111.CLKx[y] stop request.: 0, CLKx[y] active request.: 1,




CRDM1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0


[7:0] DIVMODEx These bits are used to set CLKx domain (ungatedCLKx and CLKx[7:0]) divider modes. CLKx domain divider mode is determined using the following calculation.


(where N=0~3 and M=0~3.) fCLKx : clock frequency of CLKx domain (ungatedCLKx and CLKx[7:0]) fCCLK : clock frequency of CCLK Parameters M and N are determined according to the DIVMODEx bits.

E.g. when the bitfield is set to 0x47 M = 2, N = 3 fCLKx = fCCLK X (1/72). These bits are initialized when a CRSTn port is asserted and their initial value is determined by the value of CRIDx[7:0] ports. Note 1 : Writing access is ignored while the DCHREQ bit of the CRCDC reg-ister is high. Note 2 : When N = 0 and M = 1, 2, 3, the duty cycle of the ungatedCLKx and CLKx is NOT 50/50. Note 3 : N = 0..3, M = 0..3.





CRLP1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF









CRDM2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0


[7:0] DIVMODEx These bits are used to set CLKx domain (gatedCLKx and CLKx[7:0]) divider modes. CLKx domain divider mode is determined by the fol-lowing calculation.



fCLKx : clock frequency of CLKx domain ( gatedCLKx and CLKx[7:0]) fCCLK : clock frequency of CCLK The parameter M and N are deter-mined according to the DIVMODEx bits.

E.g. when field is set to 0x47 M = 2, N = 3 fCLKx = fCCLK X (1/72). These bits are initialized when CRSTn port is asserted, and the initial value is determined by the value of CRIDx[7:0] ports. Note 1 : Writing access is ignored while the DCHREQ bit of the CRCDC register is high. Note 2 : When N = 0 and M = 1, 2, 3, the duty cycle of the gatedCLKx and CLKx is NOT 50/50. Note 3 : N = 0..3, M = 0..3.





CRLP2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF









CRDM3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0






E.g. when field is set to 0x47 M = 2, N = 3 fCLKx = fCCLK X (1/72).

These bits are initialized when CRSTn port is asserted, and the initial value is determined by the value of CRIDx[7:0] ports. Note 1 : Writing access is ignored while the DCHREQ bit of the CRCDC register is high. Note 2 : When N = 0 and M = 1, 2, 3, the duty cycle of the gatedCLKx and CLKx is NOT 50/50. Note 3 : N = 0..3, M = 0..3.





CRLP3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF









CRDM4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0












CRLP4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF









CRDM5

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0












CRLP5

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF









CRDM6

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0












CRLP6

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF









CRDM7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0












CRLP7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF









CRDM8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0












CRLP8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF









CRDM9

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0












CRLP9

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF








2.1.31 CRDMAClock divider mode register of CLKA.

CRDMA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0











2.1.32 CRLPALow power control register of CLKA.

CRLPA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF








2.1.33 CRDMBClock divider mode register of CLKB.

CRDMB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0











2.1.34 CRLPBLow power control register of CLKB.

CRLPB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF








2.1.35 CRDMCClock divider mode register of CLKC.

CRDMC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0











2.1.36 CRLPCLow power control register of CLKC.

CRLPC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF








2.1.37 CRDMDClock divider mode register of CLKD.

CRDMD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0











2.1.38 CRLPDLow power control register of CLKD.

CRLPD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF








2.1.39 CRDMEClock divider mode register of CLKE.

CRDME

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

erve

d

DIV

MO

DE

x

Res

erve

d

RW

- 0











2.1.40 CRLPELow power control register of CLKE.

CRLPE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0C

ENx

CAC

TIVE

_Cx

LPO

WE

RH

Sx

CS

YS

RE

Q_R

x

R R R RW

0xFF 0 0 0xFF







Fujitsu Semiconductor Europe GmbH MB86R12 ’Emerald

mb86r12 ’emerald-p’ mb86r12 ‘emerald-p’ register ......revised 26/8/11...

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