mb86r11 es1->es2 incompatibility and update rev.0 · clkd 0x0 800mhz (ddrclk) clke 0x3 200mhz...
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MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
All rights reserved, Copyright FUJITSU SEMICONDUCTOR LIMITED 2011
Revision History
Date Ver. Contents
2011/03/31 0.10 First release
2011/4/4 0.11 3.1.4 Compatibility method
Please set GPIO[21] external terminal to VSS(logic '0') in Emerald-L ES1.
->
Please set GPIO[21] external terminal to VSS(logic '0') in Emerald-L ES2.
3.3.4 Compatibility method
(A)Please write CRG_S.CRRRS register to 0xffffff ...
->
(A)Please write CRG_S.CRRRS register to 0xffffffff ...
Old [D15] and [D4] are integrated.
Addition new [D15] (DDR Controller).
Update [U1] description.
Delete [U15].
2011/6/15 0.13 [D5]3.5.3
Corrected figure(external terminal name,frequency).
2011/6/15 0.14 [D15]3.15.3
Added the description of the initial value.
2011/8/30 0.15 [D4]
Corrected field name
DISP_CLKSEL ->DISP_CKSEL
[D5]
Change SDIOCLK frequency.
[D15]
Delete limitations.
[D16]
Addition
[U15],[U16]
Addition
MB86R11 ES1->ES2
Incompatibility and Update
Rev.0.15
This document describes the content of the hardware failures and measures of MB86R11.
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MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
1 Incompatibility list ID Module Item
D1 Boot GPIO[21] external terminal is used by NAND Flash boot.
D2 Boot NOR Flash 32bit boot is selected when MPXMODE[2]=1'b0
D3 Reset Individual reset (RRESETn) increase 32bit.
D4 Clock Display clock select(CRG_S/CRG_P) can be individually set.
D5 Clock CRG_P/CRG_S Clock divide setting values change.
D6 Clock Clock supply sources are partly changed.
D7 Clock REFCLK multiple setting (IDIV) can be individually set by
CRG_S and CRG_P
D8 CCNT Chip ID change.
D9 External terminal Pinmux #A, #B external terminals pull-up is deleted.
D10 Pin Multiplex Pinmux #E is divided Pin multiplex #E, #J, #K, #L
D11 3D Graphics Engine Macro ID of the MID register is different.
D12 AHB Bus Unnecessary wires are deleted between masters and slaves.
D13 Pixel Engine PixelEngine register layout of fetch, store, changed
D14 Pixel Engine New dither algorithm
D15 DDR Controller Register recommended value change
Delete limitations.
D16 Clock CRG_P/CRG_S selection
2 Update list ID Module Item
U1 Boot Support Serial Flash boot.
U2 Boot Support NAND 16bit Frash boot and NAND 2GB Flash
boot.
U3 GPIO 128 GPIO ports support(125 ports support in ES1).
U4 HOST Interface HOST Interrupt external terminal added.
U5 3D Graphic Engine MSAA(Multi Sample Anti-Aliasing) function is supported.
U6 TS Interface Support STC.
U7 CAN Support IPC mode.
U8 Display/Capture Display/Capture module add some function. Please refer to
"MB86R11 Specifications"(Emerald-L(MP) part).
U9 Pin multiplex Pin multiplex #F mode6(USART4/5 SDIO0,TS(Serial), PWM,
GPIO, Ether), #H mode6(Ether) added.
U10 Command Sequencer 2 Command sequencers exists.
1 Command sequencer exists in ES1.
U11 Display Controller Add overflow/underflow detection
interrupt.
U12 3D Graphics Engine The DepthPassCount register reading and the DepthFailCount
register reading are not blocked by DDLFIFO full status.
U13 Pixel Engine Pixelengine ROP, Fetch added new features
U14 RLD Support for Toshiba format
U15 3D Graphics Engine Support Program/Uniform save and restore
U16 HS_SPI Retimed clock
[NOTE]
Eratta corrections aren't included in these list.
Please refer to "MB86R11 Eratta Sheet".
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3 Incompatibility detail
3.1 [D1] Boot(NAND Flash boot)
3.1.1 Summary
GPIO[21] external terminal is used by NAND Flash boot.
3.1.2 Emerald-L ES1
GPIO[21] external terminal is unused by NAND Flash boot.
3.1.3 Emerald-L ES2
GPIO[21] external terminal is used by NAND Flash boot.
3.1.4 Compatibility method
Please set GPIO[21] external terminal to VSS(logic '0') in Emerald-L ES2.
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3.2 [D2] Boot(NOR Flash boot)
3.2.1 Summary
NOR Flash 32bit boot is selected when MPXMODE[2]==2'b0
3.2.2 Emerald-L ES1
NOR Flash always boot 16bit mode regardless of MPXMODE[2] external terminal.
3.2.3 Emerald-L ES2
NOR Flash boot 16bit mode when MPXMODE[2] external terminal is '1'.
NOR Flash boot 32bit mode when MPXMODE[2] external terminal is '0'.
3.2.4 Compatibility method
Please set MPXMODE[2] to '1' at NOR Flash boot.
Both Emerald-L ES1 and ES2 boot in 16bit mode.
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3.3 [D3] Reset(Individual Reset)
3.3.1 Summary
Indivial reset(RRESETn) increase 32bit.
It is incompatible in the RRESETn connection.
3.3.2 Emerald-L ES1
RRESETn connection is follows.
reset modules
RRESETn[7]DDR Controller(*1,*3)
RRESETn[6]3D graphics Engine/Pixel Engine(*3)
RRESETn[5]Display0,1(*2),Display2(*3),Capture(*2),WriteBack(*2)
RRESETn[4]IrDA,USART(*5),UART,I2C,TIMER,WDT A,GPIO
,EXIRC,ADC,PWM,CAN,BC,EBC(*4)
RRESETn[3]SIG,TCON,HS_SPI,COMSEQ(*4)
RRESETn[2]I2S,WDT B,Ethernet,IDE66,Built-in SRAM(HSRAM1),HDMAC,RLD,SFI
RRESETn[1]SDIO,USB,MLB
RRESETn[0]CRG_P(*2)
*1 DDR2 /3 Contoller require CRG_P and BC.
It is necessary to release RRESETn[0] and RRESETn[4].
And please update BC module DSX0SEL register.
At system reset,DDR3 bits is '1'.
*2 It is necessary to release RRESETn[4] to change the register setting.
*3 It is necessary to release RRESETn[3] to change the register setting.
*4 The RRESETn release is necessary only that the register setting is changed
*5 USART require CRG_P.
It is necessary to release RRESETn[0].
3.3.3 Emerald-L ES2
RRESETn connection is follows.
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reset modules
RRESETn[31] USART
RRESETn[30] CAN/UART
RRESETn[29] I2C
RRESETn[28] -
RRESETn[27] -
RRESETn[26] ADC/PWM/EBC register/Display register/Capture Register
RRESETn[25] AHB0 Bridge(AHB0->other bus)
RRESETn[24] GPIO/EXIRC
RRESETn[23] TIMER/WDT_A
RRESETn[22] ADC/PWM
RRESETn[21] -
RRESETn[20]AHB2 Bus/Display2 register/ComSeq register/
PixelEngine register/DDRC register
RRESETn[19] HS_SPI
RRESETn[18] SIG
RRESETn[17] TCON
RRESETn[16] IDE66
RRESETn[15] WDT_B
RRESETn[14] Ether
RRESETn[13] I2S
RRESETn[12] SFI
RRESETn[11] RLD
RRESETn[10] HDMAC
RRESETn[9] HSRAM1
RRESETn[8] AHB1 Bus
RRESETn[7] DDR Controller
RRESETn[6] 3D Graphics Engine/Pixel Engine
RRESETn[5] Display/Capture/Writeback
RRESETn[4] IrDA
RRESETn[3] USB
RRESETn[2] SDIO I/F
RRESETn[1] MediaLB
RRESETn[0] CRG_P
*1 When you use AHB1 modules,please release RRESETn[8].
*2 When you use AHB2 modules,please release RRESETn[20].
*3 When you want to access from AHB0 masters to other bus slaves,please release RRESETn[25].
*4 If you use ADC/PWM module,please release both RRESETn[22] and RRESETn[26].
3.3.4 Compatibility method
(A)Please write CRG_S.CRRRS register to 0xffffffff instead of 0xff when you want to
release all RRESETn release.
(B)Please change the CRG_S.CRRRS value by ES1 and ES2.
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3.4 [D4] Clock(Display clock)
3.4.1 Summary
Display clock can individually select CRG_P and CRG_S.
3.4.2 Emerald-L ES1
Display Clock CRG_P/CRG_S select is controlled by SSCGCTL.CLKSEL register filed
of CCNT module.
Addre
ss SSCGCTL register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved SSRATE[9:0] SSEN SSFREC[1:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved IDIV[5:0] Reserved CLKSEL
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 - - - - - - 0 0 0 0 0 0 0 0
3.4.3 Emerald-L ES2
Display Clock CRG_P/CRG_S select is controlled by SSCGCTL.DISP_CKSEL register
fileld of CCNT module.
Addre
ss SSCGCTL register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved SSRATE[9:0] SSEN SSFREC[1:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved IDIV_P[5:0] IDIV_S[5:0] DISP_
CKSEL CLKSEL
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 - - - - - - - - - - - - 0 0
3.4.1 Compatibility method
Plese write the same value as SSCGCTL.DISP_CKSEL and SSCGCTL.CLKSEL.
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3.5 [D5] Clock(clock division setting)
3.5.1 Summary
CRG_P/CRG_S Clock divide setting values change.
3.5.2 Emerald-L ES1
1/2
1/4
1/8
1/16
ARMCLK(300-400MHz)
AXICLK(150-200MHz)
AHBCLK(75-100MHz)
APBCLK(37.5-50MHz)
DDRCLK(600-800MHz)1/n
IDIV
PSMODE(Initial )
REFCLK(CLKX0,CLKX1)20-50MHz
CRIPM(initial)
Decoder
m
Emerald
1/1
CRDMx(CRG register)
*CRDMx initial value is 1/16.Please set above value.
800-1600MHz
PLL
m:16-120 n:1,2
Set follow value.
CRDMx (CRG register) frquency(MHz)
CLK0 0x1 400MHz (ARMCLK)
CLK1 0x3 200MHz (AXICLK)
CLK2 0x3 200Mhz (AXICLK)
CLK3 0x7 100MHz (AHBCLK)
CLK4 0x7 100MHz (AHBCLK)
CLK5 0x7 100MHz (AHBCLK)
CLK6 0x7 100MHz (AHBCLK)
CLK7 0x7 100MHz (AHBCLK)
CLK8 0x3 200MHz (AXICLK)
CLK9 0xf 50MHz (APBCLK)
CLKA 0x7 100MHz (AHBCLK)
CLKB 0x0 800MHz (DDRCLK)
CLKC 0x1 400MHz (AXICLK)
CLKD 0x0 800MHz (DDRCLK)
CLKE 0x3 200MHz (AXICLK)
CLKF 0xf 50MHz (APBCLK)
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3.5.3 Emerald-L ES2
DDRCLK(600-800MHz)
DISPCLK(600-800MHz)
REFCLK(CLKX0,CLKX1)20-50MHz
1/2
1/4
1/8
ARMCLK(300-400MHz)
AXICLK(150-200MHz)
AHBCLK(75-100MHz)
APBCLK(37.5-50MHz)
IDIV
PSMODE(Initial)
CRIPM(Initial)
Decode
m
Emerald
1/n
1/8
TSCLK(50MHz)
1/8 SDIOCLK(0-50MHz)
CRDMx(CRG register)
1/1
*CRDMx initial value is 1/8.Please set above value.
1/2800MHz-1600MHz
PLL m:16-120 n:1,2
Set follow value.
CRDMx (CRG register) frquency(MHz)
CLK0 0x0 400MHz (ARMCLK)
CLK1 0x1 200MHz (AXICLK)
CLK2 0x1 200Mhz (AXICLK)
CLK3 0x3 100MHz (AHBCLK)
CLK4 0x3 100MHz (AHBCLK)
CLK5 0x3 100MHz (AHBCLK)
CLK6 0x3 100MHz (AHBCLK)
CLK7 0x3 100MHz (AHBCLK)
CLK8 0x1 200MHz (AXICLK)
CLK9 0x7 50MHz (APBCLK)
CLKA 0x3 100MHz (AHBCLK)
CLKB 0x7 50MHz (SDIOCLK)
CLKC 0x3 100MHz (AHBCLK)
CLKD 0x7 50MHz (TSCLK)
CLKE 0x1 200MHz (AXICLK)
CLKF 0x7 50MHz (APBCLK)
3.5.4 Compatibility method
Please change the CRDMx register value by ES1 and ES2.
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3.6 [D6] Clock(clock supply source)
3.6.1 Summary
Clock sources are partly changed..
3.6.1 Emerald-L ES1
Set follow table(change modules only).
module clockDisplay/Capture/WriteBack CLK1[1],CLK7[1],CLK9[1],CLKB[0]DDR Controller CLK2[4],CLK7[3],CLKC[0],CLKD[0]TS Interface CLK2[0],CLK7[6],CLK9[7]
3.6.2 Emerald-L ES2
Set follow table(change modules only).
module clockDisplay/Capture/WriteBack CLK1[1],CLK7[1],CLK9[1],DISPCLKDDR Controller CLK2[4],CLK7[3],DDRCLKTS Interface CLK2[0],CLK7[6],CLK9[7],CLKD[0]
3.6.3 Compatibility method
When you want to incompatible module clock gating,please change clock gating source
in ES1 and ES2.
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3.7 [D7] Clock(REFCLK multiple setting)
3.7.1 Summary
REFCLK multiple setting (IDIV) can be individually set by CRG_S and CRG_P.
3.7.2 Emerald-L ES1
Both CRG_P and CRG_S are controlled by SSCGCTL.IDIV bit(bit8-bit13) of CCNT module.
Addre
ss SSCGCTL register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved SSRATE[9:0] SSEN SSFREC[1:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved IDIV[5:0] Reserved CLKSEL
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 - - - - - - 0 0 0 0 0 0 0 0
3.7.3 Emerald-L ES2
CRG_P is controlled by SSCGCTL.IDIV_P bit(bit8-bit13) of CCNT module. (compatible)
CRG_S is controlled by SSCGCTL.IDIV_S bit(bit2-bit7) of CCNT module. (incompatible)
Addre
ss SSCGCTL register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved SSRATE[9:0] SSEN SSFREC[1:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved IDIV_P[5:0] IDIV_S[5:0] DISP_
CKSEL CLKSEL
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 - - - - - - - - - - - - 0 0
3.7.1 Compatibility method
Plese write the same value as SSCGCTL.IDIV_P and SSCGCTL.IDIV_S.
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3.8 [D8] CCNT(CHIP ID)
3.8.1 Summary
CHIP ID change.
3.8.2 Emerald-L ES1
CINFO register of CCNT module is 0x20100000.
3.8.3 Emerald-L ES2
CINFO register of CCNT module is 0x865211F1.
3.8.4 Compatibility method
N/A
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3.9 [D9] External terminal(Pin multiplex #A,#B pull-up)
3.9.1 Summary
Pinmux#A,#B external terminals pull-up in I/O buffer is deleted.
3.9.2 Emerald-L ES1
Pinmux#A,#B external terminals has pull-up in I/O buffer.
3.9.3 Emerald-L ES2
Pinmux#A,#B external terminals hasn't pull-up in I/O buffer.
3.9.4 Compatibility method
Please add pull-up out of the Emerald-L ES2 LSI.
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3.10 [D10] Pin muliplex(Pinmux#E divide)
3.10.1 Summary
Pinmux#E is divided pinmultiplex #E,#J,#K,#L
3.10.2 Emerald-L ES1
Follow external terminals belong to pin multiplex #E.
USART0_SIN
USART0_SOUT
USART0_SCK
USART1_SIN
USART1_SOUT
USART1_SCK
USART2_SIN
USART2_SOUT
USART2_SCK
USART3_SIN
USART3_SOUT
USART3_SCK
3.10.3 Emerald-L ES2
Follow external terminals belong to pin multiplex #E(no change).
USART0_SIN
USART0_SOUT
USART0_SCK
Follow external terminals belong to pin multiplex #J.
USART1_SIN
USART1_SOUT
USART1_SCK
Follow external terminals belong to pin multiplex #K.
USART2_SIN
USART2_SOUT
USART2_SCK
Follow external terminals belong to pin multiplex #L.
USART3_SIN
USART3_SOUT
USART3_SCK
3.10.4 Compatibility method
Plese write the same setting(pin multiplex #E, pin multiplex #J, pin multiplex #K and
pin multiplex #L).
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3.11 [D11] 3D Graphics Engine(MID)
3.11.1 Summary
Macro ID of the MID register is different.
3.11.1 Emerald-L ES1
The VER field of the MID register is Ver2.0.
3.11.2 Emerald-L ES2
The VER field of the MID register is Ver3.0.
3.11.3 Compatibility method
N/A
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3.12 [D12] AHB Bus(Sparse)
3.12.1 Summary
Unnecessary wires are deleted between masters and slaves.
3.12.2 Emerald-L ES1
NO AHB Bus access limitations.
3.12.3 Emerald-L ES2
Follow limitations exist(red character).
Level-1 Level-2 Level-3 Start Address Macro Limitation
Reserved 0xFFFF_C000 Reserved
CA9
only
Cortex-A9 Private Memory
Region 0xFFFF_A000 Cortex-A9
from Cortex-A9
only
PL310 0xFFFF_8000 PL310
AHB0 BootROM(Mirror) 0xFFFF_0000 BootROM(32KB) Can't access from
MediaLB,SDIO
AXI0
External Bus
Controller
Reserved 0xF000_0000 Reserved
ExtRAM 0xE000_0000 External RAM
Reserved 0xD120_0000 Reserved
3D Graphics
Engine 0xD100_0000 3DGE
Reserved 0xD087_0000 Reserved
Display/Capture
Reserved 0xD086_1000 Reserved
Capture 3 0xD086_0000 Capture 3
Reserved 0xD085_1000 Reserved
Capture 2 0xD085_0000 Capture 2
Reserved 0xD084_1000 Reserved
Capture 1 0xD084_0000 Capture 1
Reserved 0xD083_1000 Reserved
Capture 0 0xD083_0000 Capture 0
Reserved 0xD082_1000 Reserved
Write Back 0xD082_0000 Write Back
Reserved 0xD081_2000 Reserved
Display 1 0xD081_0000 Display 1
Reserved 0xD080_2000 Reserved
Display 0 0xD080_0000 Display 0
Reserved 0xD054_0000 Reserved
PTM 0xD050_0000 Register
Reserved 0xD041_1000 Reserved
IrDA 0xD041_0000 IrDA
Reserved 0xD040_1000 Reserved
AXI Bus 0xD040_0000 AXI Bus
PortSet Register
From Cortex-A9
only
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XDMAC 0xD030_0000 XDMAC
XSRAM
(ACP *1)
0xD020_8000 Reserved
0xD020_0000 SRAM(32KB)
Reserved 0xD010_0000 Reserved
AXI Bus 0xD000_0000 AXI Bus
Interface Register
Reserved 0xC110_0000 Reserved
XSRAM
(NO ACP *1)
0xC100_8000 Reserved
0xC100_0000 SRAM(32KB)
TS I/F 0xC000_0000 TS I/F
DDR3
(NO ACP *1) 0x8000_0000
DDR2/3
(1Gbyte)
DDR3
(ACP *1) 0x4000_0000
DDR2/3
(1Gbyte)
Reserved 0x3f07_0000 Reserved
APB0
Reserved 0x3f06_0000 Reserved
USART
USART_5 0x3f05_0000 USART_5
USART_4 0x3f04_0000 USART_4
USART_3 0x3f03_0000 USART_3
USART_2 0x3f02_0000 USART_2
USART_1 0x3f01_0000 USART_1
USART_0 0x3f00_0000 USART_0
Reserved 0x3e21_0000 Reserved
CRG_P 0x3e20_0000 CRG_P
Reserved 0x3e12_0000 Reserved
CAN CAN_1 0x3e11_0000 CAN_1
CAN_0 0x3e10_0000 CAN_0
Reserved 0x3e06_0000 Reserved
UART
UART_5 0x3e05_0000 UART_5
UART_4 0x3e04_0000 UART_4
UART_3 0x3e03_0000 UART_3
UART_2 0x3e02_0000 UART_2
UART_1 0x3e01_0000 UART_1
UART_0 0x3e00_0000 UART_0
Reserved 0x3d25_0000 Reserved
I2C
I2C_4 0x3d24_0000 I2C_4
I2C_3 0x3d23_0000 I2C_3
I2C_2 0x3d22_0000 I2C_2
I2C_1 0x3d21_0000 I2C_1
I2C_0 0x3d20_0000 I2C_0
Reserved 0x3d11_0000 Reserved
CCNT 0x3d10_0000 CCNT
Reserved 0x3d01_0000 Reserved
PMU 0x3d00_0000 PMU
Reserved 0x3c41_0000 Reserved
External Bus 0x3c40_0000 External Bus
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Controller Contoller
(Register)
Reserved 0x3c34_0000 Reserved
GCNT 0x3c30_0000 GCNT
Reserved 0x3c23_0000 Reserved
PWM
PWM_2 0x3c22_0000 PWM_2
PWM_1 0x3c21_0000 PWM_1
PWM_0 0x3c20_0000 PWM_0
Reserved 0x3c12_0000 Reserved
ADC ADC_1 0x3c11_0000 ADC_1
ADC_0 0x3c10_0000 ADC_0
Reserved 0x3b51_0000 Reserved
CRG_S 0x3b50_0000 CRG_S
Reserved 0x3b51_0000 Reserved
EXIRC EXIRC_1 0x3b41_0000 EXIRC_1
EXIRC_0 0x3b40_0000 EXIRC_0
Reserved 0x3b31_0000 Reserved
GPIO 0x3b30_0000 GPIO
Reserved 0x3b21_0000 Reserved
BC 0x3b20_0000 BC
Reserved 0x3b11_0000 Reserved
WDT A 0x3b10_0000 WDT
Reserved 0x3b01_0000 Reserved
Timers 0x3b00_0000 Timers
Reserved 0x3af2_0000 Reserved
AHB2
Reserved 0x3900_0000 Reserved
Command Sequencer 0x38F0_0000 Command Sequencer1
0x38E0_0000 Command Sequencer0
Pixel Engine 0x38C0_0000 Pixel Engine
Display 2 0x38A0_0000 Display 2
DDR Controller 0x3840_0000 DDR Controller
Reserved 0x3823_0000 Reserved
SIG
SIG_2 0x3822_0000 SIG_2
SIG_1 0x3821_0000 SIG_1
SIG_0 0x3820_0000 SIG_0
HS_SPI 0x3810_0000 HS_SPI(Register)
0x2810_0000 HS_SPI(Memory)
TCON 0x2800_0000 TCON
Reserved 0x24F2_0000 Reserved
AHB1 SFI
SFI_1
0x1700_0000 Reserved
0x1600_0000 SFI_1 Serial Flash
0x1500_0000 SFI_1 register
0x14F1_0000 Reserved
SFI_0
0x0700_0000 Reserved
0x0600_0000 SFI_0 Serial Flash
0x0500_0000 SFI_0 register
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MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
0x04F0_0000 Reserved
Reserved 0x04E4_0000 Reserved
I2S
I2S_3 0x04E3_0000 I2S_3
I2S_2 0x04E2_0000 I2S_2
I2S_1 0x04E1_0000 I2S_1
I2S_0 0x04E0_0000 I2S_0
HDMAC 0x04D0_0000 HDMAC
Can't access from
HDMAC,RLD,Ether
,IDE66
RLD 0x04C0_0000 RLD
Reserved 0x04B0_0000 Reserved
WDT B 0x04A0_0000 WDT Can't access from
Ether,IDE66
IDE66 0x0490_0000 IDE66 Can't access from
IDE66
Ethernet 0x0480_0000 Ethernet Can't access from
RLD,Ether,IDE66
HSRAM1 0x0400_8000 Reserved
0x0400_0000 SRAM(32KB)
Reserved 0x00D0_0000 Reserved
AHB0
Reserved 0x00B0_0000 Reserved
MediaLB 0x00A0_0000 MediaLB Can't access from
MediaLB
Reserved 0x0093_0000 Reserved
SDIO
SDIO 2 0x0092_0000 SDIO 2 Can't access from
SDIO2
SDIO 1 0x0091_0000 SDIO 1 Can't access from
SDIO1
SDIO 0 0x0090_0000 SDIO 0 Can't access from
SDIO0
Reserved 0x0081_5000 Reserved
USB F_USB20HF_LSP 0x0081_4400
USB2.0 Func
DMAC
Can't access from
MediaLB,SDIO,USB
0x0081_4000 USB2.0 FUNC
Reserved 0x0081_3000 Reserved
USB F_USB20HF_LSP
0x0081_2000 USB2.0
HOST_FJREG
Can't access from
MediaLB,SDIO,USB
(except USB HOST) 0x0081_1000
USB2.0
HOST_ohci
0x0081_0000 USB2.0
HOST_ehci
Reserved 0x0081_3000 Reserved
USB FASPAX_USBH
0x0080_0400 USB2.0
HOST_FJREG
Can't access from
MediaLB,SDIO,USB
0x0080_0200 USB2.0
HOST_ohci
0x0080_0000 USB2.0
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MB86R11 Incompatibility and Update
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HOST_ehci
Reserved 0x0020_0000 Reserved
HSRAM0 0x0010_8000 Reserved
0x0010_0000 SRAM(32KB)
BootROM
0x0000_8000 Reserved
0x0000_0000 BootROM(32KB) Can't access from
MediaLB,SDIO,USB
3.12.4 Compatibility method
Please don't use Emerald-ES2 access prohibition pattern.
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3.13 [D13] Pixel Engine(Register)
3.13.1 Summary
New register layout of fetch and store unit.
3.13.2 Emerald-L ES1
Please see Emerald-L ES1 specification 17.4 "Pixel Engine".
3.13.3 Emerald-L ES2
Please see Emerald-L ES2 specification 17.4 "Pixel Engine".
3.13.4 Compatibility method
New SW driver is needed, which handles the changed register addresses.
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MB86R11 Incompatibility and Update
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3.14 [D14] Pixel Engine(CLUT)
3.14.1 Summary
CLUT dither algorithm changed.
3.14.2 Emerald-L ES1
Dither algorithm present in MB86298 is implemented.
3.14.3 Emerald-L ES2
New (for the visual perception improved) dither algorithm is implemented.
3.14.4 Compatibility method
Not possible. Since ES2 brings improved perception no backward compatibility is needed.
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MB86R11 Incompatibility and Update
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3.15 [D15] DDR Controller
3.15.1 Summary
Register recommended value is changed.
Delete limitations.
3.15.2 Emerald-L ES1
Recommended value of REG_INIT4 is 0x0A0A_0A0A.
Set FFFFh to axi0_en_size_lt_width_instr of MCR_62 register (3840_00F8h), axi1_en_size_lt_width_instr
of MCR_64 register (3840_0100h), axi2_en_size_lt_width_instr of MCR_65 register (3840_0104h),
axi3_en_size_lt_width_instr of MCR_66 register (3840_0108h), and the axi4_en_size_lt_width_instr
parameter of MCR_68 register (3840_0110h) respectively.
Set the axi0_port_ordering parameter of MCR_71 register(3840_011Ch) and the axi1_port_ordering
parameter of MCR_72 register(3840_0120h), the axi2_port_ordering parameter of MCR_74
register(3840_0128h) and the axi3_port_ordering parameter of MCR_76 register(3840_0130h) by a
consecutive respectively value.
3.15.3 Emerald-L ES2
Recommended value of REG_INIT4 is 0x0808_0808.
Initial value of REG_INIT4 is 0x0A0A0A0A.
Please update above-mentioned register.
There is no necessity for setting FFFFh to axi0_en_size_lt_width_instr of MCR_62 register (3840_00F8h),
axi1_en_size_lt_width_instr of MCR_64 register (3840_0100h), axi2_en_size_lt_width_instr of MCR_65
register (3840_0104h), axi3_en_size_lt_width_instr of MCR_66 register (3840_0108h), and the
axi4_en_size_lt_width_instr parameter of MCR_68 register (3840_0110h) respectively.
There is no necessity for setting the axi0_port_ordering parameter of MCR_71 register(3840_011Ch) and the
axi1_port_ordering parameter of MCR_72 register(3840_0120h), the axi2_port_ordering parameter of
MCR_74 register(3840_0128h) and the axi3_port_ordering parameter of MCR_76 register(3840_0130h) by a
consecutive respectively value.
3.15.4 Compatibility method
Please set 0x0808_0808 to REG_INIT4 register at initialization of DDR controller module.
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MB86R11 Incompatibility and Update
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3.16 [D16] Clock(CRG_P/CRG_S Selection)
3.16.1 Summary
The clock that was able to be switched was changed.
3.16.2 Emerald-L ES1
CLK0-CLKB : CRG_P or CRG_S
CLKC-CLKF : always CRG_P
3.16.3 Emerald-L ES2
CLK0-CLKD : CRG_P or CRG_S
CLKE-CLKF : always CRG_P
(CLKE is reserved)
3.16.4 Compatibility method
Please do CLKC,CLKD setting both CRG_P and CRG_S.
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MB86R11 Incompatibility and Update
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4 Update detail
4.1 [U1] Boot(Serial Flash Boot)
Serial Flash Boot support.
When MPXMODE[1:0]==2'b11 at reset,this Serial Flash boot mode is selected.
*Only Chip select 0 can be used as a boot device.
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MB86R11 Incompatibility and Update
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4.2 [U2] Boot(16bit NAND and 2GB NAND Flash Boot)
NAND Flash boot support 16bit NAND Flash and 2GB NAND Flash
Blue:It has already been supported from Emerald-L ES1.
Red:It is newly supported in Emerald-L ES2.
exernal
terminal
bit width NAND type page size block size number of
blocks
address
bytes GPIO[21:18]
{INT_A7,INT_A6,
INT_A5,INT_A4}
4'b0000 8bits 128Mbit [SLC] 512 + 16 bytes 32 pages 1024 3
4'b1000 16bits 128Mbit [SLC] 512 + 16 bytes 32 pages 1024 3
4'b0001 8bits 256Mbit [SLC] 512 + 16 bytes 32 pages 2048 3
4'b1001 16bits 256Mbit [SLC] 512 + 16 bytes 32 pages 2048 3
4'b0010 8bits 512Mbit [SLC] 512 + 16 bytes 32 pages 4096 4
4'b1010 16bits 512Mbit [SLC] 512 + 16 bytes 32 pages 4096 4
4'b0011 8bits 1Gbit [SLC] 2048 + 64 bytes 64 pages 1024 4
4'b1011 16bits 1Gbit [SLC] 2048 + 64 bytes 64 pages 1024 4
4'b0100 8bits 1Gbit [SLC] 2048 + 64 bytes 64 pages 1024 5
4'b1100 16bits 1Gbit [SLC] 2048 + 64 bytes 64 pages 1024 5
4'b0101 8bits 8Gbit [SLC] 2048 + 64 bytes 64 pages 8192 5
4'b1101 16bits 8Gbit [SLC] 2048 + 64 bytes 64 pages 8192 5
4'b0110 8bits 16Gbit [SLC] 4096 + 128 bytes 64pages 8192 5
4'b1110 16bits 16Gbit [SLC] 4096 + 128 bytes 64pages 8192 5
4'b0111 8bits 2Gbit [SLC] 2048 + 64 bytes 64 pages 2048 5
4'b1111 16bits 2Gbit [SLC] 2048 + 64 bytes 64 pages 2048 5
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MB86R11 Incompatibility and Update
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4.3 [U3] GPIO(Supprt 128 ports)
125 GPIO ports support in ES1.(bit69, bit126-127 isn’t connected.) 128 GPIO ports support in Emerald-L ES2.
GPIO bit69,bit126-127 are arranged by pin multiplex #F mode6
USART4_SIN DISP1CLKI USART4_SIN IDE_DIORDY UART0_XCT
S
USART4_SI
NUSART4_SOUT DISP1CLKO USART4_SO
UT
IDE_DDMARQ UART1_XCT
S
USART4_S
OUTUSART4_SCK DISP1HSYNC USART4_SC
K
IDE_DD0 UART2_XCT
S
USART4_S
CKUSART5_SIN DISP1VSYNC USART5_SIN IDE_DD1 UART3_XCT
S
USART5_SI
NUSART5_SOUT DISP1CSYNC USART5_SO
UT
IDE_DD2 USART5_S
OUTUSART5_SCK DISP1DE USART5_SC
K
IDE_DD3 HS_SD0 USART5_S
CKOSDCLK0 DISP1GV OSDCLK0 IDE_DD4 HS_SD1 OSDCLK0
SD0CMD DISP1R0 SD0CMD IDE_DD5 HS_SI2 SD0CMD
SD0DAT0 DISP1R1 SD0DAT0 IDE_DD6 HS_SD3 SD0DAT0
SD0DAT1 DISP1R2 SD0DAT1 IDE_DD7 HS_SCK SD0DAT1
SD0DAT2 DISP1R3 SD0DAT2 IDE_DD8 HS_SSEL0 SD0DAT2
SD0DAT3 DISP1R4 SD0DAT3 IDE_DD9 HS_SSEL1 SD0DAT3
ISD0WP DISP1R5 ISD0WP IDE_DD10 HS_SSEL2 ISD0WP
ISD0CD DISP1R6 ISD0CD IDE_DD11 HS_SSEL3 ISD0CD
DISP1CLK DISP1R7 APIX_0_SB0 IDE_DD12 DISP1CLK
DISP1VI_0 DISP1G0 APIX_0_SB1 IDE_DD13 DISP1VI_0 TS0DATA0
DISP1VI_1 DISP1G1 APIX_0_SB2 IDE_DD14 DISP1VI_1 TS0CTL1
DISP1VI_2 DISP1G2 APIX_0_SB3 IDE_DD15 DISP1VI_2 TS0CTL2
DISP1VI_3 DISP1G3 APIX_0_SB4 IDE_DA0 DISP1VI_3 TS0CLK
DISP1VI_4 DISP1G4 APIX_0_SB5 IDE_DA1 DISP1VI_4 TS1DATA0
DISP1VI_5 DISP1G5 APIX_1_SB0 IDE_DA2 DISP1VI_5 TS1CTL1
DISP1VI_6 DISP1G6 APIX_1_SB1 IDE_XDCS0 DISP1VI_6 TS1CTL2
DISP1VI_7 DISP1G7 APIX_1_SB2 IDE_XDCS1 DISP1VI_7 TS1CLK
PWM_O6 DISP1B0 APIX_1_SB3 IDE_XDRESET PWM_O6 PWM_O6
PWM_O7 DISP1B1 APIX_1_SB4 IDE_XDIOR PWM_O7 PWM_O7
PWM_O8 DISP1B2 APIX_1_SB5 IDE_XDIOW PWM_O8 PWM_O8
I2S0_ECLK DISP1B3 I2S0_ECLK IDE_XDDMAC
K
I2S0_ECLK GPIO[69]
I2S0_SCK DISP1B4 I2S0_SCK IDE_CSEL I2S0_SCK GPIO[126]
I2S0_WS DISP1B5 I2S0_WS IDE_XIOCS16 I2S0_WS GPIO[127]
I2S0_SDI DISP1B6 I2S0_SDI IDE_XDASP I2S0_SDI TX_CLK
I2S0_SDO DISP1B7 I2S0_SDO IDE_DINTRQ I2S0_SDO RMII_CLK
I2S1_ECLK I2S1_ECLK I2S1_ECLK IDE_XCBLID I2S1_ECLK I2S1_ECLK
I2S1_SCK I2S1_SCK I2S1_SCK I2S1_SCK I2S1_SCK
I2S1_WS I2S1_WS I2S1_WS I2S1_WS I2S1_WS
I2S1_SDI I2S1_SDI I2S1_SDI I2S1_SDI I2S1_SDI
I2S1_SDO I2S1_SDO I2S1_SDO I2S1_SDO I2S1_SDO
Pin
mux #
F
US
AR
T
4
Dis
pla
y1
US
AR
T
5I2
S1
SD
IO0
I2S
1
Pinmux mode0 Pinmux mode1 Pinmux mode3 Pinmux mode4
Fun
ctio
n
Pin NamePin NameFun
ctio
n
Fun
ctio
n
I2S
1
I2S
1
DIs
pla
y1 (
YU
V)
PW
MI2
S0
I2S
0I2
S1
DIs
pla
y1 (
YU
V)
Eth
e
r
Functio
nPin NamePin Name
HS
_S
PI
IDE
66
UA
RT
FL
OW
PW
M
SD
IO/M
MC
0S
eri
al
TS
IF0
Seri
al
TS
IF1
GP
IO
Pinmux mode6
Pin Name
PW
M
Function
I2S
0A
PIX
AIC
US
AR
T
4
Pinmux mode2
Funct
ionPin Name
US
AR
T
4
US
AR
T
5S
DIO
/MM
C0
US
AR
T
5
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MB86R11 Incompatibility and Update
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4.4 [U4] HOST Interface(Interrupt)
Emerald-L ES2 can see HOST Interface interrupt by HOST_INT external terminal(pin multiplex #B
mode2).
Please refer to MB86R11 Specification Chapter 42 “42.7.3.2. Notification using HOST_INT (External
terminal)” for details.
Pinmux #B
MEM_ED16 OSDCLK1 HOST_XCS TRACECLK GPIO_0
MEM_ED17 SD1CMD HOST_DO TRACECTL GPIO_1
MEM_ED18 SD1DAT0 HOST_DI TRACEDATA0 GPIO_2
MEM_ED19 SD1DAT1 HOST_SCK TRACEDATA1 GPIO_3
MEM_ED20 SD1DAT2 HOST_INT TRACEDATA2 GPIO_4
MEM_ED21 SD1DAT3 GPIO_5 TRACEDATA3 GPIO_5
MEM_ED22 ISD1WP GPIO_6 TRACEDATA4 GPIO_6
MEM_ED23 ISD1CD GPIO_7 TRACEDATA5 GPIO_7
MEM_ED24 SPI1_HOLD GPIO_8 TRACEDATA6 GPIO_8
MEM_ED25 SPI1_DO HS_SD0 TRACEDATA7 GPIO_9
MEM_ED26 SPI1_DI HS_SD1 TRACEDATA8 GPIO_10
MEM_ED27 SPI1_SCK HS_SD2 TRACEDATA9 GPIO_11
MEM_ED28 SPI1_SS HS_SD3 TRACEDATA1
0GPIO_12
MEM_ED29 I2S3_ECLK HS_SCK TRACEDATA1
1GPIO_13
MEM_ED30 I2S3_SCK HS_SSEL0 TRACEDATA1
2GPIO_14
MEM_ED31 I2S3_WS HS_SSEL1 TRACEDATA1
3GPIO_15
MEM_XWR2 I2S3_SDI HS_SSEL2 TRACEDATA1
4GPIO_16
MEM_XWR3 I2S3_SDO HS_SSEL3 TRACEDATA1
5GPIO_17
Fun
ctio
n
Pin Name
Pinmux mode5
Pin
mu
x #
B
Extb
us
Co
ntr
oll
er
SD
IO1
PT
M
GP
IO
GP
IO
I2S
3
Pin Name
Fun
ctio
n
Pin Name
SP
I1
HS
_S
PI
HO
ST
I/F
Pinmux mode0 Pinmux
mode1
Pinmux mode2 Pinmux mode3
Fun
ctio
n
Pin Name
Fun
ctio
n
Pin Name
Fun
ctio
n
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MB86R11 Incompatibility and Update
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4.5 [U5] 3D Graphics Engine(MSAA support)
MSAA(Multi Sample Anti-Aliasing) function is supported.
Please refer to MB86R11 Specification Chapter 17 "3D Graphics Engine" for details.
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MB86R11 Incompatibility and Update
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4.6 [U6] TS Interface(STC mode support)
STC mode is supported.
Please refer to MB86R11 Specification Chapter 39 for details.
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MB86R11 Incompatibility and Update
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4.7 [U7] CAN(IPC mode)
You can select Normal mode and CAN IPC mode using CLBLCTL.CAN_MOD field of CCNT module.
Address 3d10_0100(h)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved FLOW3_
EN FLOW2_
EN FLOW1_
EN FLOW0_
EN
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved UART5_
MOD UART4_
MOD
UART3_
MOD
UART2_
MOD
UART1_
MOD
UART0_
MOD Reserved CAN_MOD[1:0] Reserved CS_
MOD
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EmeraldAPB Bus
CANCANn_TX
CANn_RX
(A)Normal
EmeraldAPB Bus
CAN
(B) Inter Processor Communication
RX
TX
TX
RX
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MB86R11 Incompatibility and Update
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4.8 [U8] Display/Capture
Display/Capture module add some function.Please refer to
"MB86R11 Specifications"(Emerald-L(MP) part).
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MB86R11 Incompatibility and Update
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4.9 [U9] Pin multiplex
Addition pin multiplex #F mode6(USART4/5 SDIO0,TS(Serial),PWM.GPIO,Ether),#H mode6(Ether).
Pinmux #F
USART4_SIN DISP1CLKI USART4_SIN IDE_DIORDY UART0_XCT
S
USART4_SI
NUSART4_SOUT DISP1CLKO USART4_SO
UT
IDE_DDMARQ UART1_XCT
S
USART4_S
OUTUSART4_SCK DISP1HSYNC USART4_SC
K
IDE_DD0 UART2_XCT
S
USART4_S
CKUSART5_SIN DISP1VSYNC USART5_SIN IDE_DD1 UART3_XCT
S
USART5_SI
NUSART5_SOUT DISP1CSYNC USART5_SO
UT
IDE_DD2 USART5_S
OUTUSART5_SCK DISP1DE USART5_SC
K
IDE_DD3 HS_SD0 USART5_S
CKOSDCLK0 DISP1GV OSDCLK0 IDE_DD4 HS_SD1 OSDCLK0
SD0CMD DISP1R0 SD0CMD IDE_DD5 HS_SI2 SD0CMD
SD0DAT0 DISP1R1 SD0DAT0 IDE_DD6 HS_SD3 SD0DAT0
SD0DAT1 DISP1R2 SD0DAT1 IDE_DD7 HS_SCK SD0DAT1
SD0DAT2 DISP1R3 SD0DAT2 IDE_DD8 HS_SSEL0 SD0DAT2
SD0DAT3 DISP1R4 SD0DAT3 IDE_DD9 HS_SSEL1 SD0DAT3
ISD0WP DISP1R5 ISD0WP IDE_DD10 HS_SSEL2 ISD0WP
ISD0CD DISP1R6 ISD0CD IDE_DD11 HS_SSEL3 ISD0CD
DISP1CLK DISP1R7 APIX_0_SB0 IDE_DD12 DISP1CLK
DISP1VI_0 DISP1G0 APIX_0_SB1 IDE_DD13 DISP1VI_0 TS0DATA0
DISP1VI_1 DISP1G1 APIX_0_SB2 IDE_DD14 DISP1VI_1 TS0CTL1
DISP1VI_2 DISP1G2 APIX_0_SB3 IDE_DD15 DISP1VI_2 TS0CTL2
DISP1VI_3 DISP1G3 APIX_0_SB4 IDE_DA0 DISP1VI_3 TS0CLK
DISP1VI_4 DISP1G4 APIX_0_SB5 IDE_DA1 DISP1VI_4 TS1DATA0
DISP1VI_5 DISP1G5 APIX_1_SB0 IDE_DA2 DISP1VI_5 TS1CTL1
DISP1VI_6 DISP1G6 APIX_1_SB1 IDE_XDCS0 DISP1VI_6 TS1CTL2
DISP1VI_7 DISP1G7 APIX_1_SB2 IDE_XDCS1 DISP1VI_7 TS1CLK
PWM_O6 DISP1B0 APIX_1_SB3 IDE_XDRESET PWM_O6 PWM_O6
PWM_O7 DISP1B1 APIX_1_SB4 IDE_XDIOR PWM_O7 PWM_O7
PWM_O8 DISP1B2 APIX_1_SB5 IDE_XDIOW PWM_O8 PWM_O8
I2S0_ECLK DISP1B3 I2S0_ECLK IDE_XDDMAC
K
I2S0_ECLK GPIO[69]
I2S0_SCK DISP1B4 I2S0_SCK IDE_CSEL I2S0_SCK GPIO[126]
I2S0_WS DISP1B5 I2S0_WS IDE_XIOCS16 I2S0_WS GPIO[127]
I2S0_SDI DISP1B6 I2S0_SDI IDE_XDASP I2S0_SDI TX_CLK
I2S0_SDO DISP1B7 I2S0_SDO IDE_DINTRQ I2S0_SDO RMII_CLK
I2S1_ECLK I2S1_ECLK I2S1_ECLK IDE_XCBLID I2S1_ECLK I2S1_ECLK
I2S1_SCK I2S1_SCK I2S1_SCK I2S1_SCK I2S1_SCK
I2S1_WS I2S1_WS I2S1_WS I2S1_WS I2S1_WS
I2S1_SDI I2S1_SDI I2S1_SDI I2S1_SDI I2S1_SDI
I2S1_SDO I2S1_SDO I2S1_SDO I2S1_SDO I2S1_SDO
Pin
mux #
F
US
AR
T
4
Dis
pla
y1
US
AR
T
5I2
S1
SD
IO0
I2S
1
Pinmux mode0 Pinmux mode1 Pinmux mode3 Pinmux mode4
Fun
ctio
n
Pin NamePin NameFun
ctio
n
Fun
ctio
n
I2S
1
I2S
1
DIs
pla
y1 (
YU
V)
PW
MI2
S0
I2S
0I2
S1
DIs
pla
y1 (
YU
V)
Eth
e
r
Functio
nPin NamePin Name
HS
_S
PI
IDE
66
UA
RT
FL
OW
PW
M
SD
IO/M
MC
0S
eri
al
TS
IF0
Seri
al
TS
IF1
GP
IO
Pinmux mode6
Pin Name
PW
M
Function
I2S
0A
PIX
AIC
US
AR
T
4
Pinmux mode2
Funct
ionPin Name
US
AR
T
4
US
AR
T
5S
DIO
/MM
C0
US
AR
T
5
Pinmux #H
34
MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
CAP3CLK GPIO_70 TSDATA0 TRACECLK GPIO_70 TXD0
CAP3VI_0 GPIO_71 TS0DATA0 TSDATA1 TRACECTL GPIO_71 TXD1
CAP3VI_1 GPIO_72 TS0CTL1 TSDATA2 TRACEDATA0 GPIO_72 TXD2
CAP3VI_2 GPIO_73 TS0CTL2 TSDATA3 TRACEDATA1 GPIO_73 TXD3
CAP3VI_3 CAP1VS TS0CLK TSDATA4 TRACEDATA2 GPIO_74 TX_EN
CAP3VI_4 CAP1HS TS1DATA0 TSDATA5 TRACEDATA3 GPIO_75 TX_ER
CAP3VI_5 CAP1CLK TS1CTL1 TSDATA6 TRACEDATA4 GPIO_76 CRS
CAP3VI_6 CAP1R0 TS1CTL2 TSDATA7 TRACEDATA5 GPIO_77 COL
CAP3VI_7 CAP1R1 TS1CLK TSCTL1 TRACEDATA6 GPIO_78 RX_DV
CAP2CLK CAP1R2 CAP2CLK TSCTL2 TRACEDATA7 GPIO_79 RXD0
CAP2VI_0 CAP1R3 CAP2VI_0 TSCLK TRACEDATA8 GPIO_80 RXD1
CAP2VI_1 CAP1R4 CAP2VI_1 I2S2_ECLK TRACEDATA9 GPIO_81 RXD2
CAP2VI_2 CAP1R5 CAP2VI_2 I2S2_SCK TRACEDATA1
0
GPIO_82 RXD3
CAP2VI_3 CAP1G0 CAP2VI_3 I2S2_WS TRACEDATA1
1
GPIO_83 RX_CLK
CAP2VI_4 CAP1G1 CAP2VI_4 I2S2_SDI TRACEDATA1
2
GPIO_84 RX_ER
CAP2VI_5 CAP1G2 CAP2VI_5 I2S2_SDO TRACEDATA1
3
GPIO_85 MDC
CAP2VI_6 CAP1G3 CAP2VI_6 GPIO[86] TRACEDATA1
4
GPIO_86 MDIO
CAP2VI_7 CAP1G4 CAP2VI_7 GPIO[87] TRACEDATA1
5
GPIO_87 OSC_CLK
Pinmux mode6
Pin Name
Eth
er
Func
tionP
inm
ux #
H
Cap
utu
re3
(YU
V) GP
IO
TS
(pa
rra
lle
l)
PT
M
Cap
utu
re2
(YU
V)
Pin NameFunc
tion
GP
IO
TS
(se
ria
l0)
Pin NameFunc
tion
Pinmux mode4 Pinmux mode5
Pin NameFunc
tionPin Name
Func
tionPin Name
Func
tionPin Name
Func
tion
Pinmux mode0 Pinmux mode1 Pinmux mode2 Pinmux mode3
Cap
utu
re1
(RG
B66
6) T
S(s
eri
al1
)C
ap
utu
re2
(YU
V)
I2S
2G
PIO
35
MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
4.10 [U10] Command Sequencer
1 more command sequencer added.
BaseAddr=0x38F0_0000
36
MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
4.11 [U11] Display Controller(Interrupt)
Cortex-A9 SPI interrupt #25 add(over/under flow detection interrupt).
37
MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
4.12 [U12] 3D Graphics Engine(Register access)
The DepthPassCount register reading and the DepthFailCount register reading are not blocked by
DDLFIFO full status.
38
MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
4.13 [U13] Pixel Engine
Pixel Engine added new functions:
Fetch:
New gamma correction stages.
Support of additional run length coded format.
Changed increments in non rotation fetch units from 1 to deltas given as s3.2 .
Added FIR2 and FIR4 operation modes for rotation fetch.
Performance improvements.
Rop:
new ADD mode.
39
MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
4.14 [U14] RLD
Support of additional run length coded format (Toshiba style).
40
MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
4.15 [U15] 3D Graphics Engine(SaveRestoreReg)
Unified shader Program and Uniform can save and restore.
Please refer to Emerald-L ES2 specification "17.2 3D Graphics Engine"(SaveRestoreReg Displaylist
description) for details.
41
MB86R11 Incompatibility and Update
FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL
4.16 [U16] HS_SPI(Retimed clock)
Retimed clock support in Emerald-L ES2.
Emerald-L(ES1) : HSSPI_PCCx bit3 is reserved(must be 0).
Emerald-L(ES1) : HSSPI_PCCx bit3 is RTM.