VLSI M.E PROJECTS1. High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for

Ultra-HD HEVC Video Encoding

2. Graph-Based Transistor Network Generation Method for Super gate Design

3. Fault Tolerant Parallel Ffts Using Error Correction Codes And Parseval Checks

4. Recursive Approach to the Design of a Parallel Self-Timed Adder

5. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique

for DSRC Applications

6. Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block

7. A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler

8. An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional

Probability

9. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology,

and Implementations

10. Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm

11. Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial

Solutions

12. Fast Sign Detection Algorithm for the RNS Moduli Set

13. Functional Constraint Extraction From Register Transfer Level for ATPG

14. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

15. Flexible Low Complexity Uniform and Non uniform Digital Filter Banks with High

Frequency Resolution for Multi standard Radios

16. A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks

17. A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator

18. Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design

Methodology

19. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

20. Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive

Cryptographic Applications

21. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

22. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

23. Design for Testability of Sleep Convention Logic

24. High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for

Ultra-HD HEVC Video Encoding

25. Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and

Vedic Multiplication

26. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

27. Network-on-Chip for Turbo Decoders

28. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

29. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on

Extended Double Base Number System

30. One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes

31. A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable

Orthogonal Approximation of DCT

32. Read Performance: The Newest Barrier in Scaled STT-RAM

33. Power and Bandwidth Scalable 10-b 30-MS/s SAR ADC

34. Low-Power Programmable PRPG With Test Compression Capabilities

35. An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation

36. Energy-Efficient Approximate Multiplication for Digital Signal Processing and

Classification Applications

37. A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on Radix-2

Decimation-In-Frequency Algorithm

38. Trade-offs for Threshold Implementations Illustrated on AES

39. Robust Learning based Camera Motion Characterization scheme with applications to

Video Stabilization

40. Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-

Advanced

41. Algorithm and Architecture Design of the H.265/HEVC Intra Encoder

42. Area-Efficient Fixed-Width Squarer with Dynamic Error-Compensation Circuit

43. A Novel Wavefront-Based High Parallel Solution for HEVC

44. Low Energy yet Reliable Data Communication Scheme for Networks on Chip

45. A Proportionate Diffusion LMS Algorithm for Sparse Distributed Estimation

46. Lossless and Reversible Data Hiding in Encrypted Images with Public Key Cryptography

47. Efficient Coding Schemes for Fault Tolerant Parallel Filters

48. Architecture Design of the H.264/AVC Encoder based on Rate-Distortion Optimization

49. Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded

Processor

50. Reversible Data Hiding in Encrypted Image with Distributed Source Encoding

51. A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM

52. A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based

Reconfigurable Architectures

53. Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO

Wireless Communications With Convolutional Codes

54. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

55. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of

Supply Voltage Levels

56. Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and

Vedic Multiplication

57. Low-Complexity High-Throughput QR Decomposition Design for MIMO Systems

58. Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors

59. High-Throughput Trellis Processor for Multistandard FEC Decoding

60. High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for

Ultra-HD HEVC Video Encoding

61. An Efficient List Decoder Architecture for Polar Codes

62. Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design

Methodology

63. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

64. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

65. Combining Image Processing and Laser Fault Injections for Characterizing a Hardware

AES

66. Novel Approach to Protect Advanced Encryption Standard Algorithm Implementation

Against

Differential Electromagnetic and Power Analysis

67. High throughput and secure advanced encryption standard on field programmable

gate array

with fine pipelining and enhanced key expansion

68. An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary

Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

69. Optimal Factoring of FIR Filters

70. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on

Extended Double Base Number System

71. Design of Sparse FIR Filters With Joint Optimization of Sparsity and Filter Order

72. An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation