max5871 evaluation kit - evaluates: max5871 · labtools\labtools\bin\nt. double-click on the file...

$: MAX5871 Evaluation Kit - Evaluates: MAX5871 · LabTools\LabTools\bin\nt. Double-click on the file impact.exe ii. For 64-bit operating system C:\Xilinx\14.7\ LabTools\LabTools\bin\nt64$
Evaluates: MAX5871MAX5871 Evaluation Kit

General DescriptionThe MAX5871 evaluation kit (EV kit) contains a single MAX5871 high-performance interpolating and modulating 16-bit 5.9Gsps RF DAC that can directly synthesize up to 600MHz of instantaneous bandwidth from DC to frequencies greater than 2.8GHz. The device is optimized for direct RF synthesis of single and multicarrier transmit signals in wireless communications applications. The MAX5871 meets spectral mask requirements of a wide range of communication standards, including MC GSM, UMTS, and LTE. The EV Kit provides a complete system for evaluating the performance of the MAX5871 and a platform for system development.The EV kit connects to one FMC connector on the Xilinx® VC707 evaluation kit, allowing the VC707 to communicate with the MAX5871’s JESD204B serial link interface.The EV kit includes Windows® 7/8 and Windows XP®-compatible software that provides a simple graphical user interface (GUI) for configuration of all of the MAX5871 registers through the SPI interface, control of the VC707 FPGA, and temperature monitoring.

Features ● Evaluates MAX5871 RF DAC Performance,

Capability and Feature Set ● Single 3.3V Input Voltage Supply ● Maximum 5.9Gsps Update Rate ● Direct Interface with Xilinx VC707 Data Source Board ● Windows 7/8 and Windows XP-Compatible Software ● On-Board SPI Interface Control for the MAX5871 ● On-Board SMBus™ Interface Control for the

MAX6654 Temperature Sensor ● GUI Controls for VC707 Operation ● Proven 10-Layer PCB Design ● Fully Assembled and Tested

19-8534; Rev 0; 5/16

Ordering Information appears at end of data sheet.

Windows is a registered trademark and registered service mark of Microsoft Corporation.Windows XP is a registered trademark and registered service mark of Microsoft Corporation.Xilinx is a registered trademark of Xilinx.

Maxim Integrated │ 2www.maximintegrated.com


Figure 1. MAX5871/VC707 Evaluation Setup

VC707 EVALUATION KIT MAX5871 EVALUATION KIT



Quick StartRequired Equipment

● Window PC (Win-7 Recommended, Win-XP, Win-8 optional), with one USB 2.0

● Spectrum Analyzer – Agilent PXA or equivalent ● RF signal generator – Rohde & Schwarz SMF100A

or equivalent ● 3.3V, 3A power supply for MAX5871 EV Kit ● Xilinx VC707 Evaluation Kit—user-supplied

• VC707 board• 12V/5A power cube• 1 each USB-A to Mini-B cable for interfacing and

programming• 1 each USB-A to Micro-B cable for interfacing and

programming ● Low-loss SMA/SMA cables, as needed for connections

to the spectrum analyzer and signal generator ● Included in the MAX5871 EV kit

• Two 1” stand-offs with screws • MAX5871 EV kit board• 4-port USB-powered hub • Two USB-A to Mini-B cables, additional one for the

VC707 and one for MAX5871 EV kit board• USB thumb drive with documentation and all

required software• Quick start guide

Required Installed Software and DriversThe MAX5871EVKIT software controller application requires the following drivers and software components to be installed:

● Xilinx ISE 14.7 LabTools Installation: Browse the Xilinx folder on the thumb drive and run the LabTools Installation program. Lab Tools is a free tool set used for programming the VC707 Evaluation Board, no software registration or license is required. Alternatively, LabTools can be downloaded from the following location: http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html

● Xilinx Drivers Installation: Browse to the Xilinx folder created during the installation of LabTools: C:\Xilinx\14.7\LabTools\LabTools\bin\nt (or nt64). Execute the install_drivers.exe application

● Silicon Labs Driver Installation: Browse to the SiLabs folder on the thumb drive and run the installation program for the CP210X Driver for the Windows Platform. Alternatively, the driver and instructions for installation can be accessed at the following location: https://www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx

If the above files have not been installed, please allow up to 30 minutes for installation. These files are included on the USB thumb drive provided with the MAX5871 EV kit.

Procedure1) Install the MAX5871 EV kit Software

• The MAX5871 EV kit software controller application is included on the USB thumb drive delivered with the EV kit. Insert the thumb drive to a USB port on the target PC with a Win 7 or Win 8 OS. Access the MAX5871 Setup folder on the thumb drive and double-click the MAX5871EVK Setup.exe file to install the software. Several files and folders are created during installation; the general descriptions of these are provided in Table 1.

• The installation routine requires the user to accept Maxim’s End-User License Agreement in order to proceed. Upon completion of the installation, a shortcut will be added to the Start Menu (Start -> MaximIntegrated -> MAX5871EVKITSoftwareCon-troller) as well as to the user’s desktop. Additionally, a short-cut to both the installation folder and the application will be placed on the user’s desktop. This step should take less than 5 minutes.

2) Setup and Connect the MAX5871 board (refer to Figure 1)a. Install the two 1” stand-offs included with the

MAX5871 EV kit. Stand-offs should be installed on the DAC output side of the board.

b. Verify all jumpers on the MAX5871 EV kit PCB are in the default position; refer to Table 2.

c. Connect the MAX5871 EV kit board to the VC707 board HPC1 FMC connector.

d. Connect the 3.3V/3A supply to the MAX5871 EV kit and enable the output. Verify the four LED board supply indicators are on and green.

http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html

http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html

https://www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx

https://www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx



e. Connect the RF generator to the clock module with a low-loss SMA cable, set the frequency to 2.5GHz with output power at +3dBm.

f. Turn on the VC707 by sliding switch SW12 to the on (left) position. Verify all LEDs on the VC707 are on momentarily; the GPIO LEDs should then begin sequencing.

g. Make the USB connections using the 4-port USB2.0 hub.i. Connect the USB A–Mini B cable from the

MAX5871 mini USB to the hub.ii. Connect the USB A–micro B cable (JTAG)

from Xilinx VC707 Eval board to the hub.iii. Connect the USB A–micro B cable (USB2.0)

from Xilinx VC707 eval board to the hub.iv. Connect the USB A –mini B (UART) from

Xilinx VC707 Eval board to the hub.v. Connect the power cube for the USB hub

and plug into an appropriate outlet.vi. Connect the USB hub to the PC.

Please ensure that all the USB device drivers are installed and ‘ready for use’ (this may take several minutes, depending on the system) before proceeding to the next step. The drivers will typically install automatically when the USB connection is first made on a given port. The FTDI device on the MAX5871 EV kit is recognized as four separate USB devices and four separate COM ports, and the driver must be installed for each device and port. The Windows OS reports new device arrivals in the Notification Area of the Task Bar.

Table 1. Installed Files and FoldersFILE DECRIPTION

MAX5871EVKITSoftwareController.exe Application program

AppFiles Directory with application support files including the USB_MS_Bulk_Transfer driver

DeviceScripts Directory with sample MAX5871 configuration scripts and Perl scripts for generating additional scripts

DeviceScripts\PERL Directory with Perl scripts and supporting files to generate new configuration files to load into the MAX5871

PatternFiles Directory with sample pattern files and Matlab routines for generating additional CW patterns

VC707Files Directory with FPGA programming file and supporting documentation

EVKIT Info Directory with PCB design details and automation support document

EULA.rtf End-User License Agreement

Miscellaneous DLLs to include ftd2xx.dll, DTD2XX_NET.dll, libMPSSE.dll and MaximStyle.dll Supporting DLL files for software operation



3) Start the MAX5871EVKITSoftwareController.exe located in the C:\MaximIntegrated\MAX5871 folder. The Splash Screen will display while the USB connections are established, followed by the Main GUI Startup screen.

4) Load the FPGA configurationa. Select the <VC707> tab.b. Click on the Xilinx Impact Tool Installed checkbox.

A file browser window will open. Locate the directory where the impact.exe program is located. If the default installation location is used for the Xilinx Lab Tools installation, the path will be:i. For 32-bit operating system C:\Xilinx\14.7\

LabTools\LabTools\bin\nt. Double-click on the file impact.exe

ii. For 64-bit operating system C:\Xilinx\14.7\LabTools\LabTools\bin\nt64. Double-click on the file impact.exe

c. Click the <Load FPGA Configuration File> button.d. A file browser will open in the C:\maximintegrated\

MAX5871\VC707Files folder. Double-click the MAX5871_DataSource.bit file.

e. A progress bar will display while the FPGA is configured (should take less than 2 minutes).

f. After completing the FPGA configuration, the PC will establish a connection to the new USB2.0 port on the FPGA. It should appear as a USB Mass Storage Device in the Device Manager.

g. After allowing the connection to complete, select the USB Mass Storage Device in the Device Manager and right-click to select the Update Driver Option. NOTE: Ensure the USB thumb drive has been ejected before proceeding.i. Select Browse My Computer for driver software.ii. Select Let Me Pick from a list of devices on

My Computer.iii. Select the USB Mass Storage Device, then

click the <Have Disk> button.iv. Click the <Browse> button in the Load from

Disk pop up window.v. Browse to C:\MaximIntegrated\MAX5871\

AppFiles\ThirdParty\USB_MS_Bulk_Transfer and select the USB_MS_Bulk_Transfer.inf file.

h. The arrival of the new device will appear in the Log window located at the bottom of the GUI as highlighted in Figure 2.

Table 2. MAX5871 EV Kit Jumper Settings

*Default position.

JUMPER POSITION EVKIT FUNCTIONJU1 Not Installed* Normal Operation

JU2 Installed* 1.0V LDO drives MAX5871: AVCLK, AVDD1_PLL, AVDD

JU3 Installed* 1.8V LDO drives MAX5871: AVCLK2, AVDD2, RVDD2, AVDD2PLL, VDD2

JU4 InstalledNot Installed*

Power for U4—MAX6161—external referenceMAX6161 NOT powered

JU5 InstalledNot Installed*

MAX5871 external reference connectedMAX5871 using internal reference

H3 1-2*,4-5*,7-8*,10-11*2-3,5-6,8-9,11-12

SCLK, SDI, SDO, CSA pins connected to USBSCLK, SDI, SDO, CSA pins connected to FPGA

H6 2-3*,5-6*,8-9*1-2,4-5,7-8

INTB, MUTE, RESETB connected to USBINTB, MUTE, RESETB connected to FPGA

H7 2-3*,5-6*,8-9*1-2,4-5,7-8

SCL, SDA, ALERT (I2C) connected to USBSCL, SDA, ALERT (I2C) connected to FPGA



Figure 2. New Device Arrival



5) Initial Setup is now complete. It is recommended to reboot the PC at this time. Power off the EV kit, the VC707, the clock source and disconnect the USB hub (power and PC connections) before restarting the system.

6) Setup the MAX5871 Evaluation System after the PC has restarted.a. Set the RF Generator to the desired input clock

frequency (e.g., 737.28MHz, refer to Table 3) and the power to +3dBm, DO NOT ENABLE the RF output yet.

b. Connect the DAC output to the spectrum analyzer.c. Enable the 3.3V power supply. Verify the four

LED board supply indicators are on and green.d. Enable the RF generator output.e. Turn on the VC707 by sliding switch SW12 to

the on (left) position.f. Verify all LEDs on the VC707 are lit, and the

GPIO LEDs are sequencing. g. Reconnect the USB hub (power and PC connections).

7) Start MAX5871EVKITSoftwareController.exe located

in the C:\MaximIntegrated\MAX5871 folder.a. Verify that the lower-left corner of the app states

either “Connected” or “FT4232H Device A for MAX5871EVKIT”; Indicates the GUI is connected to the MAX5871 EV kit. (Figure 5)

b. Verify lower-right corner of the app states “SPI, I2C connected-FPGA Connected” indicating these specific ports have been established.(Figure 5)

NOTE: These notifications must be present before proceeding, and indicates that the JTAG, UART, and EV kit interfaces are connected and operating properly. With this release, these items do no show real time status, but only status at startup.

8) Click the <Load Settings> button on the <Setup> tab of the GUI. Select one of the sample configura-tions from Table 3 (e.g. fDo5898_fC737_I8x_fDi737_J4L7G_RCd4_SC1_DC0.cfg).

Table 3. Example (Preset) Device Configurations

FILE NAME

DAC JESD204B

OU

TPU

T U

PDAT

E R

ATE

(Gsp

s)

INPU

T C

LOC

K

FREQ

UEN

CY

(MH

z)

PLL

MU

LTIP

LIER

/ IN

TER

POLA

TIO

N

RAT

E

INPU

T SA

MPL

E R

ATE

(Msp

s)

RC

LK D

IVID

ER

LAN

E R

ATE

(Gbp

s)

NO

. OF

LAN

ES

SUB

-CLA

SS

RXL

INK

CLO

CK

fDo4915_fC307_I16x_fDi307_J4L3p1G_RCd2_SC1_DC0.cfg 4.9152 307.2 16 307.2 2 3.072 4 1 DSP

fDo4915_fC614_I8x_fDi614_J4L6G_RCd4_SC1_DC0.cfg 4.9152 614.4 8 614.4 4 6.144 4 1 DSP







9) Select the <Clock and NCO> tab. Setup the GUI to match the requirements for the previously selected .cfg file. For this example:a. Click the <PLL ENABLE> button.b. Select 737.28 in the fCLK dropdown box.c. Select 8 in the multiplier dropdown box.d. Select 8 in the Interpolation Rate dropdown box.e. Select 4 in the RCLK Divide dropdown box.f. Click the <Apply Settings> button. The fDAC

text box should update with the value of 5.89824GHz. The fRCLK text box should update with the value of 184.32MHz.

10) Configure the NCO frequency – center frequency for DAC output signals.a. Enter the desired center frequency in the Target

fNCO text box.b. Click the <Calculate Values> button. The CfgFNCO

box should update with an 8 character hex value.c. Click the <Apply Values> button. The fNCO text

box should update with the programmed center frequency.

11) Select the <VC707> tab in the GUIa. Click the Xilinx Impact Tool Installed check box.b. Click the <Load FPGA Configuration File> button.

i. A file browser opens in the VC707 folder.ii. Select the MAX5871_DataSource.bit file

and click the <Open> button.iii. After loading, the GUI should look like

Figure 2, above.c. Select 411 in the Lane Configuration box.

d. Select 7.3 in the Lane Rate (Gbps) box.e. Click the <Load Pattern List> button in the

Pattern Control box.i. Select patListFile.txt in the file browser and

click <Open>.f. Select the appropriate pattern (e.g.,

2ToneSpc1M_737p28Msps_m1dBFS) in the drop-down box.

g. Click the <Start Pattern> button.12) Enable the DAC Output

a. Select the <Setup> tab.b. Uncheck the <Hardware Mute> and <Software

Mute> buttons.c. Observe the signals for the loaded pattern,

centered at fNCO on the spectrum analyzer.13) In order to change the center frequency select the

<Clock and NCO> tab and repeat step 10).14) In order to change the DAC configuration or load

new patterns:a. Select the <VC707> tab and click the <Stop Pattern>

button.b. Repeat steps 6) thru 9) for new configurations.c. Repeat steps 9e) thru 9g) for a new pattern list.

Refer to the Test Pattern Lists and Files section for details regarding the creation of custom patterns and lists. The Custom Configurations section contains a detailed procedure for creating configuration files.



Detailed Description of SoftwareThe MAX5871 EV kit software controller GUI is designed to control the EV kit and the VC707 board, as shown in Figure 3. The MAX5871 EV kit software controller includes USB controls that provide SPI and SMBus communication to

the MAX5871 and the MAX6654 interfaces. The software also controls the VC707 through the Silicon Labs COM port on the VC707 board (UART connection on the board panel). The BULK port (USB2.0 in Figure 3) is used for the transfer of patterns to the VC707 on board memory.

Figure 3. MAX5871 EV System Block Diagram

FTDI 4232H

INTERFACEPOWER SUPPLY

CIRCUITRY

MAX6161Reference

MAX6654Temp

sensor

MAX5871RF

DAC

USB

REQUIRED SUPPLY

3.3V/3A

MAX5871 EVKITXILINX VC707EVALUATION KIT

USB USB

POWER

REQUIRED SUPPLY

12V/5A

Virtex – 7

FPGA

CLK

OUT

PC/Laptop

FMC

SIGNAL GENERATOR SUCH ASROHDE & SCHWARZ

SMF100RF-GENERATOR

SPECTRUMANALYZER

(AGILENT PXA)OR

(AGILENT PSA)OR

(ROHDE SCHWARZFSU)

FMCFMC

1KB EEPROM 1GB DDR3MEMORY

128 MB Linear BPI

Flash Memory

USB 2.0ULPI PHY

USB-to-UARTBRIDGE

LCD Display2 lines x 16 Char

Differential ClockGTX SMA Clock

User SwitchesButtons & LED’s

HDMI VideoInterface

DIP SwitchConfig andFlash Addr

JTAG InterfaceMini-B

USB Connector

FMC CONNECTORS

HPC/HPC

8-Lane PCI Express

Edge Connector10/100/1000

EthernetInterface

XADC Header

USB2.0

USB2.0



MAX5871 EV Kit Software ControllerThe EV kit software controller GUI application displays a splash screen on initial startup, as shown in Figure 4. The splash screen is only visible while the application connects to the EV Kit USB interface and the UART on the VC707. The main application is displayed after these connections are made, as shown in Figure 5. Note that the EV kit connection status is reported in the lower left corner of the GUI. The lower-right corner reports the SPI and I2C/SMBus along with the FPGA connections.The EV kit software controller features five window tabs for configuration and control of the MAX5871 and the VC707. The specific tabs are:

● Setup• Load and reload MAX5871 configurations• Hardware and software MUTE control• Various reset functions

● Clock and NCO• Clock configuration• NCO configuration

● VC707• Com port connection reporting• FPGA programming• MicroBlaze command line execution• FPGA lane configuration and rate selection• Pattern loading and control

● Status• Temperature readings and control of the MAX6654

temperature sensor IC• Automation support through TCP/IP port

● Register Access• User access to read/write MAX5871 configuration

and status registers

Figure 4. Splash Screen



Figure 5. Main GUI Startup



The application will not display the main window if the required EV Kit connections are not complete. If the EV kit has not been properly identified, the pop-up window shown in Figure 6a will appear. The pop-up window in

Figure 6b appears when the application does not detect a properly configured FTDI FT4232 device. The Device Manager application of the Windows OS can be used to monitor the connections if desired.

Figure 6. Error in Locating MAX5871EV Kit and in Locating FT4232 Device



Clicking the OK button for either or both of these pop-up windows will cause the MAX5871EVKIT Software Controller Setup window to appear as shown in Figure 7. If desired, the <Demonstration Mode> button can be clicked to enter the SW GUI. Of course, there isn’t a board to connect to and therefore no configuration can take place. If demonstration mode is used, the GUI will display with the appropriate “DEMONSTRATION MODE” title and “Not Connected” and “Adapter: None” messages, as shown in Figure 8.

Setup TabThe Setup tab (Figure 5) allows the user to load a MAX5871 device configuration file. The configuration contains a specific sequence of SPI register writes required for proper operation of the desired operating mode. Several sample configuration files are included with the software installation and are stored in the

MAX5871/DeviceScripts folder. Clicking the <Load Settings> button will cause a file selection window to open in the DeviceScripts directory. The user then selects the .cfg file of their choice. Clicking the <Open> button causes the software to assert, and then clear, a <HARDWARE RESET> prior to transferring the configuration to the MAX5871. The various control buttons on the Setup tab include the <HARDWARE MUTE>, which is asserted at startup and controlled through the GPIO, as well as <SOFTWARE MUTE>, which is asserted through register control every time a new configuration is loaded. The <MUTE> controls are used to protect downstream equipment or devices while the device is configured and prior to the generation of valid test signals. Additional controls include <GLOBAL RESET> and <FIFO RESET>. These controls are NOT normally required; however, the FIFO reset may be required after initially starting a test pattern in order to clear FIFO errors.

Figure 7. SPI Adapter Setup Window



Figure 8. Demonstration Mode Startup



Clock and NCO TabThe clock and NCO tab (Figure 9) provides the controls required to configure the DAC output update rate and the NCO frequency. The MAX5871 operates normally with a very limited number of discrete update rates. The GUI

automatically populates the selections for configuring the clock based on the mode of operation. Should the user desire, the GUI provides an option to <Override Defaults>. Using this option is NOT recommended; contact the factory for additional support if this mode is desired.

Figure 9. Clock and NCO Tab



The clock configuration section provides the controls needed to configure the DAC update rate. The clocking mode, PLL ENABLED or BYPASS, determines the frequency requirements for the clock signal applied to the EV Kit. Using the PLL ENABLE mode will populate the fCLK selection box with a list of the supported reference frequencies, and the BYPASS mode will populate the list with the allowed DAC update rates. The clock frequency applied to the EVKIT should match the selected value.The PLL Multiplier selection box will populate with the allowable options based on the fCLK frequency selected. Options range from a minimum of 1 for use only in the BYPASS mode, to a maximum of 60 for use with the lowest reference frequency.The Interpolation Rate selection box populates based on the fCLK and PLL Multiplier selections. The MAX5871 supports 5x, 6x, 6.67x, 8x, 10x, 12x, 13.33x, 16x, 20x, and 24x interpolation. The RCLK Divider selection includes options for divide by 1, 2, or 4. The input sample rate is deter-mined by dividing the DAC output update rate by the interpolation rate. The MAX5871 supports input sample rates of 245.76MHz, 307.2MHz, 368.64MHz, 491.52MHz, 614.4MHz, and 737.28MHz. The RCLK frequency is equal to the input sample rate when the divide by 1 option is selected. However, the VC707 firmware requires a specific RCLK frequency based on the input sample rate. Valid frequencies for the RCLK output are: 153.6MHz, 184.32MHz, or 245.76MHz, so the RCLK divide value should be chosen accordingly.Clicking the <Apply Settings> button will update the MAX5871 registers to match the desired DAC update rate, PLL mode and RCLK output frequencies. The fDAC and fRCLK text boxes will update with the calculated frequencies based on the users selections.The NCO configuration box contains all the controls required to configure the operation of the NCO used in the digital modulator block of the MAX5871. First, the desired center frequency for the output signal is entered in the text box labeled Target fNCO. Next, the user needs to determine how they would like the NCO frequency to update. Two

options are available for the method of changing NCO frequencies: Immediate or Increment/Decrement. The Immediate mode provides the fastest switching response time and requires no additional user inputs before applying the calculated values. However, it may create a glitch at the DAC output which may or may not be an issue when lab testing. The Increment/Decrement option is glitch free and causes the NCO to change frequencies based on the step size programmed by the user. A text entry box will appear when selecting this option, which allows the user to enter the step size to be used when changing the NCO fre-quency. The NCO will step towards the new value, with one step for every 8 fDAC cycles. A specific example is shown here:Example:FCW-old = 0x80000000FCW-new = 0x80008000CfgNCOUS = 0x000010Once the NCO update is issued, it takes (0x80008000-0x80000000)/0x000010 cycles of DAC Clock /8 which is a total of 2048 x 8 = 16384 DAC clocks.The GUI also provides controls to access the PLLs Fractional or Extended mode. Extended mode is enabled with the Extended NCO Enable toggle button. When this mode is enabled, the Resolution selection box will appear as shown in Figure 9. The available resolution settings are 10kHz, 1kHz, 100Hz, 10Hz, and 1Hz. Additonally, the CfgNCON and CfgNCOD reporting boxes are added below the CfgFNCO text box.Clicking the <Calculate Values> button will update the CfgFNCO and, when enabled, the extended mode numerator (CfgNCON) and denominator(CfgNCOD) text boxes. The CfgFNCO box which will display an 8 digit HEX value that is to be written to the CfgFNCO register in the MAX5871. The CfgNCON and CfgNCOD boxes will update with a 4-digit HEX value representing the fractional portion of the frequency calculation. The CfgNCON and CfgNCOD are reduced to the lowest possible denominator value. The Apply Values button is clicked in order to transfer the calculated register values to the MAX5871.



VC707 TabThe VC707 tab (Figure 10) provides all the VC707 controls required to: a) load the FPGA firmware, b) configure the VC707 JESD204B serial interface, and c) load, start and stop test patterns. The user must initially point to the folder where the Impact tool resides, and then the location will be

stored on disk for future executions. Clicking the check-box the first time the application is executed causes a file browser to open. The user navigates to the folder containing the Impact tool, by default this is installed in \Xilinx\14.7\LabTools\LabTools\bin\nt64 (for 64-bit PCs) or \Xilinx\14.7\LabTools\LabTools\bin\nt (for 32-bit PCs).

Figure 10. VC707 Tab



Once the Impact path has been captured, the FPGA Configuration (.bit) file can be downloaded. Clicking the Load FPGA Configuration button causes a file browser window to appear with the current folder set to MAX5871\VC707Files. The user selects the MAX5871_DataSource.bit file and clicks open. The MAX5871 EV kit Software control generates and executes the command line call of the Impact tool to transfer the configuration to the FPGA. The GUI provides a Loading progress bar, which can take up to 60 seconds or more to complete. The fan on the VC707 will stop momentarily during the process. After the programming is completed, the fan will restart and the cycling LEDs on the VC707 will become static. If the progress completes within a few seconds, the fan never stops and the LEDs continue to cycle, then the firmware did not load properly. Ensure that the drive_install.exe file, located in the same folder as the Impact tool, has been executed and try loading the firmware again.The VC707 is ready to act as the data source for the MAX5871 once the firmware is load has completed. Additionally, the MicroBlaze Interface can be employed for direct communication with the FPGA. Clicking the Text Box allows the user type in a command that will either be a read or write command. Results of the command appear in the LOG window, and when successful the text box will update with ACK – Acknowledge. NAK is reported when the command fails, usually due to improper syntax. Writing a <PING> command to the MicroBlaze should at this point return and ACK, a useful step to verify configuration has completed.Next, the Lane Configuration must be selected. The 411 option is used for 4-lane configurations. Similarly, 221 is for two lane and 141 is for single-lane modes. The numbers in the lane configuration selection (411) represent the LMF of the interface where: L is the number of lanesM is the number of samples per frame,F is the number of frames per multiframe.Refer to the JESD204B standard for more details on the LMF settings of a JESD link.Next, the lane rate must be selected. This is determined by the register settings that were loaded into the MAX5871

when it was configured. Make sure the rate selected here matches the .cfg file that was loaded.The VC707 requires that the test pattern(s) be stored in the on-board memory, which occurs when the <Load Patterns> button is clicked. The GUI opens a file browser in the MAX5871\PatternFiles folder. The user then selects the desired list (patListFile.txt is included at installation for an example). The list of patterns is then read into the PC and transferred to the VC707 through the BULK USB connection. Multiple patterns can be loaded simultaneously with the total combined pattern size of up to 1GB.Now that the FPGA is configured and patterns have been loaded, the user selects the desired pattern in the drop-down box. Clicking <Start> causes the JESD204B link in the FPGA to reset and, after synchronization with the MAX5871, the selected pattern is output to the JESD204B interface.The <Stop> button must be clicked prior to selecting another pattern or changing the MAX5871 configuration. Only the NCO frequency can be altered on the fly allowing the user to dynamically move the center frequency of the output signal.

Status tabThe Status tab, Figure 11, provides the user interface to the MAX6654 Temperature Monitor IC and the ability to enable control of the MAX5871EVKIT Software Controller through a TCP/IP port.The Temperature section of this tab provides for controls for user access of the MAX6654 devices internal registers; Read Temperature, Read Sensor Register, Set Threshold and Clear Temperature Alert. Activating the <Read Temperature> button causes the MAX6654 to read the die temperature (TDA/TDC connections) and return the value. The GUI interprets the returned value, converting it to a Celsius value that is displayed in the adjacent text box.Reading the sensor registers requires the user to enter the desired register to access in the text box. Activating the <Read Sensor Register> button updates the value text box with the current contents of the address specified; the value is reported in HEX format.



Figure 11. Status Tab



The <Set Threshold> button is used to configure the high temperature ALERT threshold for the MAX6654. The ALERT signal will be asserted when the temperature of the MAX5871 exceeds this value. The Celsius value entered in the adjacent text box will be converted into the appropriate register write for this function. When ALERT is asserted, a red LED (D1) will illuminate on the MAX5871EVKIT PCB. Activating the <Clear Temperature Alert> button will clear the alert. However, if the MAX5871 die temperature is still above the programmed threshold, the LED will immediately re-illuminate. The Automation Options section provides the user the control needed to enable remote operation through a locally opened TCP/IP port. The user enters a desired port number and then clicks the <Enable TCP/IP Control> toggle button. NOTE, the application window will not respond to direct control and will not update until it receives an ‘RTL’ command from the TCP/IP port. Refer to the MAX5871EVKit Automation Support rev#.pdf document located in the c:\MaximIntegrated\MAX5871\EVKIT Info folder that was created during the software installation process.

Register Access TabThe <Register Access> tab, Figure 12, allows the user to explore and modify the register contents of the MAX5871. There are several hundred registers in the device, which are broken up into operational groups. The controls on this tab provide an intuitive, easily operated method for performing read and write operations as well as provide some detail on the specific functions of specific registers. The tab is broken up into 5 sections; 1) Register Block and Register selection, 2) Command Selection, 3) Selection Options, 4) Execute button and 5) Results returned from command execution. Valid options either populate or enable based on previously selections and entries.

Custom ConfigurationsCustom configurations of the MAX5871 can be readily generated using the PERL script included with the software installation. The PERL script MAX5871_gen_config.pl is located in the c:\MaximIntegrated\MAX5871\DeviceScripts\PERL_ScriptGen folder that was created during the software installation process. The user must have a PERL interpreter, such as the free application StrawberryPERL (http://strawberryperl.com/), installed on their system in order to execute the supplied script.

The PERL script reads a .setup file and creates the .cfg files containing the sequence of register writes required to configure the MAX5871 device for the intended operating mode. In order to create a new configuration file the user must identify the operating parameters for their application by completing the table below:

First, determine the required baseband input sample rate (fS_IN) based on the bandwidth of the signal to be generated: 737.28MHz, 614.4MHz, 491.52MHz, 368.64MHz, 307.2MHz, or 245.76MHz. The input sample rate determines the available options for the Link Rate and Lane Count, as illustrated in the LaneConfigOptions.pdf file located in the c:\MaximIntegrated\MAX5871\DeviceScripts folder. As an example, a fS_IN of 737.28Msps requires four lanes at 7.3728Gbps and the RCLK Divider set to 4, while a fS_IN of 245.76Msps has three possible lane count and rate conditions: four lanes at 2.4576Gbps, two lanes at 4.9152Gbps, or a single lane at 9.8304Gbps all with RCLK Divider setting of 1.Once fS_IN and the JESD204B configuration are determined, the DAC update rate, input clock frequency and interpolation rate can all be determined. Referring to the Valid_Configurations.pdf file, also located in the c:\MaximIntegrated\MAX5871\DeviceScripts folder, the user locates the desired combination of these parameters that match the selected fS_IN. The remaining parameters depend on the system needs of the user. SYSREF Mode can be set to use either a continuous (0), clock-like signal or a single pulse (1). The MAX5871 supports JESD204B Subclass-0 and Subclass-1 (required for deterministic latency). The Device Clock Source is a setting in the MAX5871 that determines if the DSP section of the device (interpolators, complex modulator and NCO) uses a clock derived from fDAC or recovered from the JESD204B Link.

fS_IN: ______________________

Link Rate: ______________________

Lane Count: ______________________

RCLK Divider: ______________________

PLL Mode: ______________________

fCLK: ______________________

Interpolation Rate: ______________________

SYSREF Mode: ______________________

JESD204B Subclass: ______________________

Device Clock source: ______________________

http://strawberryperl.com/



Figure 12. Register Access Tab



Now that all the required parameters are defined, they are entered into a .setup file. The user can open an existing .setup file in a text editor for modification. It is recommended that the file be saved with a new name that identifies the properties of the entered configuration, as the name of the setup file will determine the name of the .cfg file generated by executing the PERL script.

Test Pattern Lists and FilesPattern List FilesThe MAX5871 EV kit software controller utilizes list files for loading test patterns into the VC707 memory, such as the example patListFile.txt located in the MAX5871\PatternFiles folder. The list file simply contains the names, including extension, of the test pattern files. The format is simple text with one file name on each line. Any line within the list that contains a ‘#’ character will cause it to be skipped when the list is loaded by the GUI. The list can contain multiple patterns with up to 1GB in total pattern length, but only one pattern list can be loaded at a time; loading a new list will cause the previously loaded patterns to be overwritten. The total number of I/Q data points within a given pattern must be an integer multiple of 1024.

Pattern GenerationThe MAX5871 EV kit software controller is provided with a limited number of sample patterns, one for each of the supported input sample rates (fS_IN). The provided patterns allow the user to generate a two-tone, CW signal with a 1MHz spacing between the tones. Typically, the user will want to generate signals with other properties, including modulated signals. A Matlab folder is included in the MAX5871\PatternFiles folder, which contains sample Matlab routines (.m files) that allow a user with Matlab installed to create additional continuous wave, sinuous test patterns. The makesignal.m routine will performs the CW generation and outputs a complex vector with a range of ±1.0. The set_datascale_avg.m is used to convert the complex

vector into integer representations of the offset binary values for the I and Q data paths. Finally, the scaled pattern is stored to a pattern file using the MAX5871_PatFile.m routine which formats the pattern appropriately for use with the VC707. Please refer to the comments, lines that begin with % following the copyright statement at the top of the file, in these files for information about the input arguments used by these routines. The pattern file can use any extension (such as .csv or .txt), as long as the contents are simple text and conform to the format expected by the MAX5871 EV kit software controller. The specific format is as follows:The first line contains the total number of I/Q data points, N, in the pattern. The total number of lines in the pattern file will be N + 1.The second through N lines contain four, comma separated integer values. These values represent, in order, the I data Least Significant BYTE (LS BYTE), the I data Most Significant BYTE (MS BYTE), the Q data LS BYTE and the Q data MS BYTE. That is: I LS BYTE, I MS BYTE, Q LS BYTE, Q MS BYTEFor example, the first few lines of the file will look something like this:

*N is the total number of I/Q data points in the file.

LINE NUMBER CONTENTS1 65536

2 19, 242, 253, 127

3 19, 242, 250, 127

4 17, 242, 248, 127

5 15, 242, 245, 127

…

…

…

65534 13, 242, 242, 127

65535 10, 242, 239, 127

65536 7, 242, 236, 127

65537 (N+1)* 3, 242, 234, 127



MAX5871 Evaluation BoardThe MAX5871 EV kit board incorporates a USB interface, that provides a serial port interface (SPI) to control the MAX5871 RF DAC, and an SMBus interface to control the MAX6654 (Temperature Monitor). The FTDI4232 USB interface device provides the SPI and I2C interfaces, as well as GPIO controls for the hard-wired MUTE, INTB and RESETB signals on the MAX5871. The EV kit employs two on-board modules to allow easy interfacing to signal generators and spectrum analyzers.1) Clock Input Module (RFDAC_XFMR_CLK_MODULE):

converts a single-ended signal generator output to a differential signal that drives the CLKP/CLKN inputs of the MAX5871.

2) Output Module (RFDAC_XFMR_OUT_MODULE): converts the differential output of the MAX5871 DAC to a single ended 50Ω output suitable for driving the input of a 50Ω spectrum analyzer.

The EV kit board requires a single +3.3V, 3A power supply connected to the board through BANANA jacks. The +3.3V supply is used by the various support circuits, and is also used as the input source for the MAX8527 linear regulators (LDO) that provide the 1.8V and 1.0V supplies for the MAX5871. One LDO is used for each level, however the LDO outputs are isolated for analog and digital domains by on board filter networks. Additionally, the PLL supplies for the MAX5871 are also isolated from the analog domain through more filtering. The EV kit includes a MAX6161 precision reference for use as an external reference for the MAX5871. Power for the MAX6161 is supplied through jumper JU4, while JU5 connects the MAX6161 output to the MAX5871 VREF input.

The MAX5871 EV kit provides direct connection the HPC-1 FMC connector on the VC707, providing a high-quality interconnect that supports the maximum 9.8304Gbps lane rate of the JESD204B interface.Schematic and layout files for the MAX5871 EV Kit board are included with the software installation files and located in the MAX5871 EV kit info folder

Xilinx VC707 Evaluation BoardThe Xilinx VC707 board acts as the data source for the MAX5871, allowing for user defined signal generation. Test patterns, generated externally, are stored in the VC707’s on-board DDR memory and subsequently transmitted through the JESD204B to the MAX5871. A total of 1GB of pattern(s) can be stored allowing for the use of very long patterns, or multiple patterns consecutively. Multiple patterns allow the user to easily change patterns without repetitive download commands. The USB2.0 (BULK) interface minimizes the time requirement for downloading the test patterns. Integrated commands allow the VC707 to properly drive all lane rate and speed combinations supported by the MAX5871.The MAX5871 EV kit software controller also provides a simple interface for controlling the VC707 board. The user will utilize the VC707 tab in the GUI to download the firmware file that configures the on-board Virtex7 FPGA. The firmware design incorporates the MicroBlaze microcontroller function in the FPGA, which is used to manipulate the operation of the FPGA. The supported set of MicroBlaze commands are listed in Appendix 1 for reference. However, all required commands for normal operation are incorporated into specific controls in the application.



Appendix 1. MicroBlaze Command SetList of Commands

COMMAND DESCRIPTIONhelp Prints help. Use -a flag for all commands. Example: “help -a”

mem Read or write DDR memory

usb Read or write DDR memory with USB bulk transfer

Reg Read or write a register

capture Manage capture DMA channel

play Manage play DMA channel

checksum Checksum a region of DDR memory

fill Fill a region of DDR memory with a pattern

ping Does nothing but ack

memmap Print a memory map of the system

scramble Turn JESD204B scrambling on or off for RX or TX

loopback Turn the loop back on or off

resync Force the data source to resync

jesdreset Force a reset of the JESD subsystem

lanes Specify how many RX and TX lanes to use

configure Specify how many RX and TX lanes to use, and how to map data

baudrate Set the baud rate of the serial port

quit Quits this program

COMMAND: helpOnline help is provided for all commands. Short and long version are available.The help command with no options will print a list of top level commands.

Command:help <arg> ... <arg> <-flags>

Args: command, or command and subcommand to get help about.

Flags:--all or -a Print help for all the commands

Description/Syntax of VC707 Command Set



COMMAND: memThe mem commands are for reading and writing the DDR memory used for test data.

mem [read|write] [address] [number of bytes] [word] ... [word]

Available mem commands:read Read a range of memory write Write a range of memory

mem read:Read a specific number of 32 bit words from a given address of DDR memory.

Flags allow different output formats.Default mode is to send data in ASCII format. Use the -b flag to send in binary mode. When sending in binary mode, the proper number of bytes will be sent, followed by an ACK. There will not be a CR/LF between the data and the ACK.

Command:

mem read [address] [number of bytes] <-flags>

Arguments:address: address to read from in any format that strtoul will parse number of bytes: how many bytes to read in multiples of 4 flags: --binary -b send data in binary mode --chksum -c send 16 bit IPv4 checksum at the end of the data

Example:

ACK# mem read 0x80000000 8 -c 0x64636261 0x68676665 0x6A6EACK# ACK# mem read 0x80000000 8 -b -c abcdefghnjACK#

Description/Syntax of VC707 Command Set (continued)



mem write:

Write a specific number of bytes to a given address of DDR memory. Default mode is to send data in ASCII format. Use the -b flag to send in binary mode. When sending in binary mode, follow the -b flag with a CR and LF. There will not be an ACK at this point. Then send the proper amount of binary data. Do not follow the binary data with a CR/LF. After the proper number of bytes has been received, an ACK will be sent.

Command:mem write [address] [number of bytes] <-flags> [word] [word] ...

Arguments:address: address to write to in any format that strtoul will parse number of bytes: how many bytes to write in multiples of 4 word: 32 bit values in any format that strtoul will parse

flags:--binary -b send data in binary mode. --chksum -c check 16 bit IPv4 checksum at the end of the data

Example:

ACK# mem write 0x80000000 8 -c 0x64636261 0x68676665 0x6A6E ACK#

ACK# mem write 0x80000000 8 -b –c abcdefghnjACK#

COMMAND: usbThe usb commands are for reading and writing the DDR memory used for test data.

usb [read|write] [address] [number of bytes]

Available usb commands:read Read a range of memory over USB write Write a range of memory over USB




usb read:Read a specific number of bytes from a given address of DDR memory. The data is returned using a USB BULK IN transfer.

Command:

usb read [address] [number of bytes]

Arguments:address:address: to read from in any format that strtoul will parse number of bytes: how many bytes to read in multiples of 4

Example:

ACK# usb read 0x80000000 8ACK#

usb write:Write a specific number of bytes to a given address of DDR memory.The data is sent using a USB BULK OUT transfer

Command:

usb write [address] [number of bytes]

Arguments:address: address to write to in any format that strtoul will parse number of bytes: how many bytes to write in multiples of 4 word: 32 bit values in any format that strtoul will parse

Example:

ACK# usb write 0x80000000 8ACK#

COMMAND: regThe reg commands are for reading and writing registers.

reg [read|write] [address] <word>

Available reg commands:read: read a register write: write a register list: list registers or reg spaces set: set register fields by name




reg read:Read a specific 32-bit register at a given address.

Command:reg read [address]

Arguments:

Address: address to read from in any format that strtoul will parse

reg write:Write a specific 32-bit register at a given address of DDR memory.

Command:reg write [address] [word]

Arguments:Address: address to write to in any format that strtoul will parse Word: 32-bit values in any format that strtoul will parse

reg list:List the available register spaces, or the registers in a register space.

Command:reg list <register space>

Arguments:register space: optional space name to show the registers in that space

reg set:Write to control register fields by name. Only the bits of that field within the control register are modified.

Command:

reg set <register space > ... <register space> [register name] [value]

Arguments:register space zero or more hierarchical register space names register name name of the control register field to set value value to write to the control register field




COMMAND: capture

The capture commands are for configuring, starting, and stopping the capture DMA channel.

Available capture commands:buffer: Configure the base address and length of capture buffer dumpregs: Print the capture channel registers start: Start the capture channel stop: Stop the capture channel

capture buffer:

Configure the starting address and size of the capture buffer.Must start on an 64-byte alignment, and be a multiple of 512 bytes.The RX DMA engine must be stopped before using this command.

Command:capture buffer [address] [number of bytes]

Arguments:address address to read from in any format that strtoul will parse number of bytes how many bytes to read in multiples of 512

capture dumpregs:Print the contents of the RX DMA engine.Refer to Xilinx document PG021 for their meaning.

Command:capture dumpregs

capture start:Start the RX DMA engine.The capture buffer command must be used first to define the buffer.

Command:capture start

capture stop:Stop the RX DMA engine.

Command:capture stop




COMMAND: play

The play commands are for configuring, starting, and stopping the play/TX DMA channel.

Available play commands:buffer: Configure the base address and length of play buffer dumpregs: Print the play channel registers start: Start the play channel stop: Stop the play channel reset: Reset both channels of the DMA engine.

play buffer:

Configure the starting address and size of the play buffer.Must start on an 64 byte alignment, and be a multiple of 512 bytes.The TX DMA engine must be stopped before using this command.

Command:play buffer [address] [number of bytes]

Arguments:address address to read from in any format that strtoul will parse number of bytes how many bytes to read in multiples of 512

play dumpregs:Print the contents of the TX DMA engine.Refer to Xilinx document PG021 for their meaning.

Command:play dumpregs

play start:Start the TX DMA engine.The play buffer command must be used first to define the buffer.

Command:play start

play stop:Stop the TX DMA engine.

Command:play stop




COMMAND: checksumCaclulate a 16 bit IPv4/TCP/IP checksum on a range of memory.

Command:checksum [address] [number of bytes]

Arguments:address starting address in any format that strtoul will parse number of bytes how many bytes to checksum

COMMAND: fillFill a range of memory with a pattern.

Command:fill [address] [number of bytes] <word> <-flags>

Arguments:address starting address in any format that strtoul will parse number of bytes how many bytes to fill. Must be a multiple of 4 word 32 bit word to fill memory with

flags:--ramp -r Fill with a 32 bit ramp between start and stop values. --start -s [arg] Starting value for fill pattern. Defaults to 0. --stop -p [arg] Terminal value for fill pattern. Defaults to 0xFFFFFFFF

Example:fill 0x80000000 0x20000 0xA5A55A5Afill 0x80000000 0x20000 --ramp -s 0x1234 --stop 0x5678

COMMAND: scramble

The scramble command is for turning the JESD204B scrambling on/off in the RX and TX paths.

Command:scramble <-flags>

Flags:--yes or -y enable scrambling--no or -n disable scrambling--tx or -t apply to TX--rx or -r apply to RX




COMMAND: loopback

The loopback command is for turning the loopback on/off in the GTX transceivers for the TX to RX paths.

Command:loopback <-flags>

Flags:--yes or -y enable loopback--no or -n disable loopback

COMMAND: resyncThe resync command is for forceing the data sourcetransmitter to go through the resync process.

Command:resync <-flags>

Flags:--yes or -y force sending the sync characters until turned off --no or -n normal operation no flag means pulse the sync characters on, then back off

Example:resync This will force the transmitter to send a pulse of sync characters

COMMAND: jesdresetThe jesdreset command is for forcing the data source JESD subsystem to go through a reset cycle. This will reset the JESD core and the DMA engines. It does not reset the processor, or the DDR memory.

Command:jesdreset

Example:jesdreset




COMMAND: lanes

The lanes command is used to specify how many RX and TX lanes should be used.

Command:lanes <number> <-flags>number 1, 2, or 4

Flags:--tx or -t set number of TX lanes--rx or -r set number of RX lanes

COMMAND: configureThe configure command is used to specify how many RX and TX lanes should be used, and how the data should be mapped.Currently, there is only a TX mapper, and not an RX demapper.

Command:configure <number> <-flags>

number 411,422,221,141,400 411 4 lanes, 1 octet per frame, 1 sample per frame 422 4 lanes, 2 octets per frame, 2 samples per frame 221 2 lanes, 2 octets per frame, 1 sample per frame 141 1 lane, 4 octets per frame, 1 sample per frame 400 legacy mode. 4 lanes, straight through mapping

Flags:--tx or -t configure TX --rx or -r configure RX

Example:

configure 411 -t -r

COMMAND: baudrateSet the baud rate of the serial port.

Command:baudrate [rate]

valid rates: 9600 14400 19200 38400 57600 115200 230400 460800




#Denotes RoHS compliant. *Order from Xilinx or authorized distributor.

Note: Indicate that you are using the MAX5871 when contacting these component suppliers.

Ordering InformationPART TYPE

MAX5871EVKIT# EV Kit

EK-V7-V707-G Xilinx Virtex 7 FPGA Board*

Component Suppliers

PCB Layout and SchematicsSee the links below for PCB layout diagrams and schematics.

● MAX5871 EV PCB Layout

● MAX5871 EV Schematic

SUPPLIER WEBSITEFairchild Semiconductor www.fairchildsemi.com

Hong Kong X’tals Ltd. www.hongkongcrystal.com

Murata Electronics www.murata.com

Panasonic Corp. www.panasonic.com

Taiyo Yuden www.t-yuden.com

TDK Corp. www.component.tdk.com

http://www.fairchildsemi.com/

http://www.hongkongcrystal.com/

http://www.panasonic.com/

http://www.t-yuden.com/

http://www.component.tdk.com/

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2016 Maxim Integrated Products, Inc. │ 35


Revision HistoryREVISIONNUMBER

REVISIONDATE DESCRIPTION PAGES

CHANGED

0 5/16 Initial release —

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Silkscreen Top

Top

Level 2 GND

Level 3 Signal 1

Level 4 GND

Level 5 Power

Level 6 GND

Level 7 Power

Level 8 Signal 2

Level 9 GND

Bottom

Silkscreen Bottom

R42-C8

4. FLOOD TOP LAYER WITH GND, INCLUDING AROUND U1, TO MAXIMIZE THERMAL CONDUCTIVITY FOR U1.

3. R20 SHOULD BE PLACED NEAR U1.

HOWEVER, ALL VIAS MUST HAVE THERMAL RELIEF FOR EASE OF ASSEMBLY.

U1.A12-C12-R11-U1.B11

U1.M7-C8-U1.M8

5. MINIMIZE LENGTHS OF THE FOLLOWING NETWORKS/TRACES/CONNECTIONS:

LAYOUT NOTES:

1. M7 CONNECTS TO GND THROUGH VIA AS CLOSE TO BALL AS POSSIBLE.

C8 IS PLACED IMMEDIATELY BELOW AND BETWEEN M7 & M8.

R42 SHOULD BE AS CLOSE TO M8 AS POSSIBLE.

U1.B11-C66-U1.A11(GND)

2. MINIMIZE TRACE LENGTHS FOR PLL_COMP_U1 AND VCOBYP_U1.

U1.B1-R20-U1.B2

(UNDER CAPT BALL)

V2D

10UF

PLL_COMP_U1

C8C7

C9C10

4700PF

OPEN

C82

C83

C69

C68

C55

C54

C45

C36

C28

C35

C27

C26

TP3

C180 C181 C179

21

L13

C172 C173 C174

R38

21

L2

21

L3

21

L4

R42

C81

C74

C71

C8

R20

G1

F1

E1

F2

G3G2

E2

U1

K2M2

M11K11

D1D2

G11G10

D3

U1

A1A6

A7

B2B1A2

D12

U1

J11

J2H11

H2

H12J12H3J3H1J1

M5

L12

L10

L3

L1

M12

M10

M3

M1

L6L7

L5

M8

U1

M7

G5F8F7F6F5

L8

J9J4H9H4G9

B11

B8B7B6B5A8A5

M9M6M4L11L9L4L2K12K10K9K8K5K4K3K1J10J8

J6J5H10H8H7H6H5G12G7G6F12F11F10F9F4F3E10E8

E7E6

E5E3D10D9D8D7D6D5D4C12

C6C5C4

E9E4

D11

C3C2B9B4A9A4

E11

A10A3

B12

U1

21

JU1

C3C4

REF-GND

C33C32C7C2C34

C79 C80

C73C72

R13

R44

216

831

2

4

2

1

0.01UF

SYNCOP

SYNCNN

TXP3

TXN3

0.01UF

0.01UF

DN1DP0

DP1

CMU_TEST0/SYSREFEN0.01UF

DN0

DP3 PLL_COMP_U10.01UF

CMUOUTP/NCCMUOUTN/NC

PEC02SAAN

25.5K

OPEN

0.01UFDN3

0.01UF

0.01UF

0.01UF

DN2DP2

1.27K

V2A

120

1UF 0.01UF

INTB

GND

SCLK

RESETB

MUTE

10K

1UF

OUTN

OUTP

CSBP

OPEN

MAX5871

1UFOPENDACREF

REFIOCSBP

RCLKP

FSADJDACREF

CLKN

SDO

HRN

MAX5871

CSBSDI

10K

V2A

MAX5871

GND

CLKP

RCLKN

0.01UF

100PF

V2A

10UF

1UF10UF

120

1UF 0.01UF

V1A

V1A

10UF

1UF

VCOBYP_U1

GND

V2V_P

HRP

FSADJ

REFIO

GND

120

0.01UF

120

0.01UF

0.01UF

0.1UF

1UF

MAX5871

OPEN

V1D

V1D

0.01UF

TXN0

V1V_P

OPEN

VIN

REFIOJU5

PEC02SAAN

75

MAX6161AESA

U4

V2DV2D

JU4

E12

PEC02SAAN

K7K6

0.01UF

0.01UF

TXP0

SYSREFP/SYNCIPSYSREFN/SYNCIN

SYNCONSYNCNP

A12

C11

J7

C67 C70V2D G4

MAX5871

C1

TDATDC

G8

B10B3A11

R2

GND

OPENR10

C12

OPENR4

VCOBYP_U1

649R11

R12OPEN

0.22UF

C66

C25OPEN

GND_M9GND_M6

GND_K12GND_K10GND_K9

GND_K4GND_K3GND_K1

GND_J10GND_J8GND_J7GND_J6GND_J5

VDD2_H9

GND_H8GND_H7GND_H6GND_H5

VDD2_H4VDD2_G9

VDD_G8VDD_G5

VDD2_G4 GND_F9

VDD_F8VDD_F7VDD_F6VDD_F5

GND_F4

AVDD_E9

GND_E7GND_E6

AVDD_E4

VCOBYP_B11

RVDD2_B7RVDD2_B6

GND_E10GND_E8GND_E5GND_E3

GND_L11

GND_L2

VSSPLL

GND_L9

VDD2PLL

GND_K8

GND_M4

GND_L4

GND_K5

VDD2_J9VDD2_J4

GND_H10

GND_G12GND_G7GND_G6

GND_F12GND_F11GND_F10

GND_F3

AVDD1_PLL

AVDD2_PLL

GND_D10GND_D9GND_D8GND_D7GND_D6GND_D5GND_D4

GND_C12GND_C11GND_C10GND_C9GND_C8GND_C7GND_C6GND_C5GND_C4

AVDD2_C3AVDD2_C2

AVCLK2_B12

GND_B10

AVDD2_B9

RVDD2_B8

RVDD2_B5

AVDD2_B4

GND_B3GND_A11

AVCLK_A10

AVDD2_A9

RVDD2_A8RVDD2_A5

AVDD2_A4

AVCLK_A3

IN

IN

IN

IN

IN

IO

IN

IN

INNC3

GND

NC2

NC1

IN OUT

NC4

NC5

IN

OUTOUTIN

IN

OUTOUT

ININ

OUT

INIO

OUT

IN

ININ

IN

ININ

ININ

IN

OUTOUT

IN

OUT

OUT

OUT

OUT

OUTOUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

MUTEINTBSDORESETBSDICSBSCLK

TDCTDA

HRNHRPTEST2TEST1ATESTPGBSISTRSOOTP

RCLKNRCLKP

CLKNCLKP

FSADJDACREF

OUTN_A7

OUTP_A6CSBPREFIO

SYNCNNSYNCNPSYNCONSYNCOP

TXN3/NCTXP3/NC

JRES

CAPT

DN3DP3

DN2DP2

DN1DP1

DN0DP0

CMUOUTN/NCCMUOUTP/NCCMU_TESTO/SYSREFEN

SYSREFN/SYNCINSYSREFP/SYNCIP

TXN0/NCTXP0/NC

PLL_COMP

IN

A8-9/B7-9

J4/H4

(U1_H9)

(U1_F7)

C2/C3

J9/H9

DUT1V

DUT1.8V

E9F7-8/G8

G4/G9

A4-5/B4-6

F5-6/G5 E4

DEVICE POWER

DEVICE POWER FILTERING

(+3.3V)

MAIN BOARD POWER

V2V_DUT

V2V_DUT

100PF

V2V_DUT

0.01UF

+3.3V

108-0740-001

+3.3V

+3.3V

C95 C96 C97C94

C16 C22

C13 C21

V2D

V1D

21

L12

21

L11

21

L10

21

L1

2

1

C31

2

1

C47

2

1

C10

2

1

C48

R14

C46 C60

C56 C57

C37 C38

C39

C65 C61 C63

C42C50 C53 C58 C59

V2A

C64

C14 C15 C17 C18 C19 C20

C62C49

V1A

K

A

D3

R28 R29C9

14

7

6

13

12

11

10

5

4

3

2

8

9

15

1

U2

R15

C11

R17

R16

21

JU3

2

1

3N4

21

JU2

R6

R46

R45

R7

C117

2

1

3N3

C116

14

7

6

13

12

11

10

5

4

3

2

8

9

15

1

U12

2

1

C1

GND

K

A

D2

R25 R27

GND

150UF

108-0740-001

GND

LTST-C190GKT

499

VIN

VINMAX8527EUD+

2N7002

V1D

100PF 0.01UF0.01UF

47UF

0.01UF

100PF

100PF

GND

GND0.01UF 100PF

1UF

PEC02SAAN

10UF

GPIO_0_1

10K

VIN

49910UF

GPIO_0_0

2N7002

LTST-C190GKT

0.01UF

0.01UF

100PF

0.01UF

100PF

V2V_P

0

4.02K

OPEN

0.01UF

OPEN

100PF

4.02K

10UF

120

10UF

V1V_P

PEC02SAANV1V_DUT

0

4.02K

10.5K

MAX8527EUD+

0.01UF

100PF

1UF

120

V2A

47UF

100PF

GND

0.01UF 100PFGND

100PF0.01UF1UF

120

V1V_DUT

47UF

47UF

V2D

10UF 1UF

V1V_DUT

120

V1A

10UF

10UF

10UF

10K

+EP

T.P.

OUT

OUT

OUT

OUT

FB

GND

T.P.

POK

IN

IN

IN

IN

EN

IN

G

S

D

IN

G

S

D EP

T.P.

OUT

OUT

OUT

OUT

FB

GND

T.P.

POK

IN

IN

IN

IN

EN

+

OUT

OUT

++

+

1. PLACE U5 CLOSE TO U1 TO MINIMIZE TRACES FOR TDC AND TDA.

TEMPERATURE MONITORAUX3.3V

AUX1.8V

LAYOUT NOTES:

POWER ON RESET CIRCUIT

AUXILIARY POWER

K A

D1

R22TP1

C52

TP2R33

R26

2

15 12

14

16

1395187

3

4

11

6

10

U5

4

5

3

2

1

U7

R8

C51

R24

R23

4

3

2

1

SW1

R1

R41

TP_1V8AUX

C78

R9

14

7

6

13

12

11

10

5

4

3

2

8

9

15

1

U9

C75R18R19

K

AD4

2

1

3N1

C77R21R43

K

AD5

2

1

3N2

MAX6654MEE+

0.01UF

VIN

2200PF

10K

VIN

LTST-C190GKT

10K

GPIO_1_6

V2V_DUT

10K

V1V_DUT

VIN

TDA

LTST-C190EKT

VIN

V2V_AUX

TEMP_SDA

10K

V2V_DUTRESETB

GPIO_1_7

MAX8527EUD+

2N7002

LTST-C190GKT

49910UF

2N7002

499

VIN

TEMP_SCLK

B3S-1000P

RESET_IN

10K

499

10UF

10UF

VIN

MAX6740XKWED3+

47

499

TDC

ALERTB

0

4.02K

10.5K

OUT

OUT

IO

OUT

IN

IN

NC

STBY

SMBCLK

NC

SMBDATA

ALERTADD0

NC

GND

GND

ADD1

NC

DXN

DXP

VCC

NC

RSTIN

RST

GND

VCC1

VCC2

G

S

D

IN

IN

IN

NOCOM

OUT

IN

EPT.P.

OUT

OUT

OUT

OUT

FBGND

T.P.

POK

IN

IN

IN

IN

EN

G

S

D

INSTALL 0 OHM RESISTORS TO CONNECT ONE OF THE FOLLOWING OPTIONS:

2) CONNECT SYSREF_/SYNCI_ TO FPGA_SYSREF, SYSREF__A AND B ARE LEFT FLOATING (DEFAULT)

DATA INTERFACE

1) SYSREF__B CONNECTED TO FPGA_SYSREF AND SYSREF__A TO SYSREF_/SYNCI_

TXP0

R32

R37

R40

R39

R31

R30

J40

J39

J38

J37

J36

J35

J34

J33

J32

J31

J30

J29

J28

J27

J26

J25

J24

J23

J22

J21

J20

J19

J18

J17

J16

J15

J14

J13

J12

J11

J10

J9

J8

J7

J6

J5

J4

J3

J2

J1

J5

H40

H39

H38

H37

H36

H35

H34

H33

H32

H31

H30

H29

H28

H27

H26

H25

H24

H23

H22

H21

H20

H19

H18

H17

H16

H15

H14

H13

H12

H11

H10

H9

H8

H7

H6

H5

H4

H3

H2

H1

J5

G40

G39

G38

G37

G36

G35

G34

G33

G32

G31

G30

G29

G28

G27

G26

G25

G24

G23

G22

G21

G20

G19

G18

G17

G16

G15

G14

G13

G12

G11

G10

G9

G8

G7

G6

G5

G4

G3

G2

G1

J5

F40

F39

F38

F37

F36

F35

F34

F33

F32

F31

F30

F29

F28

F27

F26

F25

F24

F23

F22

F21

F20

F19

F18

F17

F16

F15

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

J5

E40

E39

E38

E37

E36

E35

E34

E33

E32

E31

E30

E29

E28

E27

E26

E25

E24

E23

E22

E21

E20

E19

E18

E17

E16

E15

E14

E13

E12

E11

E10

E9

E8

E7

E6

E5

E4

E3

E2

E1

J5

D40

D39

D38

D37

D36

D35

D34

D33

D32

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

J5

C40

C39

C38

C37

C36

C35

C34

C33

C32

C31

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

J5

B40

B39

B38

B37

B36

B35

B34

B33

B32

B31

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

J5

A40

A39

A38

A37

A36

A35

A34

A33

A32

A31

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

J5

K40

K39

K38

K37

K36

K35

K34

K33

K32

K31

K30

K29

K28

K27

K26

K25

K24

K23

K22

K21

K20

K19

K18

K17

K16

K15

K14

K13

K12

K11

K10

K9

K8

K7

K6

K5

K4

K3

K2

K1

J5

DN0

DP2

DN2

DN1

DP1

DP0

TXN0

TXN3

DP3

DN3

TXP3

SDA_FPGA

INTB_FPGA

OPEN

SYSREFP/SYNCIP

ASP-134488-01

FPGA_SYSREFN

TXN2

ASP-134488-01ASP-134488-01

TXP2

TXP1

TXN1

DEVCLKP

LA6N

DEVCLKN

SCL_FPGA

SYSREFN/SYNCIN

ALERT_FPGA

SDO_FPGA

LA4P

LA2N

ASP-134488-01

SDI_FPGA

RESETB_FPGA

MUTE_FPGA

SCLK_FPGA

SYSREFN_A

SYSREFP_A

OPEN

ASP-134488-01ASP-134488-01

LA2P

SYNCOP

SYNCON

LA7N

LA7P

LA4N

LA3P

LA3N

ASP-134488-01

SYSREFP_B

SYSREFN/SYNCIN

OPEN

0

SYSREFN_B

0

SYSREFP/SYNCIP

OPEN

FPGA_SYSREFP

CSB_FPGA

ASP-134488-01

FPGA_SYSREFN

SYNCNP

ASP-134488-01ASP-134488-01

RCLKP

RCLKN

FPGA_SYSREFP

SYNCNN

LA6PIN

IN

ININ

IN

IN

IN

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

IN

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

IN

IN

IN

IN

IN

IN

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

IN

IN

IN

IN

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

IN

IN

IN

IN

IN

IN

IN

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

IN

IN

IN

IN

IN

IN

IN

IN

IN

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

IN

IN

IN IN

IN

IN

IN

IN

IN

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

IN

IN

IN

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

FTDI USB INTERFACE

USB POWER

SW2

B3S-1000P

4

3

2

1

C1013

49

50

94 56

42

3120

64

3712

13 36

14

6

60

3

2

5147

35

2515

1151

61

63

62

8

7

5958

57

55

5453

52

48

46

45

44

4341

40

39

38

34

33

32

3029

28

27

26

10

24

23

2221

19

18

1716

U1000

21

L1001

21

L1000

41

32

Y1000

2

1

C1001

2

1

C1000

R1006

5

8

76

4

3

1

2

U1001

R1005

R1004

R1003

R1002

R1001

C1012C1011

C1010C1008 C1009C1007C1006C1005C1004

C1003C1002

R1000

C23

USB3V3

C24

3

5

4

1

2

U10

9 8 7 6

54

3

2

1

USB

USB_3V3

1K

3.3UF

12K

CSBD_USBCSBC_USBCSBB_USBCSBA_USB

MOSI_USB

+1.8V USB_3V3

0.1UF

USB_3V3

SCLK_USB

+1.8V

10UF

28

USB_3V3

0.1UF

FT4232HL

SCL_USBMAX8511EXK33

USB_3V3

GPIO_0_0

GPIO_1_1

93LC56BT-I/SN

10K

10K

GPIO_0_6

0.1UF

GPIO_0_1GPIO_0_2GPIO_0_3GPIO_0_4GPIO_0_5

SDA_USB

MISO_USB

GPIO_0_7

GPIO_1_3GPIO_1_2

GPIO_1_4

GPIO_1_6GPIO_1_5

GPIO_1_7

GPIO_1_0

0.1UF0.1UF0.1UF0.1UF

+1.8V0.1UF0.1UF4.7UF

8PF

12MHZ

28

4.7UF

GND1UF

8PF

2.2K

USB_3V3

10K

USB_3V3

897-43-005-00-100001

0

N.C.

OUT

SHDN GND

IN

9 8

54321

7 6

NOCOM

DDBUS7DDBUS6DDBUS5DDBUS4DDBUS3DDBUS2DDBUS1DDBUS0

CDBUS7CDBUS6CDBUS5CDBUS4CDBUS3CDBUS2CDBUS1CDBUS0

BDBUS7BDBUS6BDBUS5BDBUS4BDBUS3BDBUS2BDBUS1BDBUS0

ADBUS7ADBUS6ADBUS5ADBUS4ADBUS3ADBUS2ADBUS1ADBUS0

OSCO

OSCI

VCCCORE

GND

GND

VCCIO

EECSEECLKEEDATA

TEST

VREGOUT

VREGIN

VCCCORE

VCCCORE

GND

GND

RESET#

SUSPEND#PWREN#

VCCIO

GND

GND

VCCIO

GND

GND

VCCIO

VPLL

DPDM

REF

AGND

VPHY

IN

ININ

ININ

IN

ININ

ININININININININ

ININ

INININ

OUTIN

ININ

++

NCNC

VCC

VSS

DO

DI

CLK

CS

LEVEL TRANSLATORS

VIN

10K

9

8

7

6

5

4

3

2

1

H7

9

8

7

6

5

4

3

2

1

H6

12

11

10

9

8

7

6

5

4

3

2

1

H3

R35

R34

R36

C44 C43

15

16

10

8

7

2

1

11

12

13

14

6

5

4

3

9

U3

15

16

10

8

7

2

1

11

12

13

14

6

5

4

3

9

U6

C41C40

VIN

10K

VIN

0.1UF

RESETB_USB

INTB_USB

ALERT_FPGA

TEMP_SCLK

SCL_FPGA

ALERTB

SDA_FPGA

TEMP_SDA

INTB

RESETB_FPGA

INTB_FPGA

PEC09SAAN PEC09SAAN

RESET_IN

MUTE

SDO_FPGA

CSB_FPGA

SCLK_FPGA

SDI_FPGA

SDO

SCL_USB

SDA_USB

SDI

CSB

SCLK

MISO_USB

MOSI_USB

CSBA_USB

SCLK_USB

PEC12SAAN

SN74AVC4T774PW

V2V_AUX

0.1UF 0.1UF

10K

V2V_AUX

INTB_USB

CMU_TEST0/SYSREFEN

MUTE_USB

RESETB_USB

GPIO_0_2

GPIO_0_3

GPIO_0_6

GPIO_0_7

GPIO_0_4

V2V_AUX

SN74AVC4T774PW

0.1UF

V2V_AUX

GPIO_0_5

MUTE_USBMUTE_FPGA

IN

IN

OUT

OUT

OUT

IN

IN

IN

OUT

IO

OUT

OUT

IN

IN

IN

IO IO

IN

IN

OUT

IN

IO

IO

OUT

IN

9

8

7

6

5

1 3

4

2

IN

IN

OUT

OUT

IN

OUT9

8

7

6

5

1 3

4

2

DIR4

OE

DIR2

DIR1

B4

B3

B2

B1

A4

A3

A2

A1

GND

DIR3

VCCBVCCA

OUT

OUT

12

11

10

9

8

7

6

5

13

4

2

IN

IN

IN

OUT

IN

OUTDIR4

OE

DIR2

DIR1

B4

B3

B2

B1

A4

A3

A2

A1

GND

DIR3

VCCBVCCA

CLK MODULE INTERCONNECT

VIN

+3.3V

+3.3V

+3.3V

SCLK_USB

1

1

1

11SCL_USB

1SDA_USB

1MISO_USB

1

MOSI_USB

1CSBD_USB

1

1CSBC_USB

1

1GPIO_1_7

1GPIO_1_6

1GPIO_1_5

1GPIO_1_3

1GPIO_1_4

1GPIO_1_2

1GPIO_1_1

1GPIO_1_0

1

1

1

1X68

1X67

1

1

1

1

1

1

1

1

1

1

1DEVCLKP

1DEVCLKN

1SYSREFP_B

1SYSREFN_B

1SYSREFP_A

1SYSREFN_A

1CLKP

1CLKN

C6

C5

MTHOLE_JACK-RO4003

MTHOLE_JACK-RO4003

GND

SCLK_USB

SCL_USB

CSBD_USB

GPIO_1_7

GPIO_1_4

GPIO_1_5

GPIO_1_2

GPIO_1_1

GPIO_1_0

GPIO_1_3

GND

MISO_USB

CSBC_USB

GPIO_1_6

MOSI_USB

SDA_USB

GND

GND

SYSREFP_A

DEVCLKN

DEVCLKP

SYSREFN_B

SYSREFP_B

SYSREFN_A

GND

GND

100PF

CLKN

100PF

CLKP

GND

GND

GND

GND

GND

GND

GND

GND

GND

IO

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

DAC OUT MODULE INTERCONNECT

FOR EXPANSION PURPOSES

21

21

GPIO_1_0

GPIO_1_1

CSBB_USB2

MOSI_USB

SCLK_USB3

CSBB_USB

GPIO_1_5

GPIO_1_6

GPIO_1_7

MTHOLE_JACK-RO4003

MTHOLE_JACK-RO4003

1 1

+3.3V

+3.3V

+3.3V

+3.3V

VIN

MOSI_USB2

SCLK_USB

MISO_USBOUTP OUTP

L9

2.2UH

L8

2.2UH

C30

1UF

V2A

1

V2A GPIO_1_7

GPIO_1_6

C29

1UF

V2A

11NC

1

1SCLK_USB2

1MISO_USB2

1SDA_USB2

1SCL_USB2

1

1SDA_USB3

1MISO_USB3

1

1MOSI_USB3

1CSBB_USB3

1SCL_USB3

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1OUTN

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1 X138

1 X137

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

CSBB_USB

GND

GND

GND

GPIO_1_5

GND

GND

GND

GND

GND

GND

GND

OUTN

SCL_USB

SDA_USB

GND

GND

GPIO_1_1

GPIO_1_2

MOSI_USB

V2A

GPIO_1_0

GPIO_1_1

GPIO_1_4

GPIO_1_3

GPIO_1_2

GPIO_1_1

GPIO_1_0

GPIO_1_2

GPIO_1_3

GPIO_1_4

GPIO_1_0

GPIO_1_3

GPIO_1_6

GPIO_1_2

GPIO_1_5

GPIO_1_4

GPIO_1_5

GPIO_1_3

GPIO_1_6

GPIO_1_4

GPIO_1_7GPIO_1_7

V2A

VIN

GND

GND SCL_USB

SDA_USB

SCLK_USB

MISO_USB

NC

GND

GND

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IO IO

IN

IN

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

max5871 evaluation kit - evaluates: max5871 · labtools\labtools\bin\nt. double-click on the file...

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