max34417 smbs or-channel hih dnaic rane poer acclatormonitored with a standard i2c/smbus serial...

General DescriptionThe MAX34417 is a specialized current and voltage monitor used to determine power consumption of portable systems. The device has a very wide dynamic range (20,000:1) that allows for the accurate measurement of power in such systems. The device is configured and monitored with a standard I2C/SMBus serial interface. The unidirectional current sensor offers precision high-side operation with a low full-scale sense voltage. The device automatically collects the current-sense and voltage samples and then multiplies those values to obtain a power value it then accumulates. Upon a command from the host, the device transfers the accumulated power samples, as well as the accumulation count, to a set of registers accessible by the host. This transfer occurs without missing a sample and allows the host to retrieve the data not in real-time, but at any time interval.

Applications ● Tablets ● Ultra Notebooks ● Smartphones ● Servers

Ordering Information appears at end of data sheet.

19-100222; Rev 0; 12/17

Benefits and Features ● Enables Code Optimization to Minimize Power

Consumption in Portable Platforms• Four Power Monitors with Wide 86dB Dynamic

Range• Measures Both Current and Voltage• Low Power Consumption• Reduced Power Consumption in Slow Accumulation

Mode• Power-Down Mode

● Minimizes Processor Overhead with Autonomous Operation• Per Channel 56-Bit Power Accumulators Capture

4.55 Hours of Data at 1024 Samples per Second• Per Channel 14-Bit Voltage Registers

● High-Integration Solution Minimizes Parts Count, PCB Space, and BOM Cost• Wide Current Common-Mode Range of 0.5V to

20V• Low Full-Scale, Current-Sense Voltage of 100mV• As low as 5μV Current-Sense Voltage• I2C/SMBus Interface with Bus Timeout• Temperature Range: -40°C to +85°C• Small, 2mm x 2mm Footprint Wafer-Level Package

(WLP) with 16 Bumps at 0.4mm Pitch ● Ease of Development

• Evaluation Kit with Advanced GUI Available

MAX34417 SMBus Four-Channel High Dynamic Range Power Accumulator

EVALUATION KIT AVAILABLE

Simplified Block Diagram

CHANNEL-4CHANNEL-3

CHANNEL-2

CHANNEL-1

MUX

X1/X8

ADC

AUTOMATIC SEQUENCING

OSCILL-ATOR

CURRENT(13/16-BIT)

VOLTAGE(14 BIT)

REGISTERS

POWERACCUMULATOR

(56-BIT)

POWER RESULT(30-BIT)

POWER CONTROL

SMBUS INTERFACE

DIGITAL CONTROL

INTERFACE

SCLSDAPDNBSLOW

ADDR

VCCGND

INxP

INxN

VREF

VIO

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IN+ and IN- to GND ...............................................-0.3V to +24VDifferential Input Voltage, IN+ to IN- ..................................±0.5VVDD or VIO to GND .................................................-0.3V to +4VSDA or SCL to GND ................................................-0.3V to +4VAll Other Pins ................ -0.3V to VIO + 0.3 (not to exceed +4)V

Operating Temperature Range ........................... -40°C to +85°CStorage Temperature Range ............................ -55°C to +125°CSoldering Temperature ............See the IPC/JEDEC J-STD-020A

Specification°C

(VDD = 2.7V to 3.6V, VIO = 1.6V to 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are TA = +25°C. Limits are 100% tested at TA = 25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSPOWER SUPPLIESVDD Operating Range 2.7 3.6 V

VDD Average Supply Current (Note 1) IDD

PDNB = VIO and SLOW = GND 774µAPDNB = VIO and SLOW = VIO 10

PDNB = GND 2VIO Operating Range 1.6 3.6 V

VIO Average Supply Current (Note 1) IIO

PDNB = VIO 10µA

PDNB = GND 1SENSE INPUT/OUTPUTMinimum Input Common-Mode Voltage 0.5 V

Maximum Input Common-Mode Voltage 20 V

IN+ Input Bias Current 1 µA

IN- Average Input Bias Current (Note 2)

SLOW = VIO or PDNB = GND 1µASLOW = GND (VSENSE = 0mV) 5

SLOW = GND (VSENSE = 100mV) 5

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

16 WLPPACKAGE CODE N162A2+1

Outline Number 21-100184Land Pattern Number Refer to Application Note 1891Thermal Resistance, Four-Layer Board:Junction to Ambient (θJA) 49°C/WJunction to Case (θJC) N/A

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package Information

Electrical Characteristics



http://pdfserv.maximintegrated.com/package_dwgs/21-100184.PDF

https://www.maximintegrated.com/en/app-notes/index.mvp/id/1891

http://www.maximintegrated.com/thermal-tutorial

http://www.maximintegrated.com/packages


PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSDYNAMIC CHARACTERISTICSPer Channel Current and Voltage Sample Rate (Note 5) SLOW = GND 1024 sps

Per Channel Current and Voltage Sample Rate SLOW = VIO 8 sps

Per Channel Power Calculation Rate (Note 5) SLOW = GND 1024 sps

Per Channel Power Calculation Rate SLOW = VIO 8 sps

Power Measurement Accumulation Accuracy (1 Sigma Error Range with > 2500 Accumulations) (Note 3, Note 4)

VSENSE = 5µV ±25 %

Input Bandwidth (Note 3) 400 kHz

Power-Up TimeMeasured from VDD > 2.6V and VIO > 1.5V and PDNB deasserted to SMBus port active

4 ms

ACCURACYCurrent Sample Resolution VSENSE < 10mV 16 BitsVoltage Sample Resolution 14 BitsCurrent-Sense Full Scale Voltage 100 mVVoltage-Sense Full Scale 24 V

Power Measurement Accumulation Accuracy (1 Sigma Error Range with > 1000 Accumulations) (Note 3, Note 4)

VSENSE = 97mV ±0.8

%VSENSE = 10mV ±1VSENSE = 1mV ±1.5VSENSE = 100µV ±2.2VSENSE = 50µV ±3.5

LOGIC INPUT/OUTPUTInput Logic-High (SCL/SDA/PDNB/SLOW) VIH 0.7 x VIO V

Input Logic-Low (SCL/SDA/PDNB/SLOW) VIL 0.3 x VIO V

SDA Output Logic-Low VOL IOL = 4mA 0.4 VSDA Output Leakage ±1 µASCL, SDA Leakage ±5 µASLOW, PDNB Leakage ±1 µAI2C/SMBUS INTERFACE (VIO = 3.3V)SCL Clock Frequency fSCL 1000 kHzBus Free Time Between STOP and START Conditions tBUF 500 ns

Electrical Characteristics (continued)




Note 1: SMBus not active.Note 2: Input bias current varies with VSENSE (IN+ - IN-) voltage. See the Typical Operating Characteristics section for details.Note 3: Estimated from simulation, not production tested.Note 4: Includes gain error, offset error, and quantization error.Note 5: For control byte (6) = 0, the sample rate is 1ksps. For control byte (6) = 1, the sample rate is 1.5ksps.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSHold Time (Repeated) START Condition tHD:STA 260 ns

Low Period of SCL tLOW 500 nsHigh Period of SCL tHIGH 260 ns

Data Hold Time tHD:DATReceive 0

nsTransmit 0 150

Data Setup Time tSU:DAT 50 nsStart Setup Time tSU:STA 260 nsSDA and SCL Rise Time tR 120 nsSDA and SCL Fall Time tF 6 120 nsStop Setup Time tSU:STO 260 nsNoise Spike Reject tSP 25 ns

Figure 1. I2C/SMBus Timing Diagram

Electrical Characteristics (continued)

Figure 1



VDD = VIO =3.3V, TA = +25C, VCM = 3.8V, VSENSE = 1mVTypical Operating Characteristics

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VDD = VIO =3.3V, TA = +25C, VCM = 3.8V, VSENSE = 1mVTypical Operating Characteristics

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

0

-40 25 85 -40 25 85 -40 25 85 -40 25 85

0.5V 1.0V 1.5V 2.5V

POWE

RER

ROR

%

TEMP (°C), VCM (V)

POWER ERROR PERCENT AT VSENSE = 95mVBEFORE AND AFTER CORRECTION

AFTER

BEFORE

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

-40 25 85 -40 25 85 -40 25 85 -40 25 85

0.5V 1.0V 1.5V 2.5V

POWE

RER

ROR

(%)

TEMP (°C), VCM (V)

POWER ERROR PERCENT ERROR AT VSENSE = 1mVBEFORE AND AFTER CORRECTION

AFTER

BEFORE

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PIN NAME FUNCTION

A1 IN2+External-Sense Resistor Power-Side Connection for Current-Sense Amplifier 2. Voltages can be applied to these pins in the absence of power being applied to VDD or VIO. Unused current-sense inputs should be tied together and left unconnected.

A2 IN1-External-Sense Resistor Load-Side Connection for Current-Sense Amplifier 1. Voltages can be applied to these pins in the absence of power being applied to VDD or VIO. Unused current-sense inputs should be tied together and left unconnected.

A3 IN1+External-Sense Resistor Power-Side Connection for Current-Sense Amplifier 1. Voltages can be applied to these pins in the absence of power being applied to VDD or VIO. Unused current-sense inputs should be tied together and left unconnected.

A4 VDD

Supply Voltage for Current-Sense Amplifiers. +2.7V to +3.6V supply. This pin should be decoupled to GND with a minimum 100nF ceramic capacitor. Power can be applied to VDD either before or after or in the absence of VIO.

B1 IN2-External-Sense Resistor Load-Side Connection for Current-Sense Amplifier 2. Voltages can be applied to these pins in the absence of power being applied to VDD or VIO. Unused current-sense inputs should be tied together and left unconnected.

B2 VIO

Supply Voltage for Digital Interface. +1.6V to +3.6V supply. This pin should be decoupled to GND with a minimum 100nF ceramic capacitor. Power can be applied to VIO either before or after or in the absence of VDD.

B3 PDNB Power-Down Mode Input. When this pin is tied low, the device is completely powered down including the I2C/SMBus interface.

B4 GND Ground Connection

Pin Configuration

16 WLP

TOP VIEW

MAX34417

+1 2 3 4

A

B

C

D

IN2+ IN1- IN1+ VDD

IN2- VIO PDNB GND

IN3- ADDR SLOW SCL

IN3+ IN4- IN4+ SDA

Pin Description



Detailed DescriptionThe MAX34417 automatically sequences through the channels to collect samples from the common-mode voltage and the current-sense amplifiers. The 16-bit current value and the 14-bit voltage value are then multiplied to create a 30-bit power value that is then written to the power accumulator.The MAX34417 contains a 56-bit power accumulator for each channel. This accumulator is updated 1024 times per second. When the host is ready to pull the latest accumulation data, it first sends the update command that causes the MAX34417 to load the latest accumulation data and accumulation count into the inter-nal MAX34417 registers so the host can read them at any time. This type of operation allows the host to control the accumulation period. The only constraint is that the host should access the data before the accumulators can over-flow. If the accumulators overflow, they do not roll over.The MAX34417 contains a 14-bit ADC for voltage and a 13-bit ADC for current. During each sample time, a 14-bit voltage sample and a 16-bit current sample are resolved. To create a 16-bit current value from the 13-bit ADC, the device takes two current samples; one with the current

sense amplifier in a high-gain mode and another with the amplifier in a low-gain mode. The high gain setting is 8 times the low-gain setting. Based on the two current-sense ADC results, the device determines which result provides the best accuracy and fills the 16-bit current sample accordingly.

SMBus operationThe MAX34417 uses the SMBus command/response format as described in the System Management Bus Specification Version 2.0. The structure of the data flow between the host and the slave is shown below for sev-eral different types of transactions. Data is sent MSB first. The fixed slave address of the MAX34417 is deter-mined on device power-up by sampling the resistor tied to the ADDR pin. See the Slave Address Setting section for details. On device power-up, the device defaults to the control command code (01h). If the host sends an invalid command code, the device does not acknowledge (NACK) the command code. If the host attempts to read the device with an invalid command code, all ones (FFh) are returned in the data byte.

PIN NAME FUNCTION

C1 IN3-External-Sense Resistor Load-Side Connection for Current-Sense Amplifier 3. Voltages can be applied to these pins in the absence of power being applied to VDD or VIO. Unused current-sense inputs should be tied together and left unconnected.

C2 ADDR I2C/SMBus-Compatible Address Select Input. A resistor tied to GND from this pin selects the SMBus slave address. See the Addressing section for more details.

C3 SLOW Slow Accumulate Mode Input. When this pin is tied high, the power accumulation is slowed to reduce overall device power consumption.

C4 SCL I2C/SMBus-Compatible Clock Input. SCL does not load the SMBus when either VDD or VIO is not present.

D1 IN3+External-Sense Resistor Power-Side Connection for Current-Sense Amplifier 3. Voltages can be applied to these pins in the absence of power being applied to VDD or VIO. Unused current-sense inputs should be tied together and left unconnected.

D2 IN4-External-Sense Resistor Load-Side Connection for Current-Sense Amplifier 4. Voltages can be applied to these pins in the absence of power being applied to VDD or VIO. Unused current-sense inputs should be tied together and left unconnected.

D3 IN4+External-Sense Resistor Power-Side Connection for Current-Sense Amplifier 4. Voltages can be applied to these pins in the absence of power being applied to VDD or VIO. Unused current-sense inputs should be tied together and left unconnected.

D4 SDA I2C/SMBus-Compatible Data Input/Output. Output is open drain. SDA does not load the SMBus when either VDD or VIO is not present.

Pin Description (continued)



R = Read Bit (1)A = Acknowledge (0)NA = Not Acknowledge (1)Shaded Block = Slave Transaction

Table 1. Read Byte Format

Table 2. Write Byte Format

Table 3. Send Byte Format

Table 4. Block Read Format

Table 5. Bulk Read Format

1 7 1 1 8 1 1 7 1 1 8 1 1

S Slave Address W A Command

Code A SR Slave Address R A Data

Byte NA P

1 7 1 1 8 1 8 1 1


Code A Data Byte A P

1 7 1 1 8 1 1


Code A P

1 7 1 1 8 1 1 7 1 1 8 1


Code A SR Slave Address R A Byte

Count A …

8 1 8 1 1

… Data Byte 1 - MSB A … Data Byte

N - LSB NA P

1 7 1 1 8 1 1 7 1 1 8 1


Code A SR Slave Address R A Byte

Count A …

… Channel 4

8 1 8 1 1

… Data Byte 1 - MSB A … Data Byte

N - LSB NA P

Key:S = StartSR = Repeated StartP = StopW = Write Bit (0)

Note: In multibyte reads, the most significant byte is the first Data Byte read.



Slave Address SettingThe MAX34417 responds to receiving it’s fixed slave address by asserting an ACK on the bus. The fixed slave address of the MAX34417 is determined on device power up by sampling the voltage across a resistor tied to the ADDR pin after VDD rises to a valid value. See the table below for more details. The device will not respond to a general call address. It will be activated only when receiving its fixed slave address or the broadcasting address, 2Ch, for Global Update. Upon sending "00" to slave address 2Ch, all MAX34417 ICs connecting to the I2C will be updated.

On power up or when PDNB toggles from low to high, a current of 100µA is applied to the RADDR and the voltage is measured. The binary slicing value is compared to the ADC result. An ADC value that is below the slicing value but not below the adjacent lower slicing value selects the Slave Address. The selected values will tolerate a total error of ±30% in the measurement to account for errors in the current value, resistor value, ADC gain error, etc.. As shown, the 3 LSB of the ADC value are not needed for the comparison.

Table 6. SMBUS Slave Address SelectRADDR (±1%) (Ω) SLAVE ADDRESS SLICING VOLTAGE SLICING ADC VALUE VOLTAGE RANGE

(MV)Tie to ground 001 0000 (10h) 0 – 35

499 001 0010 (12h) 35mV '000001001000 35 – 65931 001 0100 (14h) 65mV '000010000000 65 – 120

1740 001 0110 (16h) 120mV '000011111000 120 – 2243160 001 1000 (18h) 224mV '000111001000 224 – 4165900 001 1010 (1Ah) 416mV '001101010000 416 – 77211000 001 1100 (1Ch) 772mV '011000110000 772 – 143320500 001 1110 (1Eh) 1433mV '101101111000 1433 – VDD



Command CodesTable 7. Command Codes

COMMAND CODE NAME DETAILED DESCRIPTION TYPE NUMBER OF

BYTESPOR

(NOTE 1)00h UPDATE Request Accumulator Update Send Byte 0 -01h CONTROL Device Configuration and Status R/W Byte 1 00h02h ACC_COUNT Accumulator Counter Block Read 3 Note 203h PWR_ACC_1 Power Accumulator for Channel 1 Block Read 7 Note 204h PWR_ACC_2 Power Accumulator for Channel 2 Block Read 7 Note 205h PWR_ACC_3 Power Accumulator for Channel 3 Block Read 7 Note 206h PWR_ACC_4 Power Accumulator for Channel 4 Block Read 7 Note 207h V_CH1 Voltage for Channel 1 Block Read 2 Note 208h V_CH2 Voltage for Channel 2 Block Read 2 Note 209h V_CH3 Voltage for Channel 3 Block Read 2 Note 20Ah V_CH4 Voltage for Channel 4 Block Read 2 Note 20Fh DID Device ID and Revision Read Byte 1 Note 3

00h BULK UPDATE Slave address = 2Ch followed by command code = 00h Send Byte 0 Note 4

10h Bulk Power Readout

Read all accumulators in bulk mode starting with channel 1 Block Read 28 Note 5

11h Bulk Voltage Readout

Read all voltages in bulk mode starting with channel 1 Block Read 8

Notes:1) The acronym POR means Power-On Reset and this is the default value when power is applied to the device.2) These registers are set to all zeros upon POR.3) The Device ID is factory set and will vary based on the die revision.4) Slave Address 2Ch is a broadcast address for Global Update to all MAX34417.5) 28 bytes if Control[7] = 1, else, 24 byte



Command Codes Bit DescriptionUpdate (00h) – Send ByteThe update send byte command does not contain any data. Each time the device receives this command, it completes an accumulation cycle for the four channels

(if not already complete) and then it transfers all of the accumulation data in the power accumulators and the accumulator counter to a set of registers that can be read with the SMBus interface and it resets all of the counters/accumulation registers. An update command does not clear the OVF bit.

Figure 2. MAX34417 SMBus Register Structure

ACCUMULATOR COUNTER (24 BITS)

POWER ACCUMULATOR FOR CHANNEL 1 (56 BITS)




OR

ACC_COUNT (02h)

PWR_ACC_1 (03h)

PWR_ACC_2 (04h)

PWR_ACC_3 (05h)

PWR_ACC_4 (06h)

UPDATE (00h)

SMBus COMMANDSUPDATE COMMAND

TRANSFERS AND RESETS ALL ACCUMULATORS

INTERNAL REAL-TIME COUNTERS

CONTROL (01h)

OVERFLOW ON ANY ACCUMULATOR SETS

THE OVF BIT



Bit 7: MAX34407/MAX34417When this bit is at 0, the accumulators are 48-bits wide and the voltage readout is 12-bit left-justified to a 16-bit field. The power calculated is still 30-bit wide. When the bit is set, the accumulators are 56 wide and the voltage readout is 14 bit left-justified to a 16-bit field.0 = MAX344071 = MAX34417Bit 6: CAMContinuous Accumulate Mode. When this bit is set, the inputs are measured and accumulated continuously with-out idle periods. After setting this bit, an UPDATE com-mand must be issued to start the accumulation cycles. The subsequent UPDATE command will move the data to the SMBus registers, reset the accumulators, and start the continuous accumulation cycle process. SMM and CAM modes should not be enabled at the same time.0 = CAM mode not active.1 = CAM Mode enabled.Note that changing any Control byte settings while CAM bit is enabled is disallowed. If CAM mode must be set, the Control byte must be set to desired values with CAM = 0, then followed by an UPDATE. After this, the CAM mode bit can be set and another UPDATE must be sent.Bit 5: SMMSingle Measure Mode. When this bit is set, the device will perform only one measure and accumulation cycle for the four input channels (normal scan mode) or four samples of one channel in Park mode in response to an UPDATE command. The data can be read by issuing another UPDATE command which moves the previous UPDATE

data into the SMBus read registers and starts another mea-surement cycle. Data should be read between UPDATE commands. UPDATE commands should be no less than 1msec apart for reliable measurements. The power accumulators remain at 56-bits even though the single calculated power is a 30-bit value. After the SMM bit is changed, the UPDATE command should be sent to reset the accumulators and perform the selected scan opera-tion. SMM and CAM modes should not be enabled at the same time.0 = Normal scan and accumulate operation.1 = SMM Mode enabled.Bit 4: PARK_ENThis bit enables the channel park feature. If this bit is set, only one channel will be enabled and the device will sample the selected channel four times faster than the normal round-robin rate. The channel to monitor is select-ed with the PARK0 and PARK1 bits. After the PARK_EN bit is changed, the UPDATE command should be sent to clear out the accumulators and start a new accumulation period. When the channel park feature is enabled, the minimum time before the power accumulators can over-flow reduces by a factor of four since the selected chan-nel is being updated four times faster. Also, the power accumulators for the disabled channels do not contain any meaningful data.0 = Round Robin Sampling of All Four Channels.1 = One Channel Selected (with the PARK0/1 bits).Bits 3 to 2: PARK1 to PARK0If the PARK_EN (Park Enable) bit is set, then these bits select which channel is to be monitored at the exclusion of the other channels.

Control (01h) – R/W ByteTable 8. Control (01h)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0NAME: Mode CAM SMM PARK_EN PARK1 PARK0 SLOW OVFPOR: 0 0 0 0 0 0 0 0

Table 9. PARK Channel SelectiionPARK1 PARK0 SELECTED CHANNEL

0 0 Channel 10 1 Channel 21 0 Channel 31 1 Channel 4



Bit 1: SLOWThis bit is logically OR’ed with the SLOW input pin. If either this bit is set or the SLOW pin is high, then the power accu-mulation calculation rate is slowed in order to lower the power consumption of the device.Bit 0: OVFThis status bit will be set to a one if any of the power accumulators or the accumulator counter reach overflow. When the accumulators or counter overflow, they will not rollover. Any active sequencing or accumulation mode will stop and the device will halt in the idle state. A UPDATE command will clear the accumulators and the accumulation counter, thus clearing the OVF condition, as well as resuming the selected accumulation mode sequence. The OVF bit in the control register is not cleared by an UPDATE command. This status bit must be cleared by writing a 0.Accumulator Counter (02h) – Block Read

Table 10. Accumulator Counter (02h)BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16

NAME: CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16POR: 0 0 0 0 0 0 0 0

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8NAME: CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8POR: 0 0 0 0 0 0 0 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0NAME: CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0POR: 0 0 0 0 0 0 0 0



Bits 23 to 0: CNT23 to CNT0These bits report the number of accumulations since the last UPDATE command. The UPDATE command copies the count into this I2C data register. By dividing the total accumulated power reported in each power accumulator by this count, the average power can be determined. The accumulator counter does not rollover.Power Accumulator for Channel 1 (03h) – Block ReadPower Accumulator for Channel 2 (04h) – Block ReadPower Accumulator for Channel 3 (05h) – Block ReadPower Accumulator for Channel 4 (06h) – Block Read

Table 11. Power AccumulatorNAME: BIT 55 BIT 54 BIT 53 BIT 52 BIT 51 BIT 50 BIT 49 BIT 48

POR: ACC55 ACC54 ACC53 ACC52 ACC51 ACC50 ACC49 ACC480 0 0 0 0 0 0 0

Bit 47 Bit 46 Bit 45 Bit 44 Bit 43 Bit 42 Bit 41 Bit 40NAME: ACC47 ACC46 ACC45 ACC44 ACC43 ACC42 ACC41 ACC40POR: 0 0 0 0 0 0 0 0








Bits 55 to 0: ACC55 to ACC0These bits report the total power accumulated by each channel. The UPDATE command moves the data in the accumulators into these registers in the I2C logic from where they are read. The power accumulators will not rollover. This is an unsigned, binary number. If the value in the accumulator is negative, this register will read 000000000000h.Voltage for Channel 1 (07h) – Block ReadVoltage for Channel 2 (08h) – Block ReadVoltage for Channel 3 (09h) – Block ReadVoltage for Channel 4 (0Ah) – Block Read

Bits 15 to 0: V15 to ACC0These bits report the voltage on the IN- pin of each channel at the approximate time of the last UPDATE command. It is an unsigned, binary value. The 14-bit value is in bits 15:2.Device ID and Revision Register (0Fh) – Read Byte

Device ID and Revision Register (0Fh)Bits 7 to 3: ID4 to ID0These bits report the device identification (ID). The ID is fixed at 07h.Bits 2 to 0: REV2 to REV0These bits report the device revision. The device revision is factory set.

Table 12. Voltage Read

Table 13. Device ID and Revision

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8NAME: V15 V14 V13 V12 V11 V10 V9 V8POR: 0 0 0 0 0 0 0 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0NAME: V7 V6 V5 V4 V3 V2 0 0POR: 0 0 0 0 0 0 0 0

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0NAME: ID4 ID3 ID2 ID1 ID0 REV2 REV1 REV0POR: 0 0 1 1 1 Factory set



Applications InformationAverage Power Calculation ExampleThe average power can be derived in an external calculation, as shown below, if the current sense resistor value is known.Power accumulator (56 bit) = 000001CEFBD314h (7767577364 decimal)Accumulator counter (24 bit) = 0005DEh (1502 decimal)Current-sense resistor = 10mΩ

Step 1Calculate the unscaled average power by dividing the power accumulator value with the accumulator count value:000001CEFBD314h/0005DEh = 4EE921h (5171489 decimal)

Step 2Calculate the ratio of the Step 1 result to the calculated power full-scale value which is a 30-bit value:5171489/230 = 0.004816324

Step 3Multiply the result from Step 2 by the correction factor listed in Table 8 that matches the current-sense resistor value:0.004816324 x 240 = 1.156W

Perr_Verr CorrectionWhen the VCM ≤ 2.0V, a correction can be applied to improve power accuracy. The correction must be used only when greater than or equal to 1000 samples are accumulated to avoid truncation errors from integer math if done on a microcontroller platform.ACCUMULATOR = Accumulator reading for a channelACCUM_COUNT = Accumulator count reading from the deviceVOLTAGE = Voltage reading for a channel.The steps include1) Power = ACCUMULATOR/ACCUM_COUNT2) Current = Power/(VOLTAGE/4)3) Adjusted Voltage, VADJ = VOLTAGE/4 – VERR,

where VERR is as shown below. a. VERR = 3 if 0.5 ≥ VCM < 1.0 b. VERR = 2 if 1.0 ≥ VCM < 1.5 c. VERR = 1 if 1.5 ≥ VCM < 2.0

4) Adjusted Power, PADJ = Current x VADJ5) Adjusted Accumulator = PADJ x ACCUM_COUNTIf there is a residue from operation ‘2’ above, it may be added to PADJ in step 5.

Correction Factors for Various Current-Sense Resistor ValuesTable 14. Correction Factors for Various Current-Sense Resistor Values

CURRENT-SENSE RESISTOR VALUE

(MΩ)

FULL-SCALE CURRENT

(A)

FULL-SCALE VOLTAGE

(V)

POWER SCALE CORRECTIONCALCULATION

POWER SCALE CORRECTION FACTOR

(W)100 1 24 1 x 24 2450 2 24 2 x 24 4840 2.5 24 2.5 x 24 6025 4 24 4 x 24 9620 5 24 5 x 24 12015 6.66667 24 6.667 x 24 16010 10 24 10 x 24 2405 20 24 20 x 24 4804 25 24 25 x 24 6002 50 24 50 x 24 12001 100 24 100 x 24 2400



Kelvin SenseFor best performance, a Kelvin sense arrangement is recommended (see Figure 2). In a Kelvin sense arrangement, the voltage-sensing nodes across the sense element are placed so that they measure the true voltage drop across the sense element and not any additional excess voltage drop that can occur in the copper PCB traces or the solder mounting of the sense element. Routing the differential sense lines along the same path to the MAX34417 and keeping the path short also improve the system performance.

Minimizing Trace ResistancePCB trace resistance from the sense resistor (RSENSE) to the IN- inputs can affect the MAX34417 power mea-surement accuracy. Every 1Ω of PCB trace resistance in the IN- path will add about 25μV of offset error. It is recommended to place the sense resistors as close as possible to the MAX34417 and not to use minimum width PCB traces. When placing an RC filter at the input, the resistor must be placed in the IN+ input path to reduce DC errors from the trace resistance.

Figure 3. Kelvin Sense Connection Layout Example

COPPER TRACE

CURRENT PATH

KELVIN CONNECTIONS

IN+ IN-

SENSE RESISTOR OUTLINE ROUTE SENSE LINES ALONG THE SAME PATH



Figure 4. Top Mark

Top Marking



PART NUMBER TEMP RANGE PIN-PACKAGE

MAX34417ENE+ -40°C to +85°C 16 Thin-WLP with 0.4mm Pitch

MAX34417ENE+T -40°C to +85°C 16 Thin-WLP with 0.4mm Pitch

+Denotes a lead(Pb)-free/RoHS-compliant package.T = Denotes tape-and-reel.

CHANNEL-4CHANNEL-3

CHANNEL-2

CHANNEL-1

MUX

X1/X8

ADC

AUTOMATIC SEQUENCING OSCILLATOR

Current(13/16-BIT)

Voltage(14-BIT)

REGISTERS

POWERACCUMULATOR

(56-BIT)

POWER RESULT(30 BIT)

POWERCONTROL

SMBUSINTERFACE

DIGITALCONTROL

INTERFACE

SCLSDAPDNBSLOW

ADDR

VCC

GND

VIO

INxP

INxN

RADDR

CURRENTFLOW

VREF

Typical Application Circuits

Ordering Information



REVISIONNUMBER

REVISIONDATE DESCRIPTION PAGES

CHANGED0 12/17 Initial release —

Revision History

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2017 Maxim Integrated Products, Inc. │ 22


For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

max34417 smbs or-channel hih dnaic rane poer acclatormonitored with a standard i2c/smbus serial...

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