max1737 stand-alone switch-mode lithium-ion battery-charger controller
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General Description
The MAX1737 is a switch-mode lithium-ion (Li+) batterycharger that charges one to four cells. It provides aregulated charging current and a regulated voltagewith only a 0.8% total voltage error at the battery ter-minals. The external N-channel switch and synchronousrectifier provide high efficiency over a wide input volt-age range. A built-in safety timer automatically termi-nates charging once the adjustable time limit has beenreached.
The MAX1737 regulates the voltage set point and charg-ing current using two loops that work together to transi-tion smoothly between voltage and current regulation. Anadditional control loop monitors the total current drawnfrom the input source to prevent overload of the input
supply, allowing the use of a low-cost wall adapter.The per-cell battery voltage regulation limit is setbetween +4.0V and +4.4V and can be set from one tofour by pin strapping. Battery temperature is monitoredby an external thermistor to prevent charging if the bat-tery temperature is outside the acceptable range.
The MAX1737 is available in a space-saving 28-pinQSOP package. Use the evaluation kit (MAX1737EVKIT)to help reduce design time.
Applications
Features
Stand-Alone Charger for Up to Four Li+ Cells 0.8% Accurate Battery Regulation Voltage
Low Dropout: 98% Duty Cycle
Safely Precharges Near-Dead Cells
Continuous Voltage and Temperature Monitoring
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDCIN = VCSSN = VCSSP = +18V, SHDN= VL, CELL = GND, VBATT = VCS = +4.2V, VVADJ = VREF/ 2, ISETIN =ISETOUT = REF, RTHM = 10k, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.
CSSP, CSSN, DCIN to GND... .............................. ..-0.3V to +30V
BST, DHI to GND....................................................-0.3V to +36V
BST to LX..................................................................-0.3V to +6V
DHI to LX ............................. .............-0.3V to ((BST - LX) + 0.3V)
LX to GND ............................. ..................-0.3V to (CSSN + 0.3V)
FULLCHG, FASTCHG, FAULTto GND ..................-0.3V to +30VVL, VLO,SHDN, CELL, TIMER1, TIMER2, CCI,
CCS, CCV, REF, ISETIN, ISETOUT, VADJ,
THM to GND........................................................-0.3V to +6V
DLO to GND...............................................-0.3V to (VLO + 0.3V)
BATT, CS to GND...................................................-0.3V to +20V
PGND to GND, CSSP to CSSN..............................-0.3V to +0.3V
VL to VLO ............................. ............................... ..-0.3V to +0.3V
VL Source Current...............................................................50mA
Continuous Power Dissipation (TA = +70C)
28-Pin QSOP (derate 10.8mW/C above +70C)........860mW
Operating Temperature Range ...........................-40C to +85C
Junction Temperature......................................................+150C
Storage Temperature Range ........................... ..-65C to +150C
Lead Temperature (soldering, 10s) ............................ .....+300C
VREF Output Voltage
SWITCHING REGULATOR
SUPPLY AND REFERENCE
With 1% VADJ resistors -1 +1Absolute Voltage Accuracy
Not including VADJ resistor tolerances -0.8 +0.8%
VVADJ = REF
VVADJ = GND
4.386 4.421 4.453
PARAMETER CONDITIONS MIN TYP MAX UNITS
6.0V < VDCIN < 28V
SHDN= GND, VBATT = 19V
LX = VDCIN = 28V, SHDN= GND
IREF = 0 to 1mA
6V < VDCIN < 28V
VCSSN = VCSSP = VDCIN = 28V,SHDN= GND
In dropout fOSC/ 4, VCCV = 2.4V,
VBATT = 15V, CELL = VL
6.0V < VDCIN < 28V
VBATT = 15V, CELL = VL
IVL = 0 to 15mA
A0.1 5
BATT, CS Input Current
A0.1 10LX Leakage
7DHI, DLO On-Resistance
A2 10CSSN + CSSP Off-State Leakage
%97 98LX Maximum Duty Cycle
kHz270 300 330PWM Oscillator Frequency
mA5 7DCIN Quiescent Supply Current
V6 28DCIN Input Voltage Range
mV6 14REF Load Regulation
mV2 6REF Line Regulation
4.179 4.20 4.221
V0.05 0.155DCIN to BATT Undervoltage Threshold,
DCIN Falling
V0.19 0.40DCIN to BATT Undervoltage Threshold,
DCIN Rising
V5.10 5.40 5.70VL Output Voltage
mV44 65VL Output Load Regulation
225 500CELL = SHDN= VL, VBATT = 17VBATT, CS Input Voltage Range
Battery Regulation Voltage (VBATTR) CELL = float, GND, VL, or REF (Note 1)
0 19
4.167 4.2 4.233
V
V/cell
Battery Regulation Voltage Adjustment
RangeVCCV = 2V
3.948 3.979 4.010V/cell
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ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSN = VCSSP = +18V,SHDN
= VL, CELL = GND, VBATT = VCS = +4.2V, VVADJ = VREF/ 2, ISETIN =ISETOUT = REF, RTHM = 10k, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
Full-Charge Timer 81 90 100 min
Fast-Charge Timer 81 90 100 min
BATT Overvoltage Threshold (Note 5) 4.55 4.67 4.8 V/cell
BATT Charge Current Full-ChargeTermination Threshold CS-BATT (Note 6)
35 44 55 mV
BATT Recharge Voltage Threshold (Note 7) 94 95 96% of
VBATTR
TIMER1, TIMER2 Oscillation Frequency 2.1 2.33 2.6 kHz
Prequalification Timer 6.25 7.5 8.75 min
CCI, CCS Clamp Voltage with Respect
to CCV25 200 mV
CCV Clamp Voltage with Respect
to CCI, CCS25 200 mV
THM Trip-Threshold Voltage 1.386 1.4 1.414 V
THM Low-Temperature Current 46.2 49 51.5 A
THM High-Temperature Current 344 353 362 A
THM COLD Threshold Resistance (Note 3) 26.92 28.70 30.59 k
THM HOT Threshold Resistance (Note 3) 3.819 3.964 4.115 k
BATT Undervoltage Threshold (Note 4) 2.4 2.5 2.6 V/cell
THM low-temperature or high-temperature
current
VTHM = 1.4V
VTHM = 1.4V
Combines THM low-temperature current and
THM rising threshold, VTRT/ITLTC
Combines THM high-temperature current and
THM rising threshold, VTRT/ITHTC
CCV Amplifier Transconductance (Note 2) 0.39 0.584 0.80 mS
CCV Amplifier Maximum Output Current 50 A
CS to BATT Current-Sense Voltage 30 40 50 mV
CS to BATT Full-Scale Current-Sense
Voltage185 200 215 mV
CS to BATT Current-Sense Voltage When in
Prequalification State5 10 15 mV
CS to BATT Hard Current-Limit Voltage 355 385 415 mV
CSSP to CSSN Current-Sense Voltage 10 20 30 mV
CSSP to CSSN Full-Scale
Current-Sense Voltage90 105 115 mV
CCI Amplifier Transconductance 0.6 1 1.4 mS
CCI Amplifier Output Current 100 A
CCS Amplifier Transconductance 1.2 2 2.6 mS
CCS Amplifier Output Current 100 A
4.15V < VBATT < 4.25V, VCCV = 2V
3.5V < VBATT < 5V, VCCV = 2V
VISETOUT = VREF/ 5
VBATT = 3V to 17V, CELL = GND or VL
VBATT < 2.4V per cell
6V < VCSSP < 28V, VISETIN = VREF/ 5,
VCCS = 2V
6V < VCSSP < 28V, VCCS = 2V
VCCI = 2V
VCS - VBATT = 0, 400mV
ISET = REF, VCCS = 2V
VCSSP - VCSSN = 0, 200mV
PARAMETER MIN TYP MAX UNITSCONDITIONS
STATE MACHINE
ERROR AMPLIFIERS
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ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSN = VCSSP = +18V,SHDN
= VL, CELL = GND, VBATT = VCS = +4.2V, VVADJ = VREF/ 2, ISETIN =ISETOUT = REF, RTHM = 10k, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
CELL Input Voltage
0 0.5
1.5 2.5
VREF - 0.3 VREF + 0.3V
VVL - 0.4 VVL
FASTCHG, FULLCHG, FAULTOutput Low Voltage
0.5 V
FASTCHG, FULLCHG, FAULTOutput HighLeakage 1 A
For 1 cell
For 2 cells
For 3 cells
For 4 cells
ISINK = 5mA
FASTCHG, FULLCHG,FAULT= 28V;SHDN= GND
Top-Off Timer 40.5 45 49.8 min
SHDNInput Voltage High 1.4 V
SHDNInput Voltage Low (Note 8) 0.6 V
VADJ, ISETIN, ISETOUT Input Voltage
Range0 VREF V
VADJ, ISETIN, ISETOUT
Input Bias CurrentnA-50 50
SHDNInput Bias Current -1 1 A
CELL Input Bias Current -5 5 A
ISETIN Adjustment Range VREF/ 5 V REF V
ISETOUT Adjustment Range VREF/ 5 V REF V
ISETOUT Voltage for ICHG = 0 150 220 300 mV
VVADJ, VISETIN, VISETOUT = 0 or 4.2V
SHDN= GND or VL
PARAMETER MIN TYP MAX UNITSCONDITIONS
Temperature Measurement Frequency 0.98 1.12 1.32 Hz1nF on TIMER1 and TIMER2
CONTROL INPUTS/OUTPUTS
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ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDCIN = VCSSN = VCSSP = +18V,SHDN
= VL, CELL = GND, VBATT = VCS = +4.2V, VVADJ = VREF/ 2, ISETIN =ISETOUT = REF, RTHM = 10k, TA = -40C to +85C, unless otherwise noted.) (Note 9)
PARAMETER CONDITIONS MIN MAX UNITS
DCIN Input Voltage Range
VL Output Voltage
REF Output Voltage
REF Line Regulation
PWM Oscillator Frequency
DHI, DLO On-Resistance
BATT, CS Input Voltage Range
Battery Regulation Voltage (VBATTR)
Absolute Voltage Accuracy
CS to BATT Current-Sense Voltage
CS to BATT Full-Scale Current-Sense
Voltage
CS to BATT Current-Sense Voltage When in
Prequalification State
CS to BATT Hard Current-Limit Voltage
CSSP to CSSN Current-Sense Voltage
CSSP to CSSN Full-Scale Current-SenseVoltage
THM Trip-Threshold Voltage
THM Low-Temperature Current
THM COLD Threshold Resistance (Note 3)
BATT Undervoltage Threshold (Note 4)
BATT Overvoltage Threshold (Note 5)
BATT Charge Current Full-Charge
Termination Threshold, CS-BATT (Note 6)
Temperature Measurement Frequency 1nF on TIMER1 and TIMER2
4.55 4.8 V/cell
35 55 mV
0.93 1.37 Hz
6.0V < VDCIN < 28V
6V < VDCIN < 28V
VBATT = 15V, CELL = VL
CELL = float, GND, VL, or REF
Not including VADJ resistor tolerances
VISETOUT = VREF/ 5
VBATT = 3V to 17V, CELL = GND or VL
VBATT < 2.4V per cell
6V < VCSSP < 28V, VISETIN = VREF/ 5,
VCCS = 2V
6V < VCSSP < 28V, VCCS = 2V
THM low-temperature or high-temperature current
VTHM = 1.4V
Combines THM low-temperature current and
THM rising threshold, VTRT/ITLTC
260 340 kHz
6 mV
4.166 4.242 V
7
0 19 V
4.158 4.242 V/cell
-1 1 %
6 28 V
5.1 5.7 V
25 55 mV
180 220 mV
3 17 mV
350 420 mV
5 35 mV
85 115 mV
1.386 1.414 V
46.2 51.5 A
26.92 30.59 k
2.4 2.6 V/cell
SUPPLY AND REFERENCE
SWITCHING REGULATOR
ERROR AMPLIFIERS
STATE MACHINE
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ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSN = VCSSP = +18V,SHDN
= VL, CELL = GND, VBATT = VCS = +4.2V, VVADJ = VREF/ 2, ISETIN =ISETOUT = REF, RTHM = 10k, TA = -40C to +85C, unless otherwise noted.) (Note 9)
Note 1: Battery Regulation Voltage = Number of Cells (3.979V + 0.10526 VVADJ).Note 2: This transconductance is for one cell. Divide by number of cells to determine actual transconductance.
Note 3: See Thermistorsection.
Note 4: Below this threshold, the charger reverts to prequalification mode and I CHG is reduced to about 5% of full scale.
Note 5: Above this threshold, the charger returns to reset.
Note 6: After full-charge state is complete and peak inductor current falls below this threshold, FULLCHGoutput switches high.Battery charging continues until top-off timeout occurs.
Note 7: After charging is complete, when BATT voltage falls below this threshold, a new charging cycle is initiated.Note 8: In shutdown, charging ceases and battery drain current drops to 5A (max), but internal IC bias current remains on.
Note 9: Specifications to -40C are guaranteed by design and not production tested.
SHDNInput Voltage Low (Note 8) 0.6 V
SHDNInput Voltage High 1.4 V
PARAMETER MIN TYP MAX UNITSCONDITIONS
CONTROL INPUTS/OUTPUTS
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0
1.0
0.5
2.5
2.0
1.5
4.0
3.5
3.0
4.5
0 1.00.5 1.5 2.0 2.5
BATTERY VOLTAGE
vs. CHARGING CURRENT
MAX1737toc01
CHARGING CURRENT (A)
BATTERYVOLTAGE(V)
R18 = 0.1
0
50
25
125
100
75
175
200
150
225
0 1.5 2.00.5 1.0 2.5 3.0 3.5 4.0 4.5
CHARGING CURRENT-SENSE VOLTAGE
vs. ISETOUT VOLTAGE
MAX1737toc02
ISETOUT VOLTAGE (V)
CHARGINGCURRENT-SENSEVOLTAGE(mV)
0
20
40
60
80
100
120
0 1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5
INPUT CURRENT-SENSE VOLTAGE
vs. ISETIN VOLTAGE
MAX1737toc03
ISETIN VOLTAGE (V)
INPUTCURRENT-SENSEVOLTAGE(mV)
3.95
4.05
4.00
4.15
4.10
4.25
4.20
4.30
4.40
4.35
4.45
0 1.0 1.5 2.00.5 2.5 3.0 3.5 4.0 4.5
VOLTAGE LIMIT vs. VADJ VOLTAGE
MAX1737toc04
VADJ VOLTAGE (V)
V
OLTAGELIMIT(V)
4.175
4.185
4.180
4.195
4.190
4.200
4.205
-40 20 40-20 0 60 80 100
REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1737toc05
TEMPERATURE (C)
REFE
RENCEVOLTAGE(V)
50
60
70
80
90
100
8 12 16 20 24 28
EFFICIENCY vs. INPUT VOLTAGE
MAX1737toc06
INPUT VOLTAGE (V)
EFFICIENCY(%)
CELL = FLOAT (2 CELLS)VBATT = 7VR18 = 0.1 (IBATT = 2A)
4.190
4.194
4.192
4.198
4.196
4.202
4.200
4.204
4.208
4.206
4.210
0 200 300 400100 500 600 700 900800 1000
REFERENCE LOAD REGULATION
MAX1737toc07
REFERENCE CURRENT (A)
REFERENCEVOL
TAGE(V)
1000
0.10.1 1 10
TIMEOUT vs. TIMER1 CAPACITANCE
1
MAX1737toc08
CAPACITANCE (nF)
TIMEOUT(MINUTES)
10
100
PREQUALIFICATION MODE
TOP-OFF MODE
FULL-CHARGEMODE
1000
10.1 1 10
FAST-CHARGE TIMEOUT
vs. TIMER2 CAPACITANCE
10
MAX1737toc09
CAPACITANCE (nF)
TIMEOUT(MINUTES) 100
Typical Operating Characteristics
(Circuit of Figure 1, VDCIN = +18V, ISETIN = ISETOUT = REF, VVADJ = VREF/ 2, TA = +25C, unless otherwise noted.)
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Pin Description
Source Current-Sense Positive Input. See Input Current Regulatorsection.CSSP27
Power-Supply Input. DCIN is the input supply for the VL regulator. Bypass DCIN to GND with a
0.1F capacitor. Also used for the source undervoltage sensing.DCIN28
Synchronous-Rectifier MOSFET Gate-Drive Bias. Bypass VLO to PGND with a 0.1F capacitor.VLO22
High-Side MOSFET Gate Drive Bias. Connect a 0.1F or greater capacitor from BST and LX.BST23
Power Inductor Switching Node. Connect LX to the high-side MOSFET source.LX24High-Side MOSFET Gate-Drive OutputDHI25
Source Current-Sense Negative Input. See Input Current Regulatorsection.CSSN26
Shutdown Input. DriveSHDN low to disable charging. Connect SHDNto VL for normaloperation.
SHDN18
Battery Current-Sense Positive Input. See Charging Current Regulatorsection.CS19
Power GroundPGND20
Synchronous-Rectifier MOSFET Gate-Drive OutputDLO21
Full-Charge Indicator. Open-drain output pulls low when charging with constant voltage in
full-charge state.FULLCHG17
Fast-Charge Indicator. Open-drain output pulls low when charging with constant current.FASTCHG16
Charge Fault Indicator. Open-drain output pulls low when charging terminates abnormally
(Table 1).FAULT15
Timer 2 Adjustment. Connect a capacitor from TIMER2 to GND to set the fast-charge time. See
Timerssection.TIMER214
Voltage Regulation Loop Compensation PointCCV9
Input Source Current Regulation Compensation PointCCS10
Battery-Current Regulation Loop Compensation PointCCI11
Cell-Count Programming Input. See Table 2CELL12
Timer 1 Adjustment. Connect a capacitor from TIMER1 to GND to set the prequalification,
full-charge, and top-off times. See Timerssection.TIMER113
4.2V Reference Voltage Output. Bypass REF to GND with a 1F or larger ceramic capacitor.REF5
Analog GroundGND6
Battery Voltage-Sense Input and Current-Sense Negative InputBATT7
Voltage Adjust. Use a voltage-divider to set the VADJ voltage between 0 and V REF to adjust the
battery regulation voltage by 5%. See Setting the Voltage Limitsection.VADJ8
Thermistor Input. Connect a thermistor from THM to GND to set a qualification temperature
range. If unused, connect a 10k resistor from THM to ground. See Thermistorsection.THM4
Battery Charging Current Adjust. Use a voltage-divider to set the voltage between 0 and V REF.
See Charging Current Regulatorsection.ISETOUT3
PIN
Input Current Limit Adjust. Use a voltage-divider to set the voltage between 0 and V REF.
See Input Current Regulatorsection.ISETIN2
Chip Power Supply. Output of the 5.4V linear regulator from DCIN. Bypass VL to GND with a
2.2F or larger ceramic capacitor.VL1
FUNCTIONNAME
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Detailed Description
The MAX1737 includes all of the functions necessary tocharge between one and four series Li+ battery cells. Itincludes a high-efficiency synchronous-rectified step-down DC-DC converter that controls charging voltageand current. It also includes input source-current limit-ing, battery temperature monitoring, battery undervolt-age precharging, battery fault indication, and a statemachine with timers for charge termination.
The DC-DC converter uses an external dual N-channelMOSFET as a switch and a synchronous rectifier to
convert the input voltage to the charging current or volt-age. The typical application circuit is shown in Figure 1.Figure 2 shows a typical charging sequence andFigure 3 shows the block diagram. Charging current isset by the voltage at ISETOUT and the voltage acrossR18. The battery voltage is measured at the BATT pin.The battery regulation voltage is set to 4.2V per celland can be adjusted 5% by changing the voltage atthe VADJ pin. By limiting the adjust range, the voltage
27
26
22
23
25
24
21
20
19
7
4
28 CSSPDCIN
CSSN
VLO
BST
DHI
LX
DLO
PGND
CS
BATT
THM
REF
ISETIN
VL
SHDN
ISETOUT
VADJ
CELL
GND
CCV
CCI
CCS
TIMER1
TIMER2
R12
Li+BATTERY(1 TO 4 CELLS)
L1R1822H
FAULT
FULLCHGFULL CHARGE
FAST CHARGE
FAULT
FASTCHG
C647nF
C131nF
C14
1nF
1nF
C547nF
C4
C31F
C14.7F C18
22FC1922F
SYSTEMLOAD
INPUTSUPPLY
C20.1F
C7
0.1F
C8
0.1F
R110k
R8
D1
D3
D2
R9
0.1F
16
11
9
6
12
3
8
2
5
18
1
10
13
14
17
15
0.1F
0.1F
C1568F
C90.1F
C110.1F
C100.1F
MAX1737
++
THERMISTOR
Figure 1. Typical Application Circuit
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accuracy is better than 1% while using 1% settingresistors.
The MAX1737 includes a state machine that controlsthe charging algorithm. Figure 4 shows the state dia-gram. Table 1 lists the charging state conditions. Whenpower is applied or SHDN is driven high, the part goes
into the reset state where the timers are reset to zero toprepare for charging. From the reset state, it enters theprequalification state. In this state, 1/20 of the fast-charge current charges the battery, and the batterytemperature and voltage are measured. If the voltage isabove the undervoltage threshold and the temperatureis within the limits, then it will enter the fast-chargestate. If the battery voltage does not rise above theundervoltage threshold before the prequalification timerexpires, the charging terminates and the FAULT outputgoes low. The prequalification time is set by theTIMER1 capacitor (CTIMER1). If the battery is outsidethe temperature limits, charging and the timer are sus-pended. Once the temperature is back within limits,charging and the timer resume.
In the fast-charge state, the FASTCHGoutput goes low,and the batteries charge with a constant current (seethe Charging Current Regulatorsection). If the batteryvoltage reaches the voltage limit before the fast timerexpires, the part enters the full-charge state. If the fast-charge timer expires before the voltage limit isreached, charging terminates with a fault indication.The fast-charge time limit is set by the TIMER2 capaci-
tor (CTIMER2). If the battery temperature is outside thelimits, charging pauses and the timers are suspended
until the temperature returns to within the limits.
In the full-charge state, the FULLCHG output goes lowand the batteries charge at a constant voltage (see theVoltage Regulatorsection). When the charging currentdrops below 10% of the charging current limit, or if thefull-charge timer expires, the state machine enters thetop-off state. In the top-off state, the batteries continueto charge at a constant voltage until the top-off timerexpires, at which time it enters the done state. In thedone state, charging stops until the battery voltagedrops below the recharge-voltage threshold. It thenenters the reset state to start the charging processagain. In the full-charge or the top-off state, if the bat-tery temperature is outside the limits, charging pausesand the timers are suspended until the battery temper-ature returns to within limits.
Voltage RegulatorLi+ batteries require a high-accuracy voltage limit whilecharging. The MAX1737 uses a high-accuracy voltageregulator (0.8%) to limit the charging voltage. The bat-tery regulation voltage is nominally set to 4.2V per celland can be adjusted 5% by setting the voltage at theVADJ pin between reference voltage and ground. Bylimiting the adjust range of the regulation voltage, anoverall voltage accuracy of better than 1% is main-tained while using 1% resistors. CELL sets the cellcount from one to four series cells (see Setting the
Battery Regulation Voltagesection).An internal error amplifier (GMV) maintains voltage reg-ulation (Figure 3). The GMV amplifier is compensatedat CCV. The component values shown in Figure 1 pro-vide suitable performance for most applications.Individual compensation of the voltage regulation andcurrent regulation loops allows for optimal compensa-tion of each.
Charging Current RegulatorThe charging current-limit regulator limits the chargingcurrent. The current is sensed by measuring the volt-age across the current-sense resistor (R18, Figure 1)placed between the BATT and CS pins. The voltage on
the ISETOUT pin also controls the charging current.Full-scale charging current is achieved by connectingISETOUT to REF. In this case, the full-scale current-sense voltage is 200mV from CS to BATT.
When choosing the charging current-sense resistor,note that the voltage drop across this resistor causesfurther power loss, reducing efficiency. However,adjusting ISETOUT to reduce the voltage across the
FAST-CHARGESTATE
OPEN-DRAINLOW
OPEN-DRAINLOW
BATTERYCURRENT
BATTERYVOLTAGE
FASTCHGOUTPUT
FULLCHGOUTPUT
FULL-CHARGESTATE
TOP-OFFSTATE DONE
CHARGE I = 1C
BATTERYINSERTION
OR SHDN HIGH
TRANSITION TOVOLTAGE MODE
(APPROX 85% CHARGE)
FULL-CHARGE TIMERTIMES OUT OR
BATTERY CURRENTDROPS TO C/10
(APPROX 95% CHARGE)
TOP-OFF TIMERTIMES OUT, END OF ALL
CHARGE FUNCTIONS
Figure 2. Charge State and Indicator Output Timing for aTypical Charging Sequence
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current-sense resistor may degrade accuracy due tothe input offset of the current-sense amplifier.
The charging-current error amplifier (GMI) is compen-sated at CCI. A 47nF capacitor at CCI provides suit-able performance for most applications.
Input Current RegulatorThe total input current (from a wall cube or other DCsource) is the sum of system supply current plus thebattery-charging current. The input current regulatorlimits the source current by reducing charging currentwhen input current exceeds the set input current limit.System current normally fluctuates as portions of thesystem are powered up or put to sleep. Without input
PWMCOMP
ON
BST
CCI
DHI
LX
DLO
VLO
PGND
CCV
CCS
LO
PWMCMP
ILIMIT
LOWILIM
OSC
160ns
160ns
PWMOSC
REF/42
REF/2
REF/2.6
CCI GND
CCS
LVC
GMS
GND
GND
R
GND
RR/9
3R
DHI
DLO
GATECONTROL
CCV
SW+
SW-
CS+
CS-
EA+
EA-
GMI
10xCSS
GMV
GND
GND
R
R
R/2R/2R/2R
R
9R
CELLCELL
REF
VADJ
3R
ISETOUT
ISETIN
REF/42
STOP
SLOPECOMP
BATTSAW
PREQ
BATT
SHDN
CS
CSSN
CSSP
ONE
TWO
THREE
FOUR
5xCSI
MAX1737
Figure 3. PWM Controller Block Diagram
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current regulation, the input source must be able tosupply the maximum system current plus the maximumcharger input current. By using the input current limiter,the current capability of the AC wall adapter may belowered, reducing system cost.
Input current is measured through an external senseresistor at CSSP and CSSN. The voltage at ISETIN alsoadjusts the input current limit. Full-scale input current isachieved when ISETIN is connected to REF, setting thefull-scale current-sense voltage to 100mV.
When choosing the input current-sense resistor, notethat the voltage drop across this resistor adds to thepower loss, reducing efficiency. Reducing the voltage
across the current-sense resistor may degrade inputcurrent limit accuracy due to the input offset of theinput current-sense amplifier.
The input current error amplifier (GMS) is compensated
at CCS. A 47nF capacitor at CCS provides suitable per-formance for most applications.
PWM ControllerThe PWM controller drives the external MOSFETs tocontrol the charging current or voltage. The input to thePWM controller is the lowest of CCI, CCV, or CCS. Aninternal clamp limits the noncontrolling signals to within200mV of the controlling signal to prevent delay whenswitching between regulation loops.
SHUTDOWNFASTCHG = HIGH
FULLCHG = HIGH
FAULT = HIGH
RESETFASTCHG = HIGH
FULLCHG = HIGH
FAULT = HIGH
PREQUALFASTCHG = LOW
FULLCHG = HIGH
FAULT = HIGH
FAULTFASTCHG = HIGH
FULLCHG = HIGH
FAULT = LOW
FAST CHARGEFASTCHG = LOW
FULLCHG = HIGH
FAULT = HIGH
FULL CHARGEFASTCHG = HIGH
FULLCHG = LOW
FAULT = HIGH
DONEFASTCHG = HIGH
FULLCHG = HIGH
FAULT = HIGH
TOP-OFFFASTCHG = HIGH
FULLCHG = HIGH
FAULT = HIGH
TEMPOK
TEMPOK
TEMPOK
TEMP
OK
TEMPNOT OK
TOP-OFFTIMEOUT
ICHARGE < IMIN ORFULL-CHARGE
TIMEOUT
ONCE PERSECOND
ONCE PERSECOND
TEMPQUAL
VBATT > 2.5V
VBATT < 0.95 VBATTR
VBATT < 0.95 VBATTR
VDCIN < BATT
VBATT < UNDERVOLTAGETHRESHOLD
VBATT = BATTERYREGULATION VOLTAGE (VBATTR)
FAST-CHARGETIMEOUT
PREQUALTIMEOUT
TEMPNOT OK
TEMPNOT OK
SHUTDOWN ISENTERED FROM ALL STATES
WHEN SHDN IS LOW.
SHDN HIGH
VDCIN > VBATT
Figure 4. State Diagram
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Table 1. Charging State Conditions
From initial power on
orFrom done state if battery voltage bat-
tery overvoltage threshold
Timers reset, charging current = 0,
FASTCHG= high,FULLCHG= high,FAULT= high
Reset
Fault
From prequalification state if prequalifi-
cation timer expires
or
From fast-charge state if fast-charge
timer expires
Charging current = 0,
FASTCHG= high,FULLCHG= high,FAULT= low
Over/Under Temperature
From fast-charge state or full-charge
state if battery temperature is outside of
limits
Charge current = 0, timers suspended,
FASTCHG= no change, FULLCHG= no change,FAULT= no change
Done From top-off state if top-off timer expires
Recharge voltage threshold battery voltage batteryregulation voltage, charging current = 0, FASTCHG=high,FULLCHG= high, FAULT= high
Top-Off
(Constant Voltage)
From full-charge state if full-charge timer
expires or charging current 10% ofcurrent limit
Battery voltage = battery regulation voltage, charging
current 10% of current limit, timeout = 45min typ(CTIMER1 = 1nF),FASTCHG= high, FULLCHG= high,
FAULT= high
Full Charge
(Constant Voltage)
From fast-charge state if battery
voltage = battery regulation voltage
Battery voltage = battery regulation voltage, charging
current current limit,timeout = 90min typ (CTIMER1 = 1nF),
FASTCHG= high,FULLCHG= low,FAULT= high
ENTRY CONDITIONS STATE CONDITIONS
Prequalification
From reset state if input power,
reference, and internal bias are within
limits
Battery voltage undervoltage threshold, chargingcurrent = C/20, timeout = 7.5min typ (CTIMER1 = 1nF),
FASTCHG= low, FULLCHG= high,FAULT= high
Fast Charge
(Constant Current)
From prequalification state if battery
voltage > undervoltage threshold
Undervoltage threshold battery voltage battery regu-lation voltage, charging current = current limit,
timeout = 90min typ (CTIMER2 = 1nF),
FASTCHG= low, FULLCHG= high,FAULT= high
STATE
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The current-mode PWM controller uses the inductorcurrent to regulate the output voltage or current, simpli-
fying stabilization of the regulation loops. Separatecompensation of the regulation circuits allows each tobe optimally stabilized. Internal slope compensation isincluded, ensuring stable operation over a wide rangeof duty cycles.
The controller drives an external N-channel MOSFETswitch and a synchronous rectifier to step the inputvoltage down to the battery voltage. A bootstrapcapacitor drives the high-side MOSFET gate to a volt-age higher than the input source voltage. This capaci-tor (between BST and LX) is charged through a diodefrom VLO when the synchronous rectifier is on. Thehigh-side MOSFET gate is driven from BST, supplyingsufficient voltage to fully drive the MOSFET gate evenwhen its source is near the input voltage. The synchro-nous rectifier is driven from DLO to behave like a diode,but with a smaller voltage drop for improved efficiency.
A built-in dead time (50ns typ) between switch and syn-chronous rectifier turn-on and turn-off prevents crowbarcurrents (currents that flow from the input voltage toground due to both the MOSFET switch and synchro-nous rectifier being on simultaneously). This dead timemay allow the body diode of the synchronous rectifierto conduct. If this happens, the resulting forward volt-age and diode recovery time will cause a small loss ofefficiency and increased power dissipation in the syn-chronous rectifier. To prevent the body diode from con-
ducting, place an optional Schottky rectifier in parallelwith the drain and source of the synchronous rectifier.The internal current-sense circuit turns off the synchro-nous rectifier when the inductor current drops to zero.
TimersThe MAX1737 includes safety timers to terminatecharging and to ensure that faulty batteries are notcharged indefinitely. TIMER1 and TIMER2 set the time-out periods.
TIMER1 controls the maximum prequalification time,maximum full-charge time, and the top-off time. TIMER2controls the maximum fast-charge time. The timers areset by external capacitors. The typical times of 7.5 min-utes for prequalification, 90 minutes for full charge, 45minutes for top-off, and 90 minutes for fast charge areset by using a 1nF capacitor on TIMER1 and TIMER2(Figure 1). The timers cannot be disabled.
Charge Monitoring Outputs
FASTCHG, FULLCHG, and FAULT are open-drain out-puts that can be used as LED drivers. FASTCHG indi-cates the battery is being fast charged. FULLCHGindicates the charger has completed the fast-charge
cycle (approximately 85% charge) and is operating involtage mode. The FASTCHG and FULLCHG outputs
can be tied together to indicate charging (see Figure 2).FAULT indicates the charger has detected a chargingfault and that charging has terminated. The charger canbe brought out of the FAULT condition by removing andreapplying the input power, or by pulling SHDNlow.
ThermistorThe intent of THM is to inhibit fast-charging the cellwhen it is too cold or too hot (+2.5C TOK +47.5C),using an external thermistor. THM time multiplexes twosense currents to test for both hot and cold qualification.The thermistor should be 10k at +25C and have anegative temperature coefficient (NTC); the THM pinexpects 3.97k at +47.5C and 28.7k at +2.5C.
Connect the thermistor between THM and GND. If notemperature qualification is desired, replace the ther-mistor with a 10k resistor. Thermistors byPhilips/BCcomponents (2322-640-63103), CornerstoneSensors (T101D103-CA), and Fenwal Electronics (140-103LAG-RB1) work well.
ShutdownWhen SHDN is pulled low, the MAX1737 enters theshutdown mode and charging is stopped. In shutdown,the internal resistive voltage-divider is removed fromBATT to reduce the current drain on the battery to lessthan 1A. DHI and DLO are low. However, the internallinear regulator (VLO) and the reference (REF) remainon. The status outputs FASTCHG, FULLCHG, and
FAULT are high impedance. When exiting shutdownmode, the MAX1737 goes back to the power-on resetstate, which resets the timers and begins a new chargecycle.
Source Undervoltage Shutdown(Dropout)
If the voltage on DCIN drops within 100mV of the volt-age on BATT, the charger resets.
Table 2. Cell-Count Programming
4VL
3REF
2
1GND
CELL COUNT (N)CELL
Float
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Design Procedure
Setting the Battery Regulation VoltageVADJ sets the per-cell voltage limit. To set the VADJvoltage, use a resistor-divider from REF to GND. AGND-to-VREF change at VADJ results in a 5% changein the battery limit voltage. Since the full VADJ rangeresults in only a 10% change on the battery regulationvoltage, the resistor-dividers accuracy need not be ashigh as the output voltage accuracy. Using 1% resis-tors for the voltage-dividers results in no more than0.1% degradation in output voltage accuracy. VADJ isinternally buffered so that high-value resistors can beused. Set VVADJ by choosing a value less than 100kfor R8 and R9 (Figure 1) from VADJ to GND. The per-cell battery termination voltage is a function of the bat-
tery chemistry and construction; thus, consult thebattery manufacturer to determine this voltage. Oncethe per-cell voltage limit battery regulation voltage isdetermined, the VADJ voltage is calculated by theequation:
where VBATTR is N x the cell voltage. CELL is the pro-gramming input for selecting cell count N. Table 2shows how CELL is connected to charge one to fourcells.
Setting the Charging Current Limit
A resistor-divider from REF to GND sets the voltage atISETOUT (VISETOUT). This voltage determines thecharging current during the current-regulation fast-charge mode. The full-scale charging current (IFSI) isset by the current-sense resistor (R18, Figure 1)between CS and BATT. The full-scale current is IFSI =0.2V / R18.
The charging current ICHG is therefore:
In choosing the current-sense resistor, note that the dropacross this resistor causes further power loss, reducing
efficiency. However, too low a value may degrade theaccuracy of the charging current.
Setting the Input Current LimitA resistor-divider from REF to GND can set the voltageat ISETIN (VISETIN). This sets the maximum source cur-rent allowed at any time during charging. The sourcecurrent (IFSS) is set by the current-sense resistor (R12,
Figure 1) between CSSP and CSSN. The full-scalesource current is IFSS = 0.1V / R12.
The input current limit (IIN) is therefore:
Set ISETIN to REF to get the full-scale current limit.Short CSSP and CSSN to DCIN if the input source cur-rent limit is not used.
In choosing the current-sense resistor, note that thedrop across this resistor causes further power loss,reducing efficiency. However, too low a resistor valuemay degrade input current limit accuracy.
Inductor Selection
The inductor value may be changed to achieve more orless ripple current. The higher the inductance, thelower the ripple current will be; however, as the physi-cal size is kept the same, higher inductance typicallywill result in higher series resistance and lower satura-tion current. A good trade-off is to choose the inductorso that the ripple current is approximately 30% to 50%of the DC average charging current. The ratio of ripplecurrent to DC charging current (LIR) can be used tocalculate the optimal inductor value:
where f is the switching frequency (300kHz).The peak inductor current is given by:
Capacitor SelectionThe input capacitor absorbs the switching current fromthe charger input and prevents that current from circu-lating through the source, typically an AC wall cube.Thus, the input capacitor must be able to handle theinput RMS current. Typically, at high charging currents,the converter will operate in continuous conduction (theinductor current does not go to 0). In this case, the
RMS current of the input capacitor may be approximat-ed by the equation:
where ICIN = the input capacitor RMS current, D =PWM converter duty ratio (typically VBATT/ VDCIN), andICHG = battery charging current.
I ICIN CHG D D2
I ILIR
PEAK CHG= +
12
LV V V
V f I LIR
BATT DCIN MAX BATT
DCIN MAX CHG=
( )( )
( )
I IV
VIN FSS
ISETIN
REF=
I IV
VCHG FSI
ISETOUT
REF =
V9.5 V
N(9.0 V )ADJ
BATTRREF=
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The maximum RMS input current occurs at 50%duty cycle, so the worst-case input ripple current is
0.5 ICHG. If the input to output voltage ratio is suchthat the PWM controller will never work at 50% dutycycle, then the worst-case capacitor current will occurwhere the duty cycle is nearest 50%.
The impedance of the input capacitor is critical to pre-venting AC currents from flowing back into the wall cube.This requirement varies depending on the wall cubesimpedance and the requirements of any conducted orradiated EMI specifications that must be met. Aluminumelectrolytic capacitors are generally the least costly, butare usually a poor choice for portable devices due totheir large size and low equivalent series resistance(ESR). Tantalum capacitors are better in most cases, asare high-value ceramic capacitors. For equivalent sizeand voltage rating, tantalum capacitors will have highercapacitance and ESR than ceramic capacitors. Thismakes it more critical to consider RMS current andpower dissipation when using tantalum capacitors.
The output filter capacitor is used to absorb the induc-tor ripple current. The output capacitor impedancemust be significantly less than that of the battery toensure that it will absorb the ripple current. Both thecapacitance and ESR rating of the capacitor are impor-tant for its effectiveness as a filter and to ensure stabili-ty of the PWM circuit. The minimum output capacitancefor stability is:
where COUT is the total output capacitance, VREF is thereference voltage (4.2V), VBATT is the maximum batteryvoltage (typically 4.2V per cell), and VDCIN(MIN) is theminimum source input voltage.
The maximum output capacitor ESR allowed for stabilityis:
where RESR is the output capacitor ESR and RCS is thecurrent-sense resistor from CS to BATT.
Setting the TimersThe MAX1737 contains four timers: a prequalificationtimer, fast-charge timer, full-charge timer, and top-offtimer. Connecting a capacitor from TIMER1 to GNDand TIMER2 to GND sets the timer periods. TheTIMER1 input controls the prequalification, full-charge,and top-off times, while TIMER2 controls fast-charge
timeout. The typical timeouts for a 1C charge rate areset to 7.5 minutes for the prequalification timer, 90 min-
utes for the fast-charge timer, 90 minutes for the full-charge timer, and 45 minutes for the top-off timer byconnecting a 1nF capacitor to TIMER1 and TIMER2.Each timer period is directly proportional to the capaci-tance at the corresponding pin. See the TypicalOperating Characteristics.
CompensationEach of the three regulation loopsthe input currentlimit, the charging current limit, and the charging volt-age limitcan be compensated separately using theCCS, CCI, and CCV pins, respectively.
The charge-current loop error amp output is broughtout at CCI. Likewise, the source-current error amplifier
output is brought out at CCS; 47nF capacitors toground at CCI and CCS compensate the current loopsin most charger designs. Raising the value of thesecapacitors reduces the bandwidth of these loops.
The voltage-regulating loop error amp output is broughtout at CCV. Compensate this loop by connecting acapacitor in parallel with a series resistor-capacitor(RC) from CCV to GND. Recommended values areshown in Figure 1.
Applications Information
MOSFET SelectionThe MAX1737 uses a dual N-channel external power
MOSFET switch to convert the input voltage to thecharging current or voltage. The MOSFET must beselected to meet the efficiency and power-dissipationrequirements of the charging circuit, as well as the tem-perature rise of the MOSFETs. The MOSFET character-istics that affect the power dissipation are thedrain-source on-resistance (RDS(ON)) and the gatecharge. In general, these are inversely proportional.
To determine the MOSFET power dissipation, the oper-ating duty cycle must first be calculated. When thecharger is operating at higher currents, the inductorcurrent will be continuous (the inductor current will notdrop to 0A) and, in this case, the high-side MOSFETduty cycle (D) can be approximated by the equation:
and the synchronous-rectifier MOSFET duty cycle (D)will be 1 - D or:
DV V
V
DCIN BATT
DCIN
DV
V
BATT
DCIN
RR V
VESR
CS BATT
REF
+
1( )
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For the high-side switch, the worst-case power dissipa-tion due to on-resistance occurs at the minimum source
voltage VDCIN(MIN) and the maximum battery voltageVBATT(MAX), and can be approximated by the equation:
The transition loss can be approximated by the equation:
where tTR is the MOSFET transition time. So the totalpower dissipation of the high-side switch is PTOT = PR+ PT.
The worst-case synchronous-rectifier power occurs atthe minimum battery voltage VBATT(MIN) and the maxi-mum source voltage VDC(MAX), and can be approxi-mated by:
There is a brief dead time where both the high-sideswitch and synchronous rectifier are off. This preventscrowbar currents that flow directly from the source volt-age to ground. During the dead time, the inductor cur-rent will turn on the synchronous-rectifier MOSFET body
diode, which may degrade efficiency. To prevent this,
connect a Schottky rectifier across the drain source ofthe synchronous rectifier to stop the body diode from
conducting. The Schottky rectifier may be omitted, typi-cally degrading the efficiency by approximately 1% to2%, causing a corresponding increase in the low-sidesynchronous-rectifier power dissipation.
VL and REF BypassingThe MAX1737 uses an internal linear regulator to dropthe input voltage down to 5.4V, which powers the inter-nal circuitry. The output of the linear regulator is the VLpin. The internal linear regulator may also be used topower external circuitry as long as the maximum currentand power dissipation of the linear regulator are notexceeded. The synchronous-rectifier MOSFET gate dri-ver (DLO) is powered from VLO. An internal 12 resistor
from VL to VLO provides the DC current to power thegate driver. Bypass VLO to PGND with a 0.1F orgreater capacitor.
A 4.7F bypass capacitor is required at VL to ensurethat the regulator is stable. A 1F bypass capacitor isalso required between REF and GND to ensure that theinternal 4.2V reference is stable. In both cases use alow-ESR ceramic capacitor.
Chip Information
TRANSISTOR COUNT: 5978
PV V
VR IDL
DCIN MAX BATT MIN
DCIN MAXDS ON CHG
( ) ( )
( )( ) 2
PV I f t
TDCIN CHG TR
3
PV
VR IR
BATT MAX
DCIN MINDS ON CHG
( )
( )( ) 2
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QSOP.E
PS
F1
121-0055
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
Note:The MAX1737EEI is a 28-pin QSOP and does not have a heat slug.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 18
2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Revision HistoryPages changed at Rev 4: 1, 9, 18
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(6,4 mm x 7,8 mm)
www.ti.com
F E A T U R E S D E S C R I P T I O N
A P P L I C A T I O N S
GA
GB
GC
GD
SA
PGND
SC
V5A
V5C
V5
CA
CSEN
VA
OCP
PH
SET
EN
VCC
VREF
GND
STC
ABR
BF
FAULT
VSEN
BBR
BC
C1Q
A
TPS68000
2 V
3.3 V
R1
C5
C7
VLOGIC
Supply Voltage
8V .. 30V
Error Output
Operating Frequency
Device Enable
Lamp current(Analog Dimming Input)
Burst Duty Cycle(Burst Dimming Input)
Direct Burst Dimming Input(Frequency + Duty Cycle)
C10
C3
C4
C2
C12
C13
R4R
3
C8
C9
SYNC
R2
2.0 V0 V
CAO
VAO
C14
QC
QB
QD
T1
C6
0 V
0 V
Burst Frequency
Synchronization
SynchronizationPhase Shift
T P S 6 8 0 0 0
S L V S 5 2 4 A O C T O B E R 2 0 0 5 R E V I S E D F E B R U A R Y 2 0 0 6
H I G H L Y E F F I C I E N T P H A S E S H I F T F U L L B R I D G E C C F L C O N T R O L L E R
8 - V t o 3 0 - V I n p u t V o l t a g e R a n g e T h e T P S 6 8 0 0 0 d e v i c e p r o v i d e s a p o w e r s u p p l y c o n t r o l l e r s o l u t i o n f o r C C F L b a c k l i g h t a p p l i c a t i o n s i n a F u l l B r i d g e T o p o l o g y W i t h I n t e g r a t e d G a t e l a r g e v a r i e t y o f a p p l i c a t i o n s . T h e w i d e i n p u t v o l t a g e D r i v e s f o r 4 N M O S S w i t c h e s r a n g e o f 8 V t o 3 0 V m a k e s i t s u i t a b l e t o b e p o w e r e d
S y n c h r o n i z a b l e C o n s t a n t F r e q u e n c y d i r e c t l y f r o m r e g u l a t e d 1 2 - V o r 2 4 - V r a i l s , o r a n y
O p e r a t i o n o t h e r s o u r c e w i t h o u t p u t v o l t a g e s i n t h i s r a n g e . W h e n
P r o g r a m m a b l e P h a s e D e l a y s o f O p e r a t i n g u s i n g a 1 0 % a c c u r a t e r e g u l a t e d 5 - V r a i l , i t a l s o c a n F r e q u e n c y f o r M a s t e r - S l a v e O p e r a t i o n b e u s e d i n n o t e b o o k c o m p u t e r s o r o t h e r p o r t a b l e
b a t t e r y - p o w e r e d e q u i p m e n t h a v i n g l o w e r m i n i m u m L a m p V o l t a g e a n d L a m p C u r r e n t R e g u l a t i o n s u p p l y v o l t a g e s . T h e c o n t r o l l e r i s c a p a b l e o f d r i v i n g
A n a l o g a n d B u r s t D i m m i n g t h e g a t e s o f a l l 4 N M O S s w i t c h e s d i r e c t l y w i t h o u t t h e C o n f i g u r a b l e D i s t r i b u t e d B u r s t D i m m i n g i n n e e d f o r a n y a d d i t i o n a l c i r c u i t r y , l i k e d e d i c a t e d g a t e
M u l t i p l e C o n t r o l l e r A p p l i c a t i o n s d r i v e r s o r g a t e - d r i v e t r a n s f o r m e r s . T h e w i d e i n p u t v o l t a g e r a n g e a l s o m a k e s i t e a s y t o d e s i g n C C F L
P r o g r a m m a b l e V o l t a g e R e g u l a t i o n T i m e o u t c o n v e r t e r s w i t h h i g h e r i n p u t v o l t a g e s l i k e 1 2 0 V o r f o r S t a r t u p a n d F a u l t C o n d i t i o n s 4 0 0 V a v a i l a b l e a t t h e o u t p u t o f a p o w e r f a c t o r
O p e n - L a m p a n d S h o r t - C i r c u i t P r o t e c t i o n c o r r e c t i o n u n i t . T h e T P S 6 8 0 0 0 a l s o s u p p o r t s C C F L I n t e r n a l O v e r - T e m p e r a t u r e P r o t e c t i o n c o n v e r t e r c i r c u i t s d r i v i n g m u l t i - l a m p a p p l i c a t i o n s ,
e i t h e r b y u s i n g h i g h e r p o w e r - r a t e d s w i t c h e s a n d U n d e r v o l t a g e L o c k o u t t r a n s f o r m e r s , o r u s i n g s e v e r a l T P S 6 8 0 0 0 s
3 0 - p i n T S S O P P a c k a g e s y n c h r o n i z e d . W h e n s y n c h r o n i z e d , t h e y c a n b e o p e r a t e d e i t h e r a t t h e s a m e f r e q u e n c y a n d p h a s e , o r p h a s e s h i f t e d t o m i n i m i z e R M S i n p u t c u r r e n t . A l r e a d y i m p l e m e n t e d s m a r t d i m m i n g f e a t u r e s , s u c h a s C C F L B a c k l i g h t P o w e r S u p p l i e s f o r D e s k t o p s u p p o r t o f d i s t r i b u t e d d i m m i n g , a l s o h e l p t o o p t i m i z e M o n i t o r s a n d L C D T V s t h e p e r f o r m a n c e o f m u l t i - c o n t r o l l e r a p p l i c a t i o n s . C C F L B a c k l i g h t P o w e r S u p p l i e s f o r N o t e b o o k ( C o n t i n u e d o n n e x t p a g e ) C o m p u t e r s
P l e a s e b e a w a r e t h a t a n i m p o r t a n t n o t i c e c o n c e r n i n g a v a i l a b i l i t y , s t a n d a r d w a r r a n t y , a n d u s e i n c r i t i c a l a p p l i c a t i o n s o f T e x a s I n s t r u m e n t s s e m i c o n d u c t o r p r o d u c t s a n d d i s c l a i m e r s t h e r e t o a p p e a r s a t t h e e n d o f t h i s d a t a s h e e t .
D i s t r i b u t e d D i m m i n g i s a r e g i s t e r e d t r a d e m a r k o f T e x a s I n s t r u m e n t s .
P R O D U C T I O N D A T A i n f o r m a t i o n i s c u r r e n t a s o f p u b l i c a t i o n d a t e . C o p y r i g h t 2 0 0 5 2 0 0 6 , T e x a s I n s t r u m e n t s I n c o r p o r a t e d P r o d u c t s c o n f o r m t o s p e c i f i c a t i o n s p e r t h e t e r m s o f t h e T e x a s I n s t r u m e n t s s t a n d a r d w a r r a n t y . P r o d u c t i o n p r o c e s s i n g d o e s n o t
n e c e s s a r i ly i n c l u d e t e s t i n g o f a l l p a r a m e t e r s .
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E L E C T R I C A L C H A R A C T E R I S T I C S
T P S 6 8 0 0 0
S L V S 5 2 4 A O C T O B E R 2 0 0 5 R E V I S E D F E B R U A R Y 2 0 0 6
o v e r r e c o m m e n d e d f r e e - a i r t e m p e r a t u r e r a n g e a n d o v e r r e c o m m e n d e d i n p u t v o l t a g e r a n g e ( t y p i c a l a t a n a m b i e n t t e m p e r a t u r e
r a n g e o f 2 5 C ) ( u n l e s s o t h e r w i s e n o t e d )
P A R A M E T E R T E S T C O N D I T I O N S M I N T Y P M A X U N I T
M A I N C O N T R O L
V5
I n t e r n a l c o n t r o l s u p p l y r e g u l a t o r I O U T - V 5
< 2 5 m A 4 . 5 5 5 . 5 V
i n c l u d i n g i n t e r n a l c u r r e n t IO U T - V 5 C o n t r o l s u p p l y o u t p u t c u r r e n t 2 5 m A c o n s u m p t i o n
VU V L O U n d e r v o l t a g e l o c k o u t t h r e s h o l d a t V 5 V o l t a g e a t V 5 d e c r e a s i n g 4 . 0 4 . 1 4 . 3 V
VO L F A U L T o u t p u t l o w v o l t a g e I F A U L T = 5 0 0 A 0 . 2 0 . 4 V
Vlk g F A U L T o u t p u t l e a k a g e c u r r e n t V F A U L T = 5 V 0 . 1 1 A
VI L E N i n p u t l o w v o l t a g e 0 . 4 V
VI H E N i n p u t h i g h v o l t a g e 1 . 4 V
E N i n p u t c u r r e n t V C C = 2 4 V 0 . 0 5 0 . 1 A
IS T C S T C s o u r c e c u r r e n t d u r i n g s t r i k e 6 A
IS T C S T C s o u r c e c u r r e n t d u r i n g w a i t 2 A
n o r m a l o p e r a t i o n , V S T C =IS T C S T C s o u r c e a n d s i n k c u r r e n t 1 0 A 1 . 2 5 V
O v e r t e m p e r a t u r e p r o t e c t i o n 1 4 0 C
O v e r t e m p e r a t u r e h y s t e r e s i s 2 0 C
Q u i e s c e n t c u r r e n t i n t o V C C V C C = 1 2 V , V 5 = 5 . 5 V 3 0 5 0 A
Q u i e s c e n t c u r r e n t i n t o V C C V C C = V 5 = 5 . 5 V 2 5 4 0 A
Q u i e s c e n t c u r r e n t i n t o V 5 V C C = V 5 = 5 . 5 V 1 0 0 0 1 5 0 0 A
S h u t d o w n c u r r e n t i n t o V C C V C C = V 5 = 5 . 5 V , E N = 0 V 1 2 A
S h u t d o w n c u r r e n t i n t o V 5 V C C = V 5 = 5 . 5 V , E N = 0 V 1 2 A
S h u t d o w n c u r r e n t i n t o V C C V C C = 1 2 V , E N = 0 V 2 . 5 5 A
VR E F R e f e r e n c e V o l t a g e I O U T - V R E F < 5 m A 3 . 2 7 3 . 3 3 . 3 3 V
IO U T - V R E F R e f e r e n c e o u t p u t c u r r e n t 5 m A
G A T E D R I V E
H i g h s i d e d r i v e s i n k r e s i s t a n c e I D = 0 . 0 5 A 1 . 2 2 . 0 H i g h s i d e d r i v e s o u r c e r e s i s t a n c e I D = 0 . 0 5 A 1 . 5 2 . 5
H i g h s i d e d r i v e r i s e t i m e C G = 4 . 7 n F , S A = SC = 0 V , 3 5 5 0 n s V5 A = V5 C = 5 V
H i g h s i d e d r i v e f a l l t i m e C G = 4 . 7 n F 1 5 2 5 n s
T i m e d e l a y b e t w e e n h i g h s i d e o f f a n d C G = 4 . 7 n F 1 0 0 n s l o w s i d e o n
T i m e d e l a y b e t w e e n l o w s i d e o f f a n d C G = 4 . 7 n F 1 0 0 n s h i g h s i d e o n
L o w s i d e d r i v e s i n k r e s i s t a n c e I D = 0 . 0 5 A 1 . 2 2 . 0
L o w s i d e d r i v e s o u r c e r e s i s t a n c e I D = 0 . 0 5 A 1 . 5 2 . 5
L o w s i d e d r i v e r i s e t i m e C G = 4 . 7 n F , V 5 = 5 V 3 5 5 0 n s
L o w s i d e d r i v e f a l l t i m e C G = 4 . 7 n F 1 5 2 5 n s
M A I N O S C I L L A T O R
O s c i l l a t o r f r e q u e n c y p r o g r a m m i n g f 3 0 1 0 0 k H z
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VI L S Y N C l o w v o l t a g e 0 . 4 V
VI H S Y N C h i g h v o l t a g e 1 . 4 V
VP H V5 - 1 . 3 V , V S Y N C = 3 . 3 IS Y N C S Y N C i n p u t c u r r e n t 0 . 5 1 . 5 A V
IS Y N C S Y N C d r i v e c u r r e n t V S Y N C 1 . 4 V , V P H = 5 V 1 0 0 0 1 2 5 0 1 5 0 0 A
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T P S 6 8 0 0 0
S L V S 5 2 4 A O C T O B E R 2 0 0 5 R E V I S E D F E B R U A R Y 2 0 0 6
E L E C T R I C A L C H A R A C T E R I S T I C S ( c o n t i n u e d )
o v e r r e c o m m e n d e d f r e e - a i r t e m p e r a t u r e r a n g e a n d o v e r r e c o m m e n d e d i n p u t v o l t a g e r a n g e ( t y p i c a l a t a n a m b i e n t t e m p e r a t u r e r a n g e o f 2 5 C ) ( u n l e s s o t h e r w i s e n o t e d )
P A R A M E T E R T E S T C O N D I T I O N S M I N T Y P M A X U N I T
IS Y N C S Y N C s i n k c u r r e n t V S Y N C 0 . 4 V , V P H = 5 V 1 0 0 0 1 2 5 0 1 5 0 0 A
M i n i m u m p u l s e w i d t h f o r 1 0 0 n s s y n c h r o n i z a t i o n
VS E T S E T o u t p u t v o l t a g e 1 . 2 5 V
P h a s e s h i f t o f t h e m a i n o s c i l l a t o r c l o c k V P H = 0 . 1 V . . 1 . 9 V 9 0 / VP H
IP H P H i n p u t c u r r e n t V P H = 2 . 0 V 0 . 1 1 A
T h r e s h o l d f o r p r o g r a m m i n g d e v i c e a s VP H V5 1 . 3 V V 5 0 . 7 V V m a i n o s c i l l a t o r f r e q u e n c y m a s t e r
V O L T A G E A N D C U R R E N T C O N T R O L
RC S E N C u r r e n t s e n s e i n p u t i m p e d a n c e V C S E N = 3 . 3 V 3 5 k
RC S E N C u r r e n t s e n s e i n p u t i m p e d a n c e V C S E N = 3 . 3 V 2 5 k
RV S E N V o l t a g e s e n s e i n p u t i m p e d a n c e V V S E N = 3 . 3 V 2 5 k
RV S E N V o l t a g e s e n s e i n p u t i m p e d a n c e V V S E N = 3 . 3 V 3 0 k
V o l t a g e a n d c u r r e n t a m p l i f i e r o u t p u t IC A O, IV A O VC A O, VV A O = 2 . 5 V 5 5 A s o u r c e c u r r e n t
V o l t a g e a n d c u r r e n t a m p l i f i e r o u t p u t IC A O, IV A O VC A O, VV A O = 2 . 5 V 2 0 0 A s i n k c u r r e n t
V R E F V R E G V o l t a g e r e g u l a t o r r e f e r e n c e v o l t a g e ( 0 . 8 VR E F) / V
V R E F O V P O v e r v o l t a g e c o m p a r a t o r t h r e s h o l d VR E F V
V R E F C R E G C u r r e n t r e g u l a t o r r e f e r e n c e v o l t a g e V A B R / V
IO C P O v e r c u r r e n t c o m p a r a t o r i n p u t c u r r e n t V O C P = 3 . 3 V 0 . 1 1 A
IO C P O v e r c u r r e n t c o m p a r a t o r i n p u t c u r r e n t V O C P = 3 . 3 V 5 0 A
V R E F O C P O v e r c u r r e n t c o m p a r a t o r t h r e s h o l d V R E F V
D I M M I N G
IA B R A B R i n p u t c u r r e n t V A B R = 3 . 3 V 0 . 0 1 0 . 1 A
A B R i n p u t v o l t a g e r a n g e f o r l a m p V
A B RB C = V
50 3 . 3 V
c u r r e n t p r o g r a m m i n g
IB B R B B R i n p u t c u r r e n t V B B R = 2 . 0 V 0 . 1 1 A
B u r s t d u t y c y c l e V B B R = 0 V . . 2 V 5 0 % / V B B R
B B R i n p u t v o l t a g e t h r e s h o l d f o r VB B R V5 1 . 3 V V 5 0 . 7 V V s e l e c t i n g s y n c h r o n i z e d b u r s t d i m m i n g
IB F B F s o u r c e c u r r e n t 1 0 A
fB u r s t I n t e r n a l b u r s t f r e q u e n c y r a n g e 2 0 1 0 0 0 H z
F r e q u e n c y l o c k / c a p t u r e r a n g e f o r 0 . 5 x fB C 1 . 5 x f B u r s t s y n c h r o n i z e d b u r s t d i m m i n g f B u r s t
tr B u r s t c u r r e n t p u l s e r i s e t i m e 4 0 0 s
IB C B C i n p u t c u r r e n t V B C = 3 . 3 V 0 . 1 1 A
VI L B C i n p u t l o w v o l t a g e 0 . 4 V
VI H B C i n p u t h i g h v o l t a g e 1 . 4 V m i n i m u m p u l s e w i d t h a t B C 1 0 0 n s
P h a s e s h i f t o f t h e d i m m i n g b u r s t V P H = 0 V . . 2 V , d i s t r i b u t e d 1 8 0 / VP Hc o m p a r e d t o B C c l o c k d i m m i n g s e l e c t e d
4 S u b m i t D o c u m e n t a t i o n F e e d b a c k
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P I N A S S I G N M E N T S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SYNC
SET
STC
PH
BBR
BC
BF
ABR
VAO
VA
VSEN
CA
CAO
CSEN
OCP
VREF
GND
SA
GA
V5A
GB
VCC
V5
PGND
GD
V5C
GC
SC
EN
FAULT
T P S 6 8 0 0 0
S L V S 5 2 4 A O C T O B E R 2 0 0 5 R E V I S E D F E B R U A R Y 2 0 0 6
D B T P A C K A G E ( T O P V I E W )
T e r m i n a l F u n c t i o n s
T E R M I N A L I / O D E S C R I P T I O N
N A M E N O .
A B R 8 I A n a l o g b r i g h t n e s s p r o g r a m m i n g i n p u t . A D C v o l t a g e a p p l i e d a t t h a t p i n p r o g r a m s t h e l a m p c u r r e n t t h e c u r r e n t r e g u l a t o r r e g u l a t e s . 0 V m e a n s n o c u r r e n t a n d 3 . 3 V m e a n s m a x i m u m c u r r e n t .
B B R 5 I B u r s t b r i g h t n e s s p r o g r a m m i n g i n p u t . A D C v o l t a g e a p p l i e d a t t h a t p i n p r o g r a m s t h e d u t y c y c l e o f t h e b u r s t p u l s e s g e n e r a t e d t o d i m m t h e b r i g h t n e s s . 0 V m e a n s z e r o d u t y c y c l e a n d 2 V m e a n s m a x i m u m d u t y c y c l e . A p p l y i n g V 5 ( 5 V ) p r o g r a m s t h e d e v i c e t o o p e r a t e i n s y n c h r o n i z e d b u r s t d i m m i n g m o d e .
B C 6 I B u r s t c o n t r o l . A P W M s i g n a l a p p l i e d a t t h a t p i n i s d i r e c t l y u s e d f o r b u r s t d i m m i n g . F r e q u e n c y a n d d u t y c y c l e a r e u s e d d i r e c t l y . T h i s i n p u t h a s p r i o r i t y a g a i n s t t h e b u r s t f r e q u e n c y p r o g r a m m i n g w i t hB B R a n d B F
B F 7 I B u r s t f r e q u e n c y p r o g r a m m i n g . A c a p a c i t o r a t t h a t p i n p r o g r a m s t h e b u r s t f r e q u e n c y . C A - 1 2 I C u r r e n t a m p l i f i e r n e g a t i v e i n p u t . T h i s i n p u t i s u s e d t o c o n n e c t t h e c o m p e n s a t i o n c a p a c i t o r f o r
c o m p e n s a t i n g t h e c u r r e n t l o o p .
C A O 1 3 O C u r r e n t a m p l i f i e r o u t p u t . T h i s i s t h e o u t p u t f o r t h e c u r r e n t a m p l i f i e r . I t i s u s e d t o c o n n e c t t h e c o m p e n s a t i o n c a p a c i t o r f o r t h e c u r r e n t l o o p .
C S E N 1 4 I C u r r e n t s e n s e . M e a s u r i n g i n p u t f o r t h e l a m p c u r r e n t . T h e a p p l i e d v o l t a g e ( c o m i n g f r o m a s h u n t r e s i s t o r ) w i l l b e u s e d f o r l a m p c u r r e n t r e g u l a t i o n . S e n s e d A C v o l t a g e s c a n b e a p p l i e d d i r e c t l y . T h e y w i l l b e r e c t i f i e d i n t e r n a l l y .
E N 1 7 I E n a b l e i n p u t . L o g i c h i g h e n a b l e s t h e d e v i c e .
F A U L T 1 6 O E r r o r o u t p u t , a n y d e t e c t e d m a l f u n c t i o n i n g o f t h e a p p l i c a t i o n w i l l b e r e p o r t e d a s e r r o r o n t h i s p i n . E r r o r m e a n s t h e o u t p u t i s p u l l e d l o w . T h e o u t p u t i s o p e n d r a i n t o a l l o w c o n n e c t i n g m u l t i p l e e r r o r o u t p u t s o f s i m i l a r d e v i c e s t o g e t h e r .
G A 2 7 O G a t e d r i v e o u t p u t o f s w i t c h A
G B 2 5 O G a t e d r i v e o u t p u t o f s w i t c h B
G C 1 9 O G a t e d r i v e o u t p u t o f s w i t c h C
G D 2 1 O G a t e d r i v e o u t p u t o f s w i t c h D
G N D 2 9 A n a l o g g r o u n d p i n . R e f e r e n c e g r o u n d f o r a l l c o n t r o l s i g n a l s .
O C P 1 5 I O v e r c u r r e n t p r o t e c t i o n . T h i s i n p u t i s u s e d t o m o n i t o r a v o l t a g e d e r i v e d f r o m a c u r r e n t s e n s o r i n a n y p a r t o f t h e c o n v e r t e r . T h i s v o l t a g e i s c o m p a r e d t o a n i n t e r n a l r e f e r e n c e v o l t a g e . E x c e e d i n g t h e i n t e r n a l r e f e r e n c e v o l t a g e c a u s e s t h e d e v i c e l o g i c t o t u r n t h e d e v i c e o f f a n d r e p o r t a n e r r o r s i g n a l a t t h e f a u l t p i n .
P G N D 2 2 R e f e r e n c e g r o u n d f o r t h e g a t e d r i v e r s a n d t h e g a t e d r i v e s u p p l y .
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T P S 6 8 0 0 0
S L V S 5 2 4 A O C T O B E R 2 0 0 5 R E V I S E D F E B R U A R Y 2 0 0 6
P I N A S S I G N M E N T S ( c o n t i n u e d )
T e r m i n a l F u n c t i o n s ( c o n t i n u e d )
T E R M I N A L I / O D E S C R I P T I O N
N A M E N O .
P H 4 I P h a s e d e l a y p r o g r a m m i n g i n p u t . A v o l t a g e b e t w e e n 0 V a n d 2 V a p p l i e d t o t h a t p i n p r o g r a m s t h e
p h a s e d e l a y o f t h e o p e r a t i n g f r e q u e n c y c o m p a r e d t o t h e s y n c h r o n i z i n g f r e q u e n c y . A p p l y i n g V 5 ( 5 . 0 V ) p r o g r a m s t h e d e v i c e a s a m a s t e r r e g a r d i n g t h e m a i n o s c i l l a t o r f r e q u e n c y ( s e e S Y N C ) . T h e v o l t a g e a p p l i e d t o t h a t p i n i s a l s o u s e d t o d e t e r m i n e t h e p h a s e d e l a y i n a d i s t r i b u t e d d i m m i n gc o n f i g u r a t i o n
S A 2 8 S o u r c e c o n n e c t i o n o f s w i t c h A
S C 1 8 S o u r c e c o n n e c t i o n o f s w i t c h C
S E T 2 I O p e r a t i n g f r e q u e n c y p r o g r a m m i n g i n p u t . A r e s i s t o r c o n n e c t e d t o t h i s p i n p r o g r a m s t h e i n t e r n a l o p e r a t i n g f r e q u e n c y .
S T C 3 I S t a r t u p c a p a c i t o r . A c a p a c i t o r c o n n e c t e d t o t h a t p i n d e t e r m i n e s t h e t h e t i m e t h e d e v i c e w a i t s i n v o l t a g e r e g u l a t i o n f o r t h e l a m p t o s t r i k e .
S Y N C 1 I / O S y n c h r o n i z a t i o n i n p u t o r o p e r a t i n g f r e q u e n c y o u t p u t . I f t h e d e v i c e i s c o n f i g u r e d a s m a s t e r ( s e e P H ) t h e p i n i s u s e d t o p r o v i d e t h e s y n c h r o n i z a t i o n f r e q u e n c y f o r t h e s l a v e s . O t h e r w i s e t h e d e v i c e w o r k s a s s l a v e a n d u s e s t h e a p p l i e d f r e q u e n c y a t t h a t p i n f o r s y n c h r o n i z i n g t h e o p e r a t i n g f r e q u e n c y .
V 5 2 3 I / O I n p u t / O u t p u t o f t h e i n t e r n a l 5 V r e g u l a t o r f o r g a t e d r i v e s u p p l y a n d c o n t r o l s u p p l y . A c a p a c i t o r m u s t b e c o n n e c t e d t o t h a t p i n t o d e c o u p l e s w i t c h i n g n o i s e c a u s e d b y t h e g a t e d r i v e r s .
V 5 A 2 6 O S u p p l y i n p u t f o r t h e g a t e d r i v e r o f t h e h i g h - s i d e s w i t c h A . A c a p a c i t o r m u s t b e c o n n e c t e d t o t h a t p i n t o s u p p l y t h e g a t e d r i v e r d u r i n g s w i t c h i n g ( b o o t s t r a p ) .
V 5 C 2 0 O S u p p l y i n p u t f o r t h e g a t e d r i v e r o f t h e h i g h s i d e s w i t c h C . A c a p a c i t o r m u s t b e c o n n e c t e d t o t h a t p i n t o s u p p l y t h e g a t e d r i v e r d u r i n g s w i t c h i n g ( b o o t s t r a p ) .
V A - 1 0 I V o l t a g e a m p l i f i e r n e g a t i v e i n p u t . T h i s i n p u t i s u s e d t o c o n n e c t t h e c o m p e n s a t i o n c a p a c i t o r f o r c o m p e n s a t i n g t h e v o l t a g e l o o p .
V A O 9 O V o l t a g e a m p l i f i e r o u t p u t . T h i s i s t h e o u t p u t f o r t h e v o l t a g e a m p l i f i e r . I t i s u s e d t o c o n n e c t t h e c o m p e n s a t i o n c a p a c i t o r f o r t h e v o l t a g e l o o p .
V C C 2 4 I D e v i c e s u p p l y v o l t a g e i n p u t . V C C m u s t b e c o n n e c t e d t o V 5 i n c a s e t h e d e v i c e i s p o w e r e d d i r e c t l y f r o m a r e g u l a t e d 5 V r a i l .
V R E F 3 0 O V o l t a g e r e f e r e n c e . O u t p u t o f t h e i n t e r n a l 3 . 3 V r e f e r e n c e f o r u s e w i t h a l l t h e a n a l o g c o n t r o l i n p u t s .
V S E N 1 1 I V o l t a g e s e n s e . M e a s u r i n g i n p u t f o r t h e l a m p v o l t a g e . T h i s v o l t a g e i s u s e d f o r l a m p v o l t a g e r e g u l a t i o n ( o p e n l a m p r e g u l a t i o n ) a n d o v e r v o l t a g e p r o t e c t i o n . S e n s e d A C v o l t a g e s c a n b e a p p l i e d
d i r e c t l y . T h e y a r e r e c t i f i e d i n t e r n a l l y .
6 S u b m i t D o c u m e n t a t i o n F e e d b a c k
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GA
GB
GC
GD
SA
PGND
SC
V5A
V5C
V5
Gate
Control
CA
CAO
VA
Main Control
VREF_OCP
OCP
Oscillator Phase Shift
Control
SET
PH
EN
VCC
VREF
GND
Startupand Strike
ControlSTC
Analogand
Burst
Dimming
ABR
BF
V5
VREF
VREF_VREG
VREF_OVP
OVP
V5
OVP
Control Supply
OCPFAULT
OCP
VAO
OVP
BBR
BC
V5
VREF
Rectifier CSEN
Rectifier VSEN
SYNC
P A R A M E T E R M E A S U R E M E N T I N F O R M A T I O N
GA
GB
GC
GD
SA
PGND
SC
V5A
V5C
V5
CA
CSEN
VA
OCP
PH
SET
EN
VCC
VREF
GND
STC
ABR
BF
FAULT
VSEN
BBR
BC
C1Q
A
TPS68000
2 V
3.3 V
R1
C5
C7
VLOGIC
Supply Voltage
8V .. 30V
Error Output
Operating Frequency
Device Enable
Lamp current(Analog Dimming Input)
Burst Duty Cycle
(Burst Dimming Input)
Direct Burst Dimming Input(Frequency + Duty Cycle)
C10
C3
C4
C2
C12
C13
R4R
3
C8
C9
SYNC
R2
2.0 V0 V
CAO
VAO
C14
QC
QB
QD
T1
C6
0 V
0 V
Burst Frequency
Synchronization
SynchronizationPhase Shift
T P S 6 8 0 0 0
S L V S 5 2 4 A O C T O B E R 2 0 0 5 R E V I S E D F E B R U A R Y 2 0 0 6
F U N C T I O N A L B L O C K D I A G R A M ( T P S 6 8 0 0 0 )
7S u b m i t D o c u m e n t a t i o n F e e d b a c k
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T Y P I C A L C H A R A C T E R I S T I C S
IO Output Current at V5 mA
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
0 10 20 30 40 50 60 70 80
VCC = 24 V
VO
OutputVoltageatV5V
VCC = 12 V
IO Output Current at VREF mA
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
0 2 4 6 8 10 12 14 16
VO
OutputVoltageatVREFV
V5 = 5 V
T P S 6 8 0 0 0
S L V S 5 2 4 A O C T O B E R 2 0 0 5 R E V I S E D F E B R U A R Y 2 0 0 6
T a b l e o f G r a p h s
F I G U R E
O u t p u t v o l t a g e a t V 5 v s o u t p u t c u r r e n t a t V 5 1
O u t p u t v o l t a g e a t V R E F v s o u t p u t c u r r e n t a t V R E F 2
O p e r a t i n g f r e q u e n c y v s r e s i s t a n c e a t S E T 3
P h a s e s h i f t o f o p e r a t i n g f r e q u e n c y v s v o l t a g e a t P H 4
B u r s t d i m m i n g d u t y c y c l e v s v o l t a g e a t B B R 5
B u r s t d i m m i n g p h a s e s