maurice goodrick & bart hommels, university of cambridge ecal dif: issues & solutions...
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Maurice Goodrick & Bart Hommels , University of Cambridge
ECAL DIF: Issues & Solutions
Readout Architecture
Maurice Goodrick & Bart Hommels , University of Cambridge
DIF-Slab, Slab-DIFControl: ODR – LDA – DIF – VFE Readout: VFE – DIF – LDA – ODR
ODR
SLABDIF
SLABDIF
SLABDIF
SLABDIF
SLABDIF
SLABDIF
LDA
LDA
Maurice Goodrick & Bart Hommels , University of Cambridge
Reality● 6 Rows of VFEs ● Some Daisy-Chained
PanelDIF Panel Panel Panel
● Many Multi-drops ● Some Differential & Zo
● Some Star● VFE & Slab Dependant
Maurice Goodrick & Bart Hommels , University of Cambridge
Personality and Adapter Card !!
Com
mon D
IF
Panel Panel Panel
Bulk Power
ADAP
Power Control & Distribution
Fan-out & Routing
Perso
nality
Multi-Row, Multi-Panel SlabADAP CardDIF Card
Maurice Goodrick & Bart Hommels , University of Cambridge
= A Multi Purpose DIF for ECAL
Should Support:● Test Slab in the Lab – WP2.2 core work
● EUDET prototype in the lab
● EUDET prototype in Test Beam
● Next ASICs
● Test bed for ILC environment
Maurice Goodrick & Bart Hommels , University of Cambridge
Many Possible DIF-SLAB Arrangements
VFE operation, Slab routing choices and Redundancy provision have major implications: this is a notional situation:
● 1 Clock & Control pair per Row● I2C Slow Control● Duplicate Slow Control paths● Common Data & DValid lines
We will encounter a large number of different arrangements thanks to permutations of:
● VFE variants: HARDROC, SKIROC,,, with their iterations● Evolving Slab designs
Maurice Goodrick & Bart Hommels , University of Cambridge
A Top-Level Description “Personality” Firmware tailors the protocol, while the Adapter Card tailors mechanics, interconnection & power distribution
This arrangement shows a 6-row
HARDROC Slab
Maurice Goodrick & Bart Hommels , University of Cambridge
VHDL
It is very worthwhile adopting a VHDL description at this stage:● behavioural description provides key framework:
● will prove the viability of the scheme● will allow fine tuning● allows rapid description and testing of different flavours for different tasks (Test Panel, EUDET Prototype, …)
● specific VFE VHDL code can be included (as has been done for HARDROC)
ODR LDA SLABDIF
Maurice Goodrick & Bart Hommels , University of Cambridge
Making it Fit
LH DIF 1.6
LH DIF 1.6
LH DIF 1.6
LH DIF 1.6
LH DIF 1.6
LH DIF 1.6
RH DIF 1.6
RH DIF 1.6
RH DIF 1.6
RH DIF 1.6
RH DIF 1.6
RH DIF 1.6
SLAB0.8
0.8
3.1 (3.4)
SLAB0.8
0.8
3.1 (3.4)
SLAB0.8
0.8
3.1 (3.4)
3.1 (3.4)
3.1 (3.4)
3.1 (3.4)
3.95 (3.65)
3.95 (3.65)
3.95 (3.65)
3.95 (3.65)
5.55 (5.25)
5.55 (5.25)
NOMINAL SPACINGS(ADAPTER CARDS IGNORED)
3.1 (3.4)
3.1 (3.4)
3.1 (3.4)
20mm OVERLAP
8.65
8.65
8.65
8.65
Side View Rear View
Card Spacing: based on Marc Anduze’s ECAL Module design
Maurice Goodrick & Bart Hommels , University of Cambridge
A Layout
DI F-Adapter
HDMI
HPDPI
US
B
Adapter (1600um)
DI F (1600um)
SLAB (800um)
DI F-DI F Pin-Out
CkOP+CkOP-
GND
CtOP
DaOP+DaOP-
GND
SpOP
CkI P+CkI P-GND
CtI P
DaI P+DaI P-GND
SpI P
180mm
100mmCL
Maurice Goodrick & Bart Hommels , University of Cambridge
How it Fits Together
The rotation routes DIF-DIF Outputs to Inputs and, combined with the lateral asymmetry, gives head room for components
Maurice Goodrick & Bart Hommels , University of Cambridge
The LDA Interface
Clock Clock
LtoD[i]Da
LtoD[i]Ck
D[i]toLSp
LtoD[i]Sp
D[i]toLDa
LDA
FPG
A
DIF
[i]
FPG
A
Pair1 (STP)
Pair2 (STP)
Pair4 (STP)
Pair3 (STP)
Pair5 (UTP)
LVDSFan-Out
LVDSTX
LVDSTX
LVDSRX
1
4
15 15
7 7
4
1
2
5
8 8
5
2
3
6
16 16
9 9
6
3
STP
STP
STP
UTP
C
C
C
C
C
C
C
C
RT
RTR
TRT
RGRG
RG
LVDSRX 10 10
11 11
12 12
STP
C
C
RT
RG
Possible Pinout f or HDMI(Based on SAMTEC HPDPIcable signal designation)
LDA-DIF Cable and Connector
Maurice Goodrick & Bart Hommels , University of Cambridge
In Conclusion
● We are producing a Multi-purpose DIF for ECAL
● We are working on the Adapter Card and Personality to allow it to
be used for further Slab signal path studies using the existing
Test Panel
● It will support laboratory work with prototype Slabs with different
VFE chips and their different iterations
● It will be usable with single and multiple EUDET ECAL modules
● The VHDL model should be an invaluable testbed for modelling
different VFEs and Slabs
● It should also allow command and data structures to be tested
● We welcome discussion with other interested groups
Maurice Goodrick & Bart Hommels , University of Cambridge
A Multi Purpose DIF for ECAL
ODR
Det
Form
at
SLABDIF
SLABDIF
SLABDIF
SLABDIF
SLABDIF
SLABDIF
LDA
LDA
Oto
L Fo
rmat
LtoD
Form
at
Dto
S F
orm
at
Different Formats at Different Levels