matlab/simulink image processing implementation on ...hdl coder ®: generate ip core for zynq -7000...
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1 © 2014 The MathWorks, Inc.
MATLAB/Simulink – Image Processing
Implementation on FPGA by HDL Coder
Code Generation, Evaluation, Custom Board and Reference
Design API for Zynq Workflow
Charles Su
TeraSoft
2
Agenda
Image Processing Platform
Target IP Core in HDMI passthrough Reference Design
Verification and Story
3
Image Platform – FPGA & HDMI Passthrough
Zedboard (ZC702)
FMC-IMAGEON
Image Sensor with HDMI Input/Output
FMC Bundle
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Image Platform – FPGA & HDMI Passthrough
1920x1080 @ 60 frame/sec
HDL
Image
Processing
IP core
FullHD
Video Input
FullHD
Video
Output
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The Perfect Couple in Image Design Workflow
MATLAB/Simulink HDL Coder + Xilinx Vivado IP Integrator
Simulink : Sobel Edge Detection Algorithm, Simulation & Verification
HDL Coder : Generate IP core for Zynq® -7000 platform & automatically integrate it into
Vivado IP Integrator
Vivado IP Integrator : Connection IP Block, Synthesis, Implementation & Bitstream
Program
Algorithm
Model
Generic IP
across platforms
HDL
IP Core
Algorithm
HDL
Simulink/MATLAB
algorithm
AXI Interface
Prototyping the generated IP
on custom Reference Designs and SoC Boards
Custom Reference Design
HDL
IP coreProcessor
Custom Reference Design
HDL
IP coreProcessor
6
Agenda
Image Processing Platform
Target IP Core in HDMI passthrough Reference Design
Verification and Story
7
Board and Reference Design
Processor
AXI4-Lite
Algorithm
Model
Generic IP
across platforms
HDL
IP Core
Algorithm
HDL
Simulink/MATLAB
algorithm
AXI Interface
Reference Design
Processor
AX
I4-L
ite Placeholder
for
Algorithm
IP Core
HDL
IP core
SOC Board
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Multiple Reference Designs
Reference Design
Processor
AX
I4-L
ite Placeholder
for
Algorithm
IP Core
Reference Design
Processor
AX
I4-L
ite
AXI
DMA
Placeholder
for
Algorithm
IP Core
SOC Board
9
Reference Design
Processor
AX
I4-L
ite
AXI
DMA
External and Internal Interfaces
Placeholder
for
Algorithm
IP Core
HDL
IP core
Interface LED Interface
Interface ADC
Interface
IP
Interface
External
Interface
Internal
Interface
(15b)
AXI
Interface
SOC Board
10
Reference design for IP integrator 32bit AXI4-Stream
RGB represented in
Xilinx Video Data Format
32'hFFRRBBGG
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MATLAB/Simulink HDL Workflow Advisor for
Video in AXI4-Stream
Video Data
VALID
SOF - m_axis_video_tuser
EOL Signal - m_axis_video_tlast
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MATLAB/Simulink HDL Workflow Advisor for
Video in AXI4-Stream
Video Data
VALID
SOF - m_axis_video_tuser
EOL Signal - m_axis_video_tlast
Video Data
Valid
TUser
TLast
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MATLAB/Simulink HDL Workflow Advisor for
Video out AXI4-Stream
Video Data
VALID
SOF - m_axis_video_tuser
EOL Signal - m_axis_video_tlast
Video Data
Valid
TUser
TLast
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MATLAB/Simulink HDL Model
Enable Algorithm by Valid
Valid
32bits Video Data
8bits x 4
32bits to 8bits
Image Latency
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MATLAB/Simulink Video IP Core Simulation
Control Signal for Video format
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HDL Workflow Advisor
Synthesis
Mapping
Place and Route
Optimize for
Speed and
Area
HDL Workflow
Advisor
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Linking Generated HDL Code to a Simulink®
Block
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Tracing a Simulink® Block to Generated HDL
Code
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How do we target a Custom SoC Board?
Avnet Zynq
Motor Control Kit
ZYBO
or a Custom Application Design?
ADI + Zynq ZC706 SDR
ZC702
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Custom Board and Reference Design API
Prototype on your own board
Interface to custom hardware
Run algorithm in real-time
SW AXI driver, External Mode
Define your own Zynq Board and
Reference Design
R2015a
Algorithm
Model
Generic IP
across platforms
HDL
IP Core
Algorithm
HDL
Simulink/MATLAB
algorithm
AXI Interface
Prototyping the generated IP
on custom Reference Designs and SoC Boards
Custom Reference Design
HDL
IP coreProcessor
Custom Reference Design
HDL
IP coreProcessor
21
Agenda
HDL Code from MATLAB/Simulink
Target Custom SoC Board or Application Design
Verification and Story
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Shorter implementation time by 48% (total project 33%)
Reduced FPGA prototype development schedule by 47%
Shorter design iteration cycle by 80%
ROI: Customer Adoption Of Model-Based Design Time spent on FPGA implementation
1st FPGA Prototype 2nd FPGA Prototype
1st FPGA Prototype
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Verification Landscape Solution:
Re-use System Level Test Bench
Model VHDL / Verilog FPGA
Requirements
Functional
Equivalence
Coverage
Property Proving
Virtual Platforms
Requirements
Equivalence
Coverage
Assertions
Equivalence
Regression
Timing Analysis
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MATLAB Code
10X more concise
HDL Coder
HDL
Coder
60% reduction in time to produce a
working prototype
Reference: http://www.mathworks.com/company/user_stories/flir-accelerates-development-of-thermal-imaging-fpga.html?s_tid=srchtitle
FLIR Systems
Provides VHDL and Verilog
code generation for MATLAB
and Simulink
25 © 2014 The MathWorks, Inc.
Thank you!