matlab and simulink for embedded system...
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![Page 1: MATLAB and Simulink for Embedded System Designmsdl.cs.mcgill.ca/people/mosterman/presentations/date07/tutorial.pdf · 19 C MATLAB® and Simulink® Algorithm and System Design Real-Time](https://reader034.vdocuments.us/reader034/viewer/2022050902/5a78d98b7f8b9a77088bf3eb/html5/thumbnails/1.jpg)
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MATLAB® and Simulink® for Embedded System Design
Pieter J. [email protected] Senior Research ScientistThe MathWorks, Inc.
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Introduction
Increasing complexity of embedded systems Complexity
– Intricacy– Size
Raising the Level of Abstraction Compilers to handle the complexity because of
size
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Agenda
The System Design Challenge Software Design Flow Hardware Design Flow Summary
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The System Design Challenge
We design, simulate, and validate system models and algorithms in MATLAB® and/or Simulink®
How can we implement and verify designs on DSPs and GPPs?
How can we implement and verify designs on FPGAs and ASICs? C
MATLABMATLAB®® and Simulink and Simulink®® Algorithm and System DesignAlgorithm and System Design
MCU DSP FPGA ASIC
HDL
![Page 5: MATLAB and Simulink for Embedded System Designmsdl.cs.mcgill.ca/people/mosterman/presentations/date07/tutorial.pdf · 19 C MATLAB® and Simulink® Algorithm and System Design Real-Time](https://reader034.vdocuments.us/reader034/viewer/2022050902/5a78d98b7f8b9a77088bf3eb/html5/thumbnails/5.jpg)
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Integrated Design Flow for Embedded Software and Hardware
Design, simulate, and validate system models and algorithms in MATLAB and Simulink
Automatically generate C and HDL
Verify hardware and software implementations against the system and algorithm models
C
MATLABMATLAB®® and Simulink and Simulink®® Algorithm and System DesignAlgorithm and System Design
Real-Time WorkshopReal-Time WorkshopEmbedded Coder,Embedded Coder,
Targets, LinksTargets, Links
Verif
y
Simulink HDL CoderSimulink HDL CoderLink for ModelSimLink for ModelSim
Link for Link for CadenceCadence Incisive Incisive
MCU DSP FPGA ASIC
HDL
Generate
Verif
y
Generate
![Page 6: MATLAB and Simulink for Embedded System Designmsdl.cs.mcgill.ca/people/mosterman/presentations/date07/tutorial.pdf · 19 C MATLAB® and Simulink® Algorithm and System Design Real-Time](https://reader034.vdocuments.us/reader034/viewer/2022050902/5a78d98b7f8b9a77088bf3eb/html5/thumbnails/6.jpg)
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Agenda
The System Design Challenge Software Design Flow Hardware Design Flow Summary
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C
MATLABMATLAB®® and Simulink and Simulink®® Algorithm and System DesignAlgorithm and System Design
Real-Time WorkshopReal-Time WorkshopEmbedded Coder,Embedded Coder,
Targets, LinksTargets, Links
Verif
y
Simulink HDL CoderSimulink HDL CoderLink for ModelSimLink for ModelSim
Link for Link for CadenceCadence Incisive Incisive
MCU DSP FPGA ASIC
HDL
Generate
Verif
y
Generate
Integrated Design Flow for Embedded Software Implementation with
automatic C code generation
Implementation– Floating- and fixed-point code– Integration with downstream
IDEs and tools– Links to verification– Device drivers– Optimization options
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Representative Application – Video Video system design and implementation
– Encapsulates challenges: complexity, convergence, time-to-market
– Sophisticated algorithms
– Floating- and fixed-point issues
– DSP or FPGA/ASIC implementations
Design flows and steps shown directly applicable to other signal processing applications
Embedded Software Case Study:
Video Edge Detection on a DSP
LiveMATLABDemo
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Example: Video Edge Detection Floating point video edge detection system based on
Prewitt algorithm Compositing original image with detected edges Utilizes blocks from Video and Image Processing Blockset
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Converting to Fixed-Point Polymorphic blocks capable of floating- and fixed-point
operation 8-bit input datatype – blocks inherit fixed-point data Simulink Accelerator provides fast fixed-point simulation
8-bit fixed-point input
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Automatic Code Generationfor Implementation on GPPs and DSPs
Fixed-point model
Code generation options
and preferences
Select target or flavor of generated code
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Code Generation Report
HTML report
Links to code files from HTML report
Readable, commented code
Links to Simulink model from
generated code
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Video Edge DetectionEmbedded Software System on TI 6000TM
TCP/IP Blocks
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Target Code Generation Options
High-Speed RTDX
Incorporate DSP/BIOS
Inline Signal Processing Blockset functions
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Build and execute– Auto-generate C and ASM
– Integrate RTOS and scheduler
– Create full CCS project
– Invoke compiler, linker, and download code
– Run on target
Profile code performance
Code Execution on Target and Profiling
System profiling includes entire DSP
application codeSubsystem profiling
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Code Optimization Options
Utilize target-specific blocks– C-callable assembler libraries– Simulate bit-true in Simulink– Generate calls to hand-optimized
assembler libraries– Highly optimized implementation
of core functionality– C62x and C64x fixed-point DSPs
Manual optimization by user
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Design Verification and Visualization:MATLAB as software test bench
Captured video
Visualize and debug embedded software with MATLAB
Input video
MATLAB script (test bench)
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Design Verification and Visualization:Simulink as software test bench
Processor and hardware-in-the-loop testing, simulation,
visualization, and verification of embedded software with Simulink
Device or design under test (DUT)
Simulink system design embedded on DSP
Simulink test bench
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C
MATLABMATLAB® ® and Simulinkand Simulink®® Algorithm and System DesignAlgorithm and System Design
Real-Time WorkshopReal-Time WorkshopEmbedded Coder,Embedded Coder,
Targets, LinksTargets, Links
Verif
y
Simulink HDL CoderSimulink HDL CoderLink for ModelSimLink for ModelSim
Link for Link for CadenceCadence Incisive Incisive
MCU DSP FPGA ASIC
HDL
Generate
Verif
y
Generate
Review: Integrated Design Flow for Embedded Software Drive system development
with an executable specification
Quickly create complete working code base
Use code profiles to identify and optimize bottlenecks
Verify code with Links to IDEs and processors
![Page 20: MATLAB and Simulink for Embedded System Designmsdl.cs.mcgill.ca/people/mosterman/presentations/date07/tutorial.pdf · 19 C MATLAB® and Simulink® Algorithm and System Design Real-Time](https://reader034.vdocuments.us/reader034/viewer/2022050902/5a78d98b7f8b9a77088bf3eb/html5/thumbnails/20.jpg)
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Agenda
The System Design Challenge Software Design Flow Hardware Design Flow Summary
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C
MATLABMATLAB®® and Simulink and Simulink®® AlgorithmAlgorithm andand System DesignSystem Design
Real-Time WorkshopReal-Time WorkshopEmbedded Coder,Embedded Coder,
Targets, LinksTargets, Links
Verif
y
Simulink HDL CoderSimulink HDL CoderLink for ModelSimLink for ModelSim
Link for Link for CadenceCadence Incisive Incisive
MCU DSP FPGA ASIC
HDL
Generate
Verif
y
Generate
Integrated Design Flow for Hardware (FPGA and ASIC) Design elaboration
Implementation– HDL code generation
(VHDL and Verilog)– test bench generation– Links to verification– Integration with
synthesis tools
![Page 22: MATLAB and Simulink for Embedded System Designmsdl.cs.mcgill.ca/people/mosterman/presentations/date07/tutorial.pdf · 19 C MATLAB® and Simulink® Algorithm and System Design Real-Time](https://reader034.vdocuments.us/reader034/viewer/2022050902/5a78d98b7f8b9a77088bf3eb/html5/thumbnails/22.jpg)
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What We Will Show In This Case Study Behavioral modeling and simulation Fixed-point modeling and simulation Design elaboration HDL generation Co-simulation using Link for ModelSim
LiveMATLABDemo
Hardware Case Study:Video Edge Detection
on an FPGA
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Executable Specification
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Design Elaboration
Automatically generate Verilog or VHDL code from
elaborated models
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HDL Code Generation Using GUI
Select subsystem, target language, directory
Select output options
Check model for errors Generate HDL Code
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More Code Generation Options
Select reset andclock options
Set language-specific options: input/output datatypes, timescale
directives, …
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Automatically Generate Test Bench
Self-checking HDL test bench compares Simulink results to HDL results
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Co-simulate Generated HDL
HDL code executing on ModelSim simulator
Link for ModelSim
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C
MATLABMATLAB® ® and Simulinkand Simulink®® Algorithm and System DesignAlgorithm and System Design
Real-Time WorkshopReal-Time WorkshopEmbedded Coder,Embedded Coder,
Targets, LinksTargets, Links
Verif
y
Simulink HDL CoderSimulink HDL CoderLink for ModelSimLink for ModelSim
Link for Link for CadenceCadence Incisive Incisive
MCU DSP FPGA ASIC
HDL
Generate
Verif
y
Generate
Review:Integrated Design Flow for Hardware Drive system development
with an executable specification
Quickly create complete working HDL code baseand test benches
Verify code with Links to RTL simulators and synthesis tools
![Page 30: MATLAB and Simulink for Embedded System Designmsdl.cs.mcgill.ca/people/mosterman/presentations/date07/tutorial.pdf · 19 C MATLAB® and Simulink® Algorithm and System Design Real-Time](https://reader034.vdocuments.us/reader034/viewer/2022050902/5a78d98b7f8b9a77088bf3eb/html5/thumbnails/30.jpg)
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Agenda
The System Design Challenge Software Design Flow Hardware Design Flow Summary
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C
MATLABMATLAB®® and Simulink and Simulink®® Algorithm and System DesignAlgorithm and System Design
Real-Time WorkshopReal-Time WorkshopEmbedded Coder,Embedded Coder,
Targets, LinksTargets, Links
Verif
y
Simulink HDL CoderSimulink HDL CoderLink for ModelSimLink for ModelSim
Link for Link for CadenceCadence Incisive Incisive
MCU DSP FPGA ASIC
HDL
Generate
Verif
y
Generate
Summary
Accelerate development using Model-Based Design– Generate
• Real-Time Workshop• Simulink HDL Coder
– Verify• Link for Cadence
Incisive
Design and verify software and hardware from MATLAB and Simulink