master of technology in vlsi design effective from … · 2016-07-12 · vlsi design effective from...

I.E.C. UNIVERSITY

BADDI (SOLAN) H.P.

MASTER OF TECHNOLOGY IN

VLSI DESIGN

EFFECTIVE FROM THE ACADEMIC YEAR(2013-14)

INDEX

1. Programme Objectives

2. Programme Outcomes

3. Academic Regulations

4. Flexible Credit base system

5. Proposed Scheme of Evaluation

6. Detailed syllabus semester wise

M.ECH(VLSI) MISSION

To provides high quality of technical education to make students able to solveuniversal technical problems.

To train students to produce creative solution with moral, professional and ethicalvalues. To provides the technical knowledge and skills that will enable students tohave a successful career in the electronics and communication engineering.

To provides the best skilled, hands on practicing electronics engineers. .

PROGRAMME OBJECTIVES

This Postgraduate specialized course has been structured to make students familiar with thedesign methodologies and complexities of advanced and current IC design technologies. Itaims to equip students with the knowledge of different aspects of nanometer/VLSI ScaleASIC and IC design methodologies and offer hands-on design capabilities for digital, analogand mixed signal ASIC/IC design.

PROGRAMME OUTCOMES

(a) This is an interdisciplinary graduate program that helps shaping the future leaders ofVLSI industry.

(b) The program emphasizes on the interface between VLSI Design and ComputerEngineering and focuses on the application of VLSI Design to Computer SystemsDesign and Development and also on the algorithmic approach to computerengineering as extended to the area of VLSI design.

(c) Student gets the advantage of being trained in software/hardware interfacing aspectsalong with complete knowledge of VLSI Circuits and Layouts preparing them forIndustries and Academia.

(d) Placement in leading core companies like Intel, IBM, ARM, Free-scaleSemiconductors, Wipro, Sasken, Philips, GDA Tech, Synopsis, Cadence, Magma,Mentor Graphics, Texas Instruments, Analog Devices, 3D, Motorola, Honeywell,HCL Technologies, Interra Systems, Soliton, Honeywell, Cypress Semiconductors,Micro-chip, Tata Elxsi etc.

ACADEMIC REGULATIONS

PREAMBLE

M.TECH VLSI programme under Flexible Credit System Based (FCBS) shall adopt aSemester system. There will be two semesters in an academic year. Normally theODD semester will be from July to December & Even Semester from December toMay.

As part of our objective of providing quality education & making the graduatesemployable, IEC University is taking up the step in this direction by introducing theFlexible Credit Based System (FCBS).

Thus, the students can register courses of their choice & alter the pace of learningwithin the broad framework of academic programmes & credit requirements.

Students can register courses according to their interest & academic ability incompleting them.

FCBS allows students in deciding their academic plan & permits students to alter it asthey progress during the programme.

The academic counsellor helps the students in identifying the courses based onprogramme requirement, course pre requisite, students’ ability & interest in variousacademic disciplines.

The extract of PG Academic regulations given hereunder is for general information,& the students are advised to go through the detailed regulations of the programme inwhich he/she is admitted.

ADMISSION AND ENROLMENT OF STUDENTS

• Admission shall be done on the basis of merit, providing for reservations inaccordance with the Act.

• The merit shall be determined by the marks obtained by the candidates in qualifyingexamination.

ELIGIBILITY CRITERIA FOR ADMISSION

Qualification B.Tech./B.E./M.Sc. or equivalent in Electronics &Communication Engineering, Electronics Engineering

The candidate should also satisfy the conditions regardingminimum marks, the number of attempts in the qualifyingexamination & age as prescribed by the AICTE/UGC fromtime to time, & physical fitness as may be prescribed bythe Academic Council of the University.

Eligibility criteria for admission to Foreign Nationals (FN)/ Person Of Indian

Origin(PIO)/ Children Of Indian Workers In Gulf Countries ( CIWGC) In PG/

Integrated Programmes

The FN/ PIO/ CIWGC students shall meet the eligibility conditions outlined above.

The qualifying examinations passed by FN/ PIO/ CIWGC students should be

considered equivalent to eligibility examinations by the Association of Indian

Universities/ Academic council.

The candidate should also satisfy other conditions as prescribed by the AICTE/UGC

from time to time, & physical fitness as may be prescribed by the Academic Council

of the University.

Note: The candidates appearing in the qualifying examinations are also eligible to apply,

subject to the condition that they must fulfil the eligibility criteria as given above at the

time of registration in the programme.

MEDIUM OF INTRUCTION AND EXAMINATIONS

The medium of instructions and examination shall be English in all the programmes, except

in language courses where it is necessary to use the corresponding mediums.

UNIVERSITY FEE

Every student has to deposit his total Fee, other charges and dues, if any, in the beginning of

the semester at the time of Registration, failing which he will not be permitted for registration

in the programme.

FELLOWSHIPS, SCHOLARSHIPS, STIPENDS, MEDALS AND PRIZES

Fellowships, Scholarships, Stipends, Medals and Prizes may be instituted by the University

and awarded as per rules.

REGISTRATION

• Every Student will register every semester for courses that he wishes to pursue in that

semester.

• A non-registered student will not be allowed to attend classes and take examination

even if he has paid the fees.

• The late registration of a freshman who is admitted after the start of the semester

may be done at the time of admission by the authorized official.

Adding and Dropping of Courses

• A student may be permitted to add or drop course(s) within two weeks of the

beginning of the semester.

• In case a student has been allowed to change the course or programme during

the current semester by the University, the classes attended in the previous

course may also be considered in calculation of attendance to determine the

eligibility for appearing in ESE.

MID – TERM MIGRATION OF STUDENTS

• Inter-university migration shall not be allowed in normal circumstances.

• Under exceptional circumstances, mid-term transfer of a student from any other

University to IEC University may be permitted on a case to case basis. In all such

cases, the approval on the transfer of relevant credits the student has already

earned in that University may be granted by the Academic Council.

TRANSFER OF PROGRAMME

A student once admitted and registered in a programme will not be allowed

to change the programme under any circumstances.

ACADEMIC SYSTEM

• The University will follow semester system in all of its PG/ Integrated programmes.

Summer Semester

• The Vice Chancellor may decide to hold a Summer semester on the

recommendation of the Academic Advisory Committee.

• Summer semester is a special privilege to be offered at the discretion of the

University, and the University will not be under any obligation to offer summer

semester every year.

• Summer semester, if offered, may be allowed only for students who are not ondisciplinary probation.

• A list of courses to be offered in the summer semester is brought out during the evensemester before the ESE. Only a few selected courses as decided by the Universitymay be offered during the summer semester.

• A course may be offered in the Summer semester if there are a minimum of tenstudents registering for it.

• Unless prescribed otherwise in the Regulations of any specific programme, theSummer semester is a fast-paced semester where all the rules for the normalsemester shall apply but the registration shall be limited to three courses havingtotal credits not exceeding 12.

• The Summer semester may be of about seven to eight weeks duration and eachcourse may run on about two times the normal load, thus imparting equivalent toabout 16 weeks of teaching, but at an accelerated pace.

• Whenever possible, the deficient students may be allowed to register for backlogcourses and/ or marginal courses (in which they have obtained D grade) in theSummer semesters on payment of necessary fees per course.

• A student can normally register only for backlog or marginal courses for theSummer semester.

• In view of the short duration of the Summer semester, late registration and addingand dropping of courses are not permitted beyond three days of the start of classes

Academic Counsellor

• Upon joining the University, each student will be assigned an Academic Counsellor.

• The Academic Counsellor will discuss with the student his academic performance in

previous semester(s) and suggest the number and nature of courses the student should

register during the ensuing semester, within the framework of that Programme

curriculum.

• The Academic Counsellor may advice students having many backlog courses to

register for lesser number of credits (subject to the minimum credits specifications)

and prepare a revised plan of study for the student with a slower pace.

Curriculum

Each programme contains a prescribed course structure which is generally calledCurriculum.

These courses will be offered to a student in a pre determined manner in eachsemester.

Students are expected to take course in each semester & clear them to variousconditions prescribed in this regulation.

Syllabus

• A course syllabus is a document that explains what a student is going to study in that

course.

• Each course will have a course code, course title, Lecture- Tutorial- Practical- Credit

(LTPC) distribution indicating the weightage of the course, version of syllabus

revision, course pre-requisites/ anti-requisites/ co-requisites (if any), course objectives,

expected outcome, short and detailed description of the topics, suggested text and

reference books, the mode of evaluation adopted, the effective date of application of

the revised version of the syllabus.

Course Plan

• A course plan consists of a list of lectures/ experiments carried out in each

instructional class/ lab by the course teacher during the semester as per the LTPC of

the course, with details like mode of delivery, reference material used, etc.

• One hour of lecture/ tutorial classes or two hours of laboratory work/ seminar/

practical/ group discussion per week constitutes ONE credit for the course. Separate

course plans need to be prepared for the theory and laboratory portions of any course,

if the course has an embedded lab component.

Example:

An LTPC of 2-1-2-4 means 2 hour of class room lecture; one hour of tutorial and

one hour of laboratory, all delivered within a calendar week. This course will

have 4 credits.

Maximum Credits: 135

Credits

Maximum Credit: 90

Project/ Thesis/ Dissertation:

• Wherever required in the PG/ Integrated programme, all students of that programmes

should successfully complete Project/ Thesis/ Dissertation work.

• A student has to select a thesis supervisor at the beginning of the last year of the

programme, if not done earlier.

• A student shall not normally have more than two supervisors at any given time.

• Thesis supervisor(s) of a student will normally be appointed from amongst the faculty

members of the University using modalities decided by the departments.

• A student can have a co-supervisor from outside the University on the

recommendation of the Supervisor and with approval of the Director of the Institute.

• In case there has been a change/addition in the supervisor(s), the thesis will not be

submitted earlier than three months from the date of such change.

• Normally, a faculty member shall not supervise more than five individual PG

candidates. However the department may evolve a transparent policy for the

distribution of PG students amongst the faculty members in the department.

• In case a faculty member is suspended / debarred for indulging in lowering the

prestige of the University in any manner, he shall cease to be a thesis supervisor.

• If a supervisor resigns/ expires/ leaves the University, alternative/ caretaker supervisor

be appointed by the Departmental Postgraduate Committee (DPGC.)

• Submitting a thesis that was bought (purchased)/ borrowed/ thesis submitted in

another University/ Institution shall be considered as examination malpractice and

will be awarded an ‘F’ grade.

• Students have the responsibility to decide on the specific thesis area and title, and

carry out substantial portion of the literature survey at the beginning of their final year.

• Various time limits specified for monitoring and evaluation of performance of the

student, to be announced by the University in each semester, should be strictly

followed.

Industrial/Practical Training

Wherever required in the programme, all the students of that programme should

undergo industrial/ practical training ina reputed industry in, anytime after one

year of study. This is listed in course structure.

Students who have completed their training are required to register for industrial/

practical training in the following semester for award of the grades.

Minimum/ Maximum Credit Limits for Course Registration

• The Average Academic Load in a regular semester will be of 23 credits.

• However, a fast pace student can register for a maximum of 28 credits.

• Similarly a slow pace student can register for a minimum of 16 credits in a regular

semester (other than during Summer semester).

• Under no circumstances, a student will be permitted to cross these limits.

• A student carrying out the last registration of his Programme will be permitted to

register less than 16 credits if the minimum credit requirements for the completion of

Programme so require.

• The average number of credits a student can register during a Summer semester shall

be between 6 and 8, or 2 courses.

• However, in special cases, the student may be permitted to register a maximum of 12

credits during a Summer semester.

• There is no minimum number of credits fixed for course registration during Summer

semester.

Course Prerequisites / Anti-requisites/ C-requisites

• Some courses may have specific prerequisites to be met before a student can register

for the course in the current semester.

• Students who had received an ‘F’ grade in a prerequisite course are also permitted to

register the next level course by assuming that they had attained the required

‘exposure’ by attending that course.

• This stand is adopted so that the student can make further progress towards earning

credits and his progress need not be pulled down by backlog courses. Thus,

concurrent registration of a prerequisite and next level course becomes a possibility.

• Similarly, a course may have an anti-requisite and/ or co-requisite.

• When two courses having almost similar/ same course contents and considered as

equivalent are made available to a student to choose within a group, and to prevent

students crediting both the courses, the anti-requisite option can be used.

• Similarly, an independent laboratory course can be coupled with a theory alone course

through a co-requisite thereby forcing a student to register both the courses together.

PG Teaching Experience

To provide an opportunity to Final year students having current CGPA 8.50 or more,

value-addition schemes are available in the University.

Such students may be awarded tutoring assignments in the lower year courses.

Such contributions will be duly recognized by providing financial support and making

a mention in the Grade sheets.

Vice Chancellor’s List

• Students who maintain a CGPA of 9.50 and above, starting from the beginning of

3rd semester results and subsequently, having no ‘F’ grade to their credit, having

never debarred for lack of attendance in any ESE or indiscipline, will be placed on

Vice Chancellor’s List for their meritorious performance.

• Their name will be removed from the Vice Chancellor’s List if their CGPA falls

below 9.50 or they receive an ‘F’ grade or are debarred due to lack of attendance

in any ESE or an act of indiscipline subsequently.

• Such students will be accorded benefits/ recognition as per rules.

Conversion Factor for Converting CGPA into Marks Equivalent

If a conversion to marks is required, the following formula may be used to calculate

the same:

The Equivalent Percentage of Marks = CGPA* 9.0 + 5

ATTENDANCE REQUIREMENTS

• A student must have 75% or more attendance in aggregate of delivered classes, in

all registered courses of theory (lectures plus tutorial) and practicals (including

workshops training, seminar, projects, industrial training etc.) of the

concerned semester.

• Only such students who fulfill the above 75% attendance criteria will be permitted to

appear in End Semester Examination (ESE).

• The cases of students having attendance less than 75% but more than or equal to 60%

shall be reviewed by the University on a case to case basis as per the Ordinance.

• If a student’s attendance falls below 60%, for any reason including medical, he will not

be allowed to appear in the ESE of any course registered in the semester. He will be

awarded ‘F’ grades in all the courses of that semester.

• Calculation of attendance for determining the eligibility to appear in ESE will be

based on the date of actual registration of the candidate, if late registration is

permitted by the University.

COMPONENTS OF EVALUATION

• In general, a course will have three components of evaluation viz. Continuous

A ssessment (CA), Mid-Semester Exams (MSE), and End- semester Exam

(ESE),

• CA will carry 40 Marks [Tutorials 10 Marks, Quizzes10 Marks, Assignments10

Marks, and Projects/ Case studies/ Viva voce 10 Marks]

• MSE will carry 20 marks.

•First MSE to be held after completion of 35% - 40% course coverage.

•Second MSE to be held after completion of 70% - 80% course coverage.

• ESE will carry 40 marks.

SYSTEM OF EVALUATION BASED ON BROAD BAND GRADES

• The University shall follow the Broad-band Grades systems for various PG

programmes as specified in the respective Programme detail.

• The course credit (C), number of lectures, tutorials, practicals (L), (T), (P) in a course

are related as C = (L + T + 0.5 P)

• The students will be awarded grades using relative grading in a course and

result cards will show individual course grades, the course credits and the

overall weighted performance indices such as SGPA (Semester Grade Point

Average) and CGPA (Cumulative Grade Point Average).

• The following broadband letter grades will be used to report a student’s performance

on a 10-point scale.

• The letter grades and their numerical equivalents on a 10-point scale (called Grade

Points) are as follows:

Letter

Grade

A AB B BC C D F

Grade

Points

10 9 8 7 6 4 0

• In addition to the above, there are three letter grades viz., I, S, and X which stands

for Incomplete, Satisfactory, and Unsatisfactory, respectively.

• For courses with zero weightage (audit) only satisfactory (S)/ Unsatisfactory (X)

grades are awarded.

• No student shall be awarded ‘A’ grade in any course unless he has secured a

minimum of 80% marks in the total of all components of evaluation in that course.

• No students shall be awarded ‘F’ grade in any course if he has secured a

minimum of 40% marks in the total of all components of evaluation in that course.

• In case a student repeats a particular course during summer semester along with

his juniors, he will be awarded only up to a maximum of AB grade based on his

current performance and the grade he obtained earlier.

• The statistical method shall invariably be used with marginal adjustment for the

natural cut off if the number of students appearing in a course is 60 or more. The

mean and standard deviation (σ) of marks obtained of all the students in a course

shall be calculated and the grades shall be awarded to a student depending upon

the marks and the mean and the standard deviation as per Table given below:

Lower Range of Marks Grade Upper Range of Marks

A ≥ Mean + 2.5 σ

Mean + 1.5 σ ≤ AB < Mean + 2.5 σ

Mean + 0.5 σ ≤ B < Mean + 1.5 σ

Mean - 0.5 σ ≤ BC < Mean + 0.5 σ

Mean - 1.5 σ ≤ C < Mean - 0.5 σ

Mean - 2.5 σ ≤ D < Mean - 1.5 σ

F < Mean - 2.5 σ

• If the number of students appearing in any course is less than 60, the grades in that

course will be awarded in the following manner :

Marks Obtained in a course out of 100 (M) Letter Grade

85 <= M <= 100 A

75 <= M <= 84 AB

65 <= M <= 74 B

55 <= M <= 64 BC

50 <= M <= 54 C

40 <= M <= 49 D

M <= 39 F

Incomplete I

• A student may be awarded the grade ‘I’ (Incomplete) in a course if he has missed

the ESE for a genuine reason.

• This grade must, however, be converted by the Faculty-In-Charge into an

appropriate letter grade within ten days from the completion of ESE.

• Any ‘I’ grade still outstanding two days after the prescribed last date, shall be

automatically be converted into ‘F’ grade.

• The course(s) in which a student has earned ‘F’ grade will be termed as back-log

course(s), which he has to improve by repeating/ replacing the course(s) as per the

rules.

• ‘F’ grade is also awarded to a student who is not allowed to/ do not appear in ESE in

a particular subject due to shortage of attendance, though he might have

undergone other components such as MSE, assignments, class tests, projects, etc.

• Such a student will be required to repeat the course in the Summer semester in

which he has secured ‘F’ grade.

• The Semester Grade Point Average is a weighted average of the grade points earned

by a student in all the courses credited and describes his academic performance in

a Semester. If the grade point associated with the letter grades awarded to a

student are say, g1, g2, g3,………. and the corresponding weightage is (credits)

are say, w1, w2, w3,………. the SGPA is given by:

• The Cumulative Grade Point Average indicates overall academic

performance of a student in all the courses registered up to and including

the latest completed Semester. It is computed in the same manner as SGPA,

considering all the courses (say, n), and is given by:

CGPA=∑ {credit of semester*SGPA of semester}/total credits

• The minimum CGPA requirement for the award of an Post Graduate degree/

diploma/ certificate will be 5.5 subject to getting ‘D’ or above grade in each of

the courses individually.

• A minimum of 4.5 SGPA in a UG programme is required in each semester for

moving to the higher semester.

• A student will not be allowed to move to higher Semester without clearing the

backlog courses so as to obtaining the required minimum SGPA and/ or CGPA.

• A student will be required to get grade ‘D’ or above in a course for passing in

the course.

• A student will be issued a Cumulative Grade Card at the end of each semester

indicating the grades secured for all the registered courses up to and including the

last semester.

EXAMINATION

• The period of Examination(s) (Mid semester and End semester) shall be as specified

in the Academic Calendar.

• All students who have registered for a particular course are eligible to write the

ESE of that course, except if he is declared ineligible due to one or more of reasons

listed below.

1. Shortage of attendance

2. Acts of indiscipline

3. Withdrawal of a course from Registration

• Make-up examinations are special examinations conducted for students who could

not take regularly scheduled examination and have been awarded the ‘I’ grade or

‘Incomplete’ result.

• Make–up examination is a special privilege to be offered at the discretion of the

University and the University will not be under any obligation to allow a student a

make-up examination. The student(s) shall have no right to cite the non-availability

of this facility as an excuse for his/ their poor performance.

• Make-up Examination for MSE and/ or ESE may not be allowed to students on

disciplinary probation

• A student, who has missed one or more papers in a regular examination because of a

genuine medical reason, may be permitted in Make-up Examination as per rules.

• A student appearing in a make up examination for ESE and/ or MSE in any course

shall not be awarded ‘A’ grade in that course.

• After valuation of MSE answer scripts, they will be handed over to students.

• Recounting of ESE answer scripts is permitted.

• There is no provision of re-evaluation of ESE answer scripts.

TERMINATION OF THE PROGRAMME

A student will be declared “Not Fit for the Programme (NFP)” and shall have to

discontinue if he does not satisfy following conditions:

After the completion of the First Year the student should have passed a

minimum of forty percent (40%) courses prescribed in the first year to be

calculated after the summer semester, if any.

Second Year onwards, the academic performance of a student is reviewed at

the end of every semester by the Academic Advisory Committee, and the

decision is taken on a case to case basis as per rules..

MAXIMUM DURATION FOR THE COMPLETION OF THE PROGRAMME

The maximum duration for completion of the degree/ diploma/ certificate, for the completion of

the course, subject to other conditions, shall be as follows:

Normal

Duration

Maximum Duration

Allowed

2 Years 4 Years

RESULT AND DIVISION

• A student will be issued a Cumulative Grade Card at the end of each semester

indicating the grades secured for all the registered courses up to and including the

last semester.

• The minimum CGPA requirement for the award of an Post Graduate degree/ diploma/

certificate/ integrated programme will be 5.5 subject to getting ‘D’ or above grade

in each of the courses individually.

• The result of a student may be withheld if,

(1) he has not paid all the dues, or

(2) if there is a case of indiscipline or use of unfair means or of

academic misconduct pending against him, or

(3) for any other reason as deemed fit by the University.

• Four divisions as defined below shall be awarded:

Division CGPA

First with Honors and

Certificate of Merit

> = 9.0

First with Honours > = 8.0 < 9.0

First > = 6.5 < 8.0

Second > = 5.0 < 6.5

• For securing degree/ diploma/ certificate in First Division with Honors and First

Division with Honors and certificate of Merit , a student shall have passed all the

courses (Theory and Practical) of the programme in the first attempt, i.e., without

ever being awarded a Re-appear or a Fail.

MAINTENANCE OF DISCIPLINE AMONG STUDENTS

• All powers relating to maintenance and enforcement of discipline in the University

and taking disciplinary action against the students and employees of the University

shall vest in the Vice-Chancellor, which he may delegate as he deems proper.

• All acts given in details in Ordinance shall amount to acts of indiscipline or

misconduct or ragging on the part of a student of the University and colleges /

institutions.

• The University Authority in the exercise of the powers, order or direct that any

student –

(a) be expelled from the University, college or institution, or

(b) be, for a stated period, rusticated or

(c) be not, for a stated period, admitted to a course or courses of study of the

University; or

(d) be imposed with the fine of a specified amount of money;

(e) be debarred from taking a University examination or examinations for one or

more years.

ACADEMIC MISCONDUCT AND USE OF UNFAIR MEANS

• Plagiarism, collusion and cheating are all forms of academic misconduct and

use of unfair means as defined in the Examination Ordinances.

• In case the student has come to examination under the influence of any

intoxicating material, misbehaves with one or more members of the

supervisory staff, it will also be treated as an act of Unfair Means and

academic misconduct.

• In relation to continuous assessment, Academic misconduct and use of Unfair

Means is classified as Major Misconduct or Minor Misconduct as described

below:

(1) Major Misconduct: Where plagiarism, collusion or cheating is detected

in Thesis, Dissertation or Major Project of a programme.

(2) Minor Misconduct: All other academic misconduct excluding

those defined in major misconduct will be regarded as a minor misconduct

and will be dealt accordingly.

• If the Unfair Means Board (UFMB) finds the student guilty, one of the following

actions may be taken:

(1) The student may be disqualified for one or more semester, or

(2) The student may be rusticated for one or more semester, or

(3) The academic programme of the student may be terminated.

(4) Any other action as deemed fit by the UMB.

RESIDUAL PROVISION

In case of any dispute/ difference of interpretation of provisions made in the Ordinances andRegulations, the decision of the Chancellor shall be final

IEC University, BaddiPROPOSED SCHEME OF EVALUATION FOR M. TECH.

in VLSI

ELECTRONICS AND COMMUNICATION DEPARTMENT

(Effective from the academic year 2013-14)

SEMESTER I

Sr.No

CourseCode

Subject Periods Evaluation Scheme Subject

Total

Credits

L T P Sessional Exam

MSE CA P Total ESE

(Theory)

1 MEC

101

Device Modelingfor CircuitSimulation

4 0 0 40 20 0 60 40 100 4

2 MEC

102

VLSI Technology&Applications

4 0 0 40 20 0 60 40 100 4

3 MEC

103

CAD of VLSI 4 0 0 40 20 0 60 40 100 4

4 Elective I 4 0 0 40 20 0 60 40 100 4

5 Elective II 4 0 0 40 20 0 60 40 100 4

Total 20

(Practical/Training/Project)

1 MEC151

ElectronicDesignAutomationLab

0 0 4 50 50 100 2

Total 22

Semester II

1 MEC201

Digital VLSIDesign

4 0 0 40 20 0 60 40 100 4

2 MEC202

Digital SignalProcessing

4 0 0 40 20 0 60 40 100 4

3 MEC203

Analog VLSIDesign

4 0 0 40 20 0 60 40 100 4

4 Elective-III 4 0 0 40 20 0 60 40 100 4

5 Elective-IV 4 0 0 40 20 0 60 40 100 4

total 20


1 MEC251

VLSI & MEMSDesign Lab

0 0 4 50 50 100 2

Total 22

Note: Grouping of batches will be done in a way that groups select either all subjects given innumerator or denominator, choice of mix of numerator and denominator is not permitted.

COMPONENTS OF EVALUATIONThe components of Evaluation for each course will be as under:

For Non-Practical Subjects:(a) Continuous A ssessment (CA), -- 20 Marks in the form of:

(i) Assignments (15 Marks)(ii) Attendance (05 Marks),

(b) Mid-Term Exams (MSE), ---------40 Marks(i) First MSE to be held after completion of 35% - 40% course

coverage,(ii) Second MSE to be held after completion of 70% - 80% course

coverage(c) End- semester Exams (ESE), ------ 40 Marks

For Practical Subjects:(a) Continuous A ssessment (CA), -- 15 Marks in the form of:

(i) Assignments (10 Marks)(ii) Attendance (05 Marks),

(b) Mid-Term Exams (MSE), ---------30 Marks(i) First MSE to be held after completion of 35% - 40% course

coverage,(ii) Second MSE to be held after completion of 70% - 80% course

coverage(c) End- semester Exams (ESE), ------ 30 Marks(d) Practical(Internal-15,External-10)---- 25 Marks

SECOND YEAR SEMESTER III

Sr.No

CourseCode

Subject Periods Evaluation Scheme Subject

Total

Credits

L T P Sessional Exam

MSE CA P Total ESE

(Theory)

1 MEC

301

RF Circuit

Design

4 0 0 40 20 0 60 40 100 4

2 MEC

302

Embedded

Systems

4 0 0 40 20 0 60 40 100 4

3 MEC

303

Self study* 40 20 0 60 40 100 4


1 MEC351

Seminar 0 0 4 2

2 MEC352

Dissertation(to be continuedin 4th Sem)

0 0 24 12

Total 26

Semester IV


1 MEC353

Dissertation(Continued)

0 0 40 20

Total 90

Self Study Course:

In the third semester there is one subject which students will study yourself. Self-study coursewill be related to the research/specialization area of a candidate. The concerned supervisorwill act as course coordinator who will be responsible for proposing the course name andsyllabus The candidate has to be continuously evaluated in same pattern as applicable to othercourses (two mid-term exams, one semester exam, assignments, quizzes, etc.).

Dissertation:

The students will finalise their thesis work with their internal guide And submit a synopsis onthe same. They would complete the Experimentation on the critical part of their thesis workand Formulate a detailed plan for their future work in the 4th semester. They would make aseminar presentation of their work on the same Which will be evaluated by the internal andexternal examiners Appointed by the university. The sessional will be awarded by periodicInternal evaluation. The students will complete their Thesis work and submit copies of theThesis report to the University as per its existing procedures. The Internal and ExternalExaminers appointed by the University will evaluate the same through a Viva-voceexamination and award Distinction / Pass / Fail to the Thesis.Seminar: For seminar Students have to prepare presentation on their topic and they have togive presentation two times in front of faculties decided by HOD .They will evaluate theperformance of students and grades accordingly.

Elective-I

MEMS & Microsensor DesignMicrowave & Optoelectronic DevicesModeling & SimulationAdvanced Computer Architecture

Elective II

Characterization of Semiconductor Materials & DevicesDigital Logic Design with HDLVLSI Interconnects

Elective III

Low Power VLSI DesignVLSI Test & TestabilityDigital Image ProcessingEmbedded System Design

Elective IV

VLSI DesignMEMS & Micro Sensor DesignNano-Electronics

DETAILED SYLLABUS

MEC 101 DEVICE MODELLING FOR CIRCUIT SIMULATION

Note: Question Paper will contain three sections of 100 marks, Section (A) iscompulsory & will contain 10 short questions each will carrying weightage of 2marks(Fill in the blanks/ True –false/ MCQ/One Word answer)

Section B will contain question no 2 and 3. Each question will have six subquestions and candidate will attempt any four questions from each questioncarrying weightage of 5 marks.)

Section C will contain question no 4 and 5. Each question will have four subquestions and candidates will attempt any two questions from each questioncarrying weightage of 10 marks.

L T P Total

3 1 0 4

Credits: 4

Unit I

FundamentalsSemiconductor Physics, Principle of circuit simulation and its objectives.Introduction to SPICEAC, DC, Transient, Noise, Temperature extra analysis.

Unit IIJunction DiodesDC, Small signal, Large signal, High frequency and noise models of diodes, Measurement ofdiode model-parameters.

Unit III

Modelling BJTDC, small signal, high frequency and noise models of bipolar junction transistors. Extractionof BJT model parameters.MOSFETsDC, small signal, high frequency and noise models of MOSFETs, MOS Capacitors. MOSModels: Level-1 and level-2 large signal MOSFET models. Introduction to BSIM models.Extraction of MOSFET model parameters.

Unit IV

Device SCALINGShort and narrow channel MOSFETs. MOSFET channel mobility model, DIBL, chargesharing and various non-linear effects.

Unit V

JFET, MESFETs & HBTsModeling of JFET & MESFET and extraction of parameters. Principles of hetro-junctiondevices, HBTs, HEMT.Text Books1. S.M.Kang & Y.Leblibici, CMOS Digital Integrated Circuits-Analysis & Design, TMH, 3rdEd.2. S.M. Sze, Physics of Semiconductor Devices, Wiley Pub.References1. Sedra and Smith, SPICE.2. H.M. Rashid, Introduction to PSPICE, PHI.3. B.G. Streetman & S. Baneerjee, Solid State Electronic Devices, PHI.4. R. Raghuram, Computer Simulation of Electronic Circuits, Wiley Eastern Ltd.5. Bar Lev, Basic Electronics.

MEC 102 VLSI TECHNOLOGY & APPLICATIONS

L T P Total

3 1 0 4

Credits: 4




Unit I

Crystal growthWafer preparation, Processing considerations, Chemical cleaning, Getting the thermal stressfactors etc.EpitaxyVapors phase epitaxy basic transport processes & reaction kinetics, Doping & Auto doping,equipments, & Safety considerations, Buried layers, Epitaxial defects, Molecular beamepitaxy, Equipment used, Film characteristics, SOI structure

. Unit II

OxidationGrowth mechanism & kinetics, Silicon oxidation model, Interface considerations, Orientationdependence of oxidation rates thin oxides, Oxides, Oxidation technique & systems dry & wetoxidation.,Masking properties of SiO2.DiffusionDiffusion from a chemical source in vapor form at high temperature, Diffusion from dopedoxide source, Diffusion from an ion implanted layer.

Unit IIILithographyOptical lithography, Optical resists, Contact & proximity printing, Projection printing,Electron lithography, resists, Mask generation, Electron optics, Roster scans & vector scans,Variable beam shape, X-ray lithography, Resists & printing, X-ray sources &masks, Ionlithography.

EtchingReactive plasma etching, AC & DC plasma excitation, Plasma properties, Chemistry &surface interactions, Feature size control & apostrophic etching, Ion enhanced & inducedetching, Properties of etch processing. Reactive ion beam etching, Specific etches processes,poly/polycide, Trench etching.

Unit IV

Simulation & Analytical TechniquesIntroduction to process modelling, SUPREM. Reliability issues in VLSI technology,Geometrical manipulations, A novel measurement technique for 2D implanted iondistributions, Introduction to partial differential equation solver, The merged multi gridmethod, Modeling & simulation of isothermal, Non isothermal and hydrodynamic devices.

Unit V

MEMSSystem-level design methodology, Equivalent Circuit representation of MEMS,Signalconditioning circuits, and sensor noise calculation. Pressure sensors with embeddedelectronics(Analog/Mixed signal), Accelerometer with transducer, Gyroscope, RF MEMSswitch with electronics, Bolometer design. RF MEMS and Optical MEMSText1. SM Sze, “Modern Semiconductor Device Physics”, John Wiley & Sons, 2000.2. SM Sze, “VLSI Technology”, John Wiley & Sons, 2000.References1. B.G. Streetman, “Solid State Electronics Devices”, Prentice Hall, 2002.2. Chen, “VLSI Technology” Wiley, March 2003.3. Circuit, Device and Process Simulation: Mathematical and Numerical Aspects byGraham F. Carey (Editor), W. B. Richardson, C. S. Reed, B. Mulvaney, John Wiley &Sons; 1 edition.4. Process and Device Simulation for MOS-VLSI Circuits, edited by P. Antognetti, D.A.Antoniadis , Robert W. Dutton, W.G. Oldham, kluwer Academic Publisher, 2000.5. Gregory T.A. Kovacs, Micromachined Transducers Sourecbook, The McGraw-Hill, Inc.19986. Stephen D. Senturia, Microsystem Design, Kluar Publishers, 20017. Nadim Maluf, An Introduction to Microelectromechanical Systems Engineering, ArtechHouse, 2000.

MEC 103 CAD of VLSI

L T P Total

3 1 0 4

Credits: 4 Note: Question Paper will contain three sections of 100 marks, Section (A) is

compulsory & will contain 10 short questions each will carrying weightage of 2marks(Fill in the blanks/ True –false/ MCQ/One Word answer)



Unit I

Introduction to Hierarchical and Structured Design,Role of CAD Tools in the VLSI design process, CAD Algorithms for switch level andcircuits simulation, Techniques and algorithms for symbolic layout, Algorithms for physicaldesign – Placement and routing Algorithms, Compaction, Circuit extraction and Testing.

Unit II

Specification of Combinational Systems Using VHDLIntroduction to VHDL, Basic language element of VHDL, Behavioral Modeling, Data flowmodeling, Structural modeling, Subprograms and overloading, VHDL description of gates.

Description and Design of Sequential CircuitsStandard combinational modules, Design of a Serial adder with accumulator, State graph forcontrol network, Design of a binary multiplier, Multiplication of a signed binary number,Design of a binary divider.

Unit IIIRegister-Transfer Level SystemsExecution graph, Organization of system, Implementation of RTL Systems, Design of RTLsystems, Analysis of RTL systems.

Data SubsystemsStorage modules, Functional modules, Data paths, Control subsystems, Micro programmedcontroller, Structure of a micro programmed controller, Micro instruction format, Microinstruction sequencing, Micro instruction Timing, Basic component of a micro system,Memory subsystem.

Unit IV

I/O SubsystemProcessors, Operation of the computer and cycle time. Binary decoder, Binary encoder,Multiplexers and demultiplexers, Floating Point arithmetic-representation of floating pointnumber, Floating point multiplication, Adders, Multipliers.

Unit V

PLA based synthesisMultilevel logic synthesis, Logic optimization, Logic simulation, Compiled and eventsimulators, Relative advantages and disadvantages, Layout Algorithms, Circuit partitioning,Placement and routing algorithms, Automatic test program generation, Combinational testing,DAlgorithm and PODEM algorithm, Scan-based testing of sequential circuits, Testabilitymeasures for circuits.

Text Books1. J. Bhaskar, “A VHDL Primer”, Addison Wesley, 1999.2. M. Ercegovac, T. Lang and L.J. Moreno, “Introduction to Digital Systems”, Wiley, 20003. C. H. Roth, “Digital System Design using VHDL”, PWS Publishing4. G. DeMicheli, “Synthesis and optimization of digital circuits”, McGraw Hill.References1. J.F. Wakerly, “Digital Design-Principles and Practices”, PHL2. Douglas Perry, “VHDL”, MGH

MEC 201 DIGITAL VLSI DESIGNL T P Total

3 1 0 4

Credits: 4




Unit IIntroductionBasic principle of MOSFETs, Introduction to large signal MOS models (long channel) fordigital design.MOS InvertersStatic and Dynamic characteristics: Inverter principle, Depletion and enhancement loadinverters, the basic CMOS inverter, transfer characteristics, logic threshold, Noise margins,and Dynamic behavior, transition time, Propagation Delay, Power Consumption.

Unit II

MOS Circuit Layout & SimulationLayout design rules, MOS device layout: Transistor layout, Inverter layout, CMOS digitalcircuits layout & simulation, Circuit Compaction; Circuit extraction and post-layoutsimulation.Combinational MOS Logic DesignStatic MOS design: Complementary MOS, Ratioed logic, Pass Transistor logic, Complexlogic circuits, DSL, DCVSL, Transmission gate logic.

Unit III

Dynamic MOS designDynamic logic families and performances.Memory DesignROM & RAM cells design

Unit IV

Sequential MOS Logic DesignStatic latches, Flip flops & Registers, Dynamic Latches & Registers, CMOS Schmitt trigger,Monostable sequential Circuits, Astable Circuits. Adders, Multilpier Circuits.

Unit V

VLSI InterconnectsInterconnect delays, Cross Talks. Introduction to low power design, Input and OutputInterface circuits.BiCMOS Logic CircuitsIntroduction, Basic BiCMOS Circuit behavior, Switching Delay in BiCMOS Logic circuits.Text Books1. Kang & Leblebigi “CMOS Digital IC Circuit Analysis & Design”- McGraw Hill, 20032. JM Rabey, “Digital Integrated Circuits Design”, Pearson Education, Second Edition, 20033. NHE Weste & K. Eshraghian, Principles of CMOS VLSI Design:A Sys.Pers., McGrawHill Pub.References1. B.G. Streetman & S. Banerjee, Solid State Electronics.2. Uyemera, CMOS Logic Circuit Design, Springer India Pvt. Ltd. New Delhi, 2007.3. Eshraghian & Pucknell, Introduction to VLSI, PHI4. David A. Hodges, Horace G. Jackson, Resve Saleh, “Analysis & Design of DigitalIntegrated Circuits”, 3rd Edi Mc Graw Hill, 2003.5. Sedra & Smith, SPICE.

ECE 601 DIGITAL SIGNAL PROCESSING

L T P Total

3 1 0 4

Credits: 4




Unit I

Discrete time signals and systemsTime Domain Representation of Signals & SystemsDiscrete Time Signals, Operations on Sequences, the sampling process, Discrete-Timesystems, Time-Domain characterization of LTI Discrete-Time systems, state-spacerepresentation of LTI Discrete-Time systems, random signals.

Unit II

Transform-Domain Representation of SignalsDiscrete-Time Fourier Transform, Discrete Fourier Transform, DFT properties, computationof the DFT of real sequences, Linear Convolution using the DFT. Z-transforms, Inverseztransform, properties of z-transformTransform-Domain Representation of LTI Systemsthe frequency response, the transfer function, types of transfer function, minimum-phase andmaximum-Phase transfer functions

Unit III

5. Digital Processing of Continuous-Time SignalsSampling of Continuous Signals, Analog Filter Design, Anti-aliasing Filter Design, Sample-andhold circuits, A/D & D/A converter, Reconstruction Filter Design.

Unit IV

6. Digital Filter StructureBlock Diagram representation, Signal Flow Graph Representation, Equivalent Structures;bone FIR Digital Filter Structures, IIR Filter Structures, State-space structure, all pass filters,tunable IIR Digital filters, cascaded Lattice realization of IIR and FIR filters, Parallel all passrealization of IIR transfer function

Unit V

7. Digital Filter DesignImpulse invariance method of IIR filter design, Bilinear Transform method of IIR FilterDesign, Design of Digital IIR notch filters, FIR filter Design based on truncated fonner sens,FIR filter design based on Frequency Sampling approach.

Text Books:1. Sanjit K. Mitra, Applications DSP a Computer based approach , TMH.2. Proakis, Digital Signal Processing, PHI, Second edition3.Allan Y. Oppenhein & Ronald W. Schater , Digital Signal Processing, PHIReferences:1. Monson H. Hayes, Schaum’s Outline of Digital Signal Processing, Mcgraw Hill, 1999.2. Lars Wanhammar, DSP Integrated Circuits, Academic Press, First edition, 1999.

MEC 203 ANALOG VLSI DESIGNL T P Total

3 1 0 4

Credits: 4




Unit I

Introduction to Analog VLSIAnalog integrated circuit design, Circuit design consideration for MOS challenges in analogcircuit design, Recent trends in analog VLSI circuits.Analog MOSFET ModellingMOS transistor, Low frequency MOSFET Models, High frequency MOSFET Models,Temperature effects in MOSFET, Noise in MOSFET.

Unit II

Current Source, Sinks and ReferencesMOS Diode/Active resistor, Simple current sinks and mirror, Basic current mirrors, Advancecurrent mirror, Current and Voltage references, Bandgap references.CMOS AmplifierPerformances matrices of amplifier circuits, Common source amplifier, Common gateamplifier, Cascode amplifier, Frequency response of amplifiers and stability of amplifier.

Unit III

CMOS Feedback AmplifierFeedback equation, Properties of negative feedback on amplifier design, Feedback Topology,Stability.CMOS Differential AmplifierDifferential signalling, source coupled pair, Current source load, Common mode rejectionratio, CMOS Differential amplifier with current mirror load,, Differential to single endedconversion.

Unit IV

CMOS Operational amplifierBlock diagram of Op-amplifier, Ideal characteristics of Op-Amplifier, Design of two stageOp- Amplifier, Compensation of Op-Amplifier, Frequency response of Op-Amplifier,Operational Transconductance Amplifier (OTA).

Unit VCMOS ComparatorCharacteristic of a comparator, Two stage open loop comparator, Special purposecomparator, Regenerative comparator, High output current amplifier, High speed comparator.Introduction to Switched Capacitor CircuitsSwitched capacitor circuits, Switched capacitor amplifiers, Switch capacitor integrators.Text Book:1. Design of Analog CMOS Integrated Circuits by Behzad Razavi McGraw Hill.2. CMOS: Circuit Design , Layout and Simulation by R. Jacob Baker, Harry W. Li, andDavid E. Boyce, Prentice Hall of IndiaReference Books

1. Analog Integrated circuit Design by David A. Johns and Ken Martin, John Wiley &Son

MEC 104 MEMS & MICRO SENSOR DESIGNL T P Total

3 1 0 4

Credits: 4




Unit I

Introduction to MEMSMEMS Fabrication Technologies, Materials and Substrates for MEMS, Processes forMicromachining, Characteristics, Sensors/Transducers, Piezoresistance Effect,Piezoelectricity, Piezoresistive Sensor.Mechanics of Beam and Diaphragm StructuresStress and Strain, Hooke's Law. Stress and Strain of Beam Structures: Stress, Strain in a BentBeam, Bending Moment and the Moment of Inertia, Displacement of Beam Structures UnderWeight, Bending of Cantilever Beam Under Weight.

Unit II

Air DampingDrag Effect of a Fluid: Viscosity of a Fluid, Viscous Flow of a Fluid, Drag Force Damping,The Effects of Air Damping on Micro-Dynamics. Squeeze-film Air Damping: Reynolds'Equations for Squeeze-film Air Damping, Damping of Perforated Thick Plates. Slide-filmAir Damping: Basic Equations for Slide-film Air Damping, Couette-flow Model, Stokes-flowModel.

Unit III

Electrostatic ActuationElectrostatic Forces, Normal Force, Tangential Force, Fringe Effects, Electrostatic Driving ofMechanical Actuators: Parallel-plate Actuator, Capacitive sensors. Step and AlternativeVoltage Driving: Step Voltage Driving, Negative Spring Effect and Vibration Frequency.

Unit IV

Thermal Effects

Temperature coeficient of resistance, Thermo-electricity, Thermocouples, Thermal andtemperature sensors.

Unit V

Applications of MEMS in RFMEMS Resonator Design Considerations, One-Port Micromechanical Resonator ModelingVertical Displacement Two-Port Microresonator Modeling, Micromechanical ResonatorLimitations.Text Books1. S.M. Sze, “Semiconductor Sensors”, John Wiley & Sons Inc., Wiley Interscience Pub.2. M.J. Usher, “Sensors and Transducers”, McMillian Hampshire.References

1. RS Muller, Howe, Senturia and Smith, “Microsensors”, IEEE Press.

MEC 105 MICROWAVE & OPTOELECTRONIC DEVICESL T P Total

3 1 0 4

Credits: 4




Unit I

Microwave Solid State DevicesMicrowave frequencies, Tunnel diode, Backward diode, MIS tunnel diode, Transferredelectron devices-Gunn diode, Avalanche transit time devices: IMPATT Diode, BARRITTDiode, and TRAPATT Diode, Microwave transistor, Microwave field effect transistor

Unit IIMicrowave Integrated CircuitIntroduction, Transmission lines for MICs, Lumped elements for MICs, Material for MICs:Substrate, Conductor, Dielectric and resistive materials, Fabrication techniques, Typicalexample of fabrication, Hybrid fabrication.

Unit III

Microwave TubesKlystron, Reflex Klystron and Magnetron, Traveling wave tubes, microwave detectiondiodes, application of microwave

Unit IV

Optoelectronic DevicesPhotovoltaic devices, Solar Radiation, PN-homojunction solar cells, Antireflection coatings,Ideal conversion efficiency, Spectral response, I-V Characteristics, Temperature and radiationeffects, Heterojunction solar cells, Schottky barrier solar cell, Thin film and amorphoussilicon solar cell, Solar arrays

Unit V

LasersStimulated emission: ruby lasers, other lasers, p-n-p-n switching devices, Switchingmechanism, Semiconductor controller rectifier, Negative conductance. Laser Diodes,Spontaneous and stimulated emission, Population inversion, Semiconductor opticalamplifiers, Optical feedback, Modes of a laser cavity, Condition for threshold, Currentdensity, Transparency current, Threshold current, Double heterostructure laser for improvedconfinement of carriers and lower threshold currents, Quantum wells for wavelength “tuning”and reduced drive currents, Factors influencing device design from infrared to blue lasers.Text Books1. S M Sze, Physics of Semiconductor Devices by, Willy Eastern Pub.2. S. Y. Liao, Microwave Devices and Circuits, PHI3. O.P. Gandhi, Microwave Engineering and Application, Maxwell Macmillan Pub.References1. J.I. Pankove, Topic in applied physics – Vol. 40 , Springer Verlag2. E. S . Yang, Microelectronic Devices, MGH3. A. G. Milness, Semiconductor Devices and Integrated Electronics, CBS Pub4. J. Wilson & J.F.B. Hawkers, Optoelectronics : An introduction, PHI

MEC 106 MODELING AND SIMULATIONL T P Total

4 0 0 4

Credits: 4




Unit IComponent model for ICsDesign rule checks, timing verification worst case delay simulation, setup and hold times forclocked devices; Behaviour modeling, structural modeling, simulation with the physicalmodel; Hardware Description Language.

Unit IIStatisticalDescription of data, Data-fitting methods, Regression analysis, Analysis of Variance,Goodness of fit.

Probability and Random ProcessesDiscrete and Continuous Distribution, Central Limit theorem, Measure of Randomness,Monte Carlo Methods.

Unit III

Stochastic ProcessesStochastic Processes and Markov Chains, Time Series Models.

Unit IVModelling and simulationConcepts, Discrete-event simulation: Event scheduling/Time advance algorithms,Verification and validation of simulation models.

Unit V

Continuous simulation: Modelling with differential equations, Example models, BondGraph Modelling, Population Dynamics Modelling, System dynamics.

Text Books1. James R., Armstrong J.R., Chip-level Modelling with VHDL., Prentice Hall, 1989.2. Navalih, Z., VHDL, Analysis and Modelling of Digital Systems, 1993.

MEC 107 ADVANCED COMPUTER ARCHITECTURE

L T P Total

4 0 0 4

Credits: 4




Unit IParallel Computer ModelsThe state of computing, Classification of parallel computers, Multiprocessors andmulticomputers, Multivector and SIMD computers.Program and Network PropertiesConditions of parallelism, Data and resource dependences, Hardware and softwareparallelism, Program partitioning and scheduling, Grain size and latency, Program flowmechanisms, Control flow versus data flow, Data flow architecture, Demand drivenmechanisms, Comparisons of flow mechanisms.

Unit II

System Interconnect ArchitecturesNetwork properties and routing, Static interconnection networks, Dynamic interconnectionnetworks, Multiprocessor system interconnects, Hierarchical bus systems, Crossbar switchand multiport memory, Multistage and combining network.

Unit III

Advanced ProcessorsAdvanced processor technology, Instruction-set architectures, CISC Scalar processors, RISCScalar processors, Superscalar processors, VLIW architectures, Vector and symbolicprocessors.

Unit IV

PipeliningLinear pipeline processor, nonlinear pipeline processor, Instruction pipeline Design,Mechanisms for instruction pipelining, Dynamic instruction scheduling, Branch Handlingtechniques, branch prediction, Arithmetic Pipeline Design, Computer arithmetic principles,Static Arithmetic pipeline, Multifunctional arithmetic pipelines.Memory Hierarchy DesignCache basics & cache performance, Reducing miss rate and miss penalty, Multilevel cachehierarchies, Main memory organizations, Design of memory hierarchies.

Unit V

Multiprocessor ArchitecturesSymmetric shared memory architectures, Distributed shared memory architectures, Models ofmemory consistency, Cache coherence protocols (MSI, MESI, MOESI), Scalable cachecoherence, Overview of directory based approaches, Design challenges of directoryprotocols, Memory based directory protocols, Cache based directory protocols, Protocoldesign tradeoffs, Synchronization.Text1. Kai Hwang, “Advanced computer architecture”, TMH.2. D. A. Patterson and J. L. Hennessey, “Computer organization and design,” MorganKaufmann, 2nd Ed.References1. J.P.Hayes, “computer Architecture and organization”, MGH.2. Harvey G.Cragon,”Memory System and Pipelined processors”; Narosa Publication.3. V.Rajaranam & C.S.R.Murthy, “Parallel computer”; PHI.4. R.K.Ghose, Rajan Moona & Phalguni Gupta, “Foundation of Parallel Processing”; NarosaPublications.

CHARACTERIZATION OF SEMICONDUCTOR MATERIALS AND DEVICESMEC 108

L T P Total

4 0 0 4





Unit IIntroductionVarious Semiconductor materials and their advantages & disadvantages applied to VLSI andNano-electronics.Properties of SemiconductorCrystal structure, Band theory, Carrier concentration at thermal equilibrium, Density ofstates, Fermi energy, Ionization of impurity in semiconductor, Quantum aspect ofsemiconductors.

Unit IISemiconductor Carrier DynamicsScattering of carrier in semiconductors, Low field effect in semiconductor, Very high fieldeffect in semiconductor, Carrier transport phenomena, Charge injection and quasiequilibrium, Generation and recombination of electron and holes and Basic equation forsemiconductor device operation.

Unit IIIMeasurement of Semiconductor PropertiesResistivity, conductivity, Band gap etcSemiconductor Junction with Metal, Insulator and SemiconductorsCharacteristics and energy band diagrams of PN Junction diodes-step and graded junction,Schottky barrier diode, Ohmic contact, Insulator-semiconductor junction.

Unit IVCompound SemiconductorClassifications; Energy band diagram; Phase diagram, Electronic properties of compoundSemiconductor materials; Microwave Devices.

Unit VApplications of Compound SemiconductorsPN Junction, Solar cells; P-I-N photodetector; Semiconductor lasers.Text Books1. S.M. Sze, “Physics of semiconductor devices”, Wiley Pub.2. B.G. Streetman, “Solid State Electronics Devices”, Prentice Hall, 2002.

RF Circuit DesignMEC 301

L T P Total

4 0 0 4





Unit I

Introduction to RF design and Wireless TechnologyDesign and applications, Complexity and choice of Technology, Basic concepts in RF design,Nonlinearly and time Variance, Intersymbol interference, Random processes and noise.Sensitivity and dynamic range, Conversion of gains and distortion.

Unit II

RF ModulationAnalog and digital modulation of RF circuits, Comparison of various techniques for powerefficiency, Coherent and non-coherent detection, Mobile RF communication and basics ofMultiple Access techniques. Receiver and Transmitter architectures, Direct conversion andtwo-step transmitters.

Unit III

RF TestingRF testing for heterodyne, Homodyne, Image reject, Direct IF and sub sampled receivers.

Unit IV

BJT and MOSFET Behavior at RF FrequenciesBJT and MOSFET behavior at RF frequencies, Modeling of the transistors and SPICE model,Noise performance and limitations of devices, Integrated parasitic elements at highfrequencies and their monolithic implementation

Unit V

RF Circuits DesignOverview of RF Filter design, Active RF components & modeling, Matching and BiasingNetworks. Basic blocks in RF systems and their VLSI implementation, Low noise Amplifierdesign in various technologies, Design of Mixers at GHz frequency range, Variousmixersworking and implementation. Oscillators- Basic topologies VCO and definition ofphase noise, Noise power and trade off. Resonator VCO designs, Quadrature and singlesideband generators. Radio frequency Synthesizers- PLLS, Various RF synthesizerarchitectures and frequency dividers, Power Amplifier design, Liberalization techniques,Design issues in integrated RF filters.Text Books1. Thomas H. Lee, Design of CMOS RF Integrated Circuits, Cambridge University press1998.References1. B. Razavi, RF Microelectronics, PHI 19982. R. Jacob Baker, H.W. Li, D.E. Boyce, CMOS Circuit Design, layout and Simulation,PHI, 1998

2. Y.P. Tsividis, Mixed Analog and Digital Devices and Technology, TMH, 1996

MEC 109 DIGITAL LOGIC DESIGN WITH HDLL T P Total

4 0 0 4





Unit I

Introduction to logic circuits:Variables and functions, Synthesis using AND, OR and NOT gates, Introduction to CADtools, Introduction to HDL(VHDL/Verilog)

Unit II

Implementation Technology:Transistor switches, CMOS Logic, PLD, Transmission gates

Unit III

Optimized Implementation of Logic Functions:Strategy for minimization, minimization of POS, Multiple Output circuits, Analysis ofMultilevel Circuits

Unit IV

Number Representation and Arithmetic Circuits:Positional Number representation, Addition of unsigned numbers, signed Numbers, Fastadders, Design of arithmetic circuits using CAD tools, Multiplication

Unit V

Combinational Circuit Building blocks:Multiplexers, Decoder, Encoder, Code Converters, Arithmetic Comparison circuits,Verilog for combinational circuits , Design of Sequential design, Design AsynchronousSequential DesignText Books1. Fundamental of digital Logic with Verilog design by S. Brown & Z. Vransesic, TMH.2. A VHDL Primer by J. Bhaskar, Addison Wesley.

MEC 110 VLSI INTERCONNECTSL T P Total

4 0 0 4





Unit I

InterconnectsInterconnect Parameters: Resistance, Inductance, and Capacitance, Interconnect RC Delays:Elmore Delay Calculation. Interconnect Models: The lumped RC Model, the distributed RCModel, the transmission line model. SPICE Wire Models: Distributed RC lines in SPICE,Transmission line models in SPICE.Scaling issues in interconnectsGate and Interconnect Delay

Unit II

CMOS RepeaterThe Static Behavior- Switching Threshold, Noise Margins, The Dynamic Behavior-Computing the capacitances, Propagation Delay: First order Analysis, Propagation Delayfrom a Design perspective, Power, energy and Energy-Delay- Dynamic Power Consumption,Static Consumption, Analyzing Power Consumption using SPICE

Unit III

Repeater Design: Driving Interconnects for Optimum speed and powerShort channel model of CMOS Repeater - Transient Analysis of an RC loaded CMOSrepeater, Delay Analysis, Analytical power expressions: Dynamic power, Short circuitPower, Resistive Power Dissipation, CMOS Repeater insertion: Analytical expressions fordelay and power of a repeater chain driving an RC load.

Unit IV

Advanced Interconnect TechniquesReduced-swing Circuits, Current-mode Transmission Techniques

Unit VCrosstalkTheoretical basis and circuit level modeling of crosstalk, Energy dissipation due to crosstalk:Model for energy calculation of two coupled lines. Contribution of driver and interconnect todissipated energy, Crosstalk effects in logic VLSI circuits: Static circuits, Dynamic circuitsand various remedies.

Text Books1. Jan M. Rabaey, Analysis and Design of Digital Integrated Circuits– A designPerspective, TMH, 2nd Edition 2003.2. F.Moll, M.Roca, Interconnection Noise in VLSI Circuits, Kluwer Academic Publishers.

Reference Books:1.John P. Uymera, Introduction to VLSI Circuits and Systems, Wiley Student Edition.2. S.M. Kang, L. Yusuf, CMOS Digital Integrated Circuits-Analysis and Design TMH, 3rdEdition.

MEC 204 LOW POWER VLSI DESIGNL T P Total

4 0 0 4





Unit I

IntroductionNeed for low power VLSI chips, Sources of power dissipation in Digital Integrated circuits.Emerging low power approaches. Physics of power dissipation in CMOS devices.Device & Technology Impact on Low PowerDynamic dissipation in CMOS, Transistor sizing & gate oxide thickness, Impact oftechnology Scaling, Technology & Device innovation.

Unit II

Power EstimationSimulation Power analysis- SPICE circuit simulators, Gate level logic simulation, Capacitivepower estimation, Static state power, Gate level capacitance estimation, Architecture levelanalysis, Data correlation analysis in DSP systems. Monte Carlo simulation. Probabilisticpower analysis- Random logic signals, Probability & frequency, Probabilisticpower analysis techniques.

Unit III

Low Power DesignCircuit level- Power consumption in circuits, Flip Flops & Latches design, High capacitancenodes, Low power digital cells library Logic level- Gate reorganization, Signal gating, Logicencoding, State machine encoding, Precomputation logic

Unit IV

Low Power Architecture & SystemsPower & performance management, Switching activity reduction, Parallel architecture withvoltage reduction, Flow graph transformation, Low power arithmetic components, Lowpower memory design.

Unit V

Low Power Clock Distribution: Power dissipation in clock distribution, single driver vsdistributed buffers, zero skew vs tolerable skew, chip & package co design of clock networkAlgorithm & Architectural Level Methodologies: Introduction, design flow, algorithmiclevel analysis & optimization, architectural level estimation & synthesis.Text Books1. Gary K. Yeap, Practical Low Power Digital VLSI Design, KAP, 20022. Rabaey and Pedram, Low power design methodologies, Kluwer Academic,1997References1. Kaushik Roy, Sharat Prasad, Low-Power CMOS VLSI Circuit Design, Wiley,2000

MEC 205 VLSI TEST & TESTABILITYL T P Total

4 0 0 4





Unit I

Motivation for TestingDesign for testability, The problems of digital and analog testing, Design for test, Softwaretesting.Faults in Digital CircuitsGeneral introduction, Controllability and Observability, Fault models - stuck-at faults,Bridging faults, Intermittent faults.

Unit II

Digital Test Pattern GenerationTest pattern generation for combinational logic circuits, Manual test pattern generation,Automatic test pattern generation - Roth's D-algorithm, Developments following Roth'sDalgorithm, Pseudorandom test pattern generation, Test pattern generation for sequentialcircuits , Exhaustive, non-exhaustive and pseudorandom 70 test pattern Generation, Delayfault testing .

Unit III

Signatures and Self TestInput compression output compression arithmetic, Reed-Muller and spectral coefficients,Arithmetic and Reed-Muller coefficients ,Spectral coefficients, Coefficient test signatures,Signature analysis and online self test .

Unit IV

Testability TechniquesPartitioning and ad-hoc methods and scan-path testing , Boundary scan and IEEE standard1149.1, Offline built in Self Test (BIST), Hardware description languages and test .

Unit V

Testing of Analog and Digital circuitsTesting techniques for Filters, A/D Converters, RAM, Programmable logic devices and DSP,Test generation algorithyms for combinational logic circuits – fault table, Boolean difference,Path sensitilization, D-algorithm, Podem, Fault simulation techniques – serial single faultpropogation, Deductive, Parallel and concurrent simulation, Test generation for a sequentiallogic, Design for testability – adhoc and structured methods, Scan design, Partial scan,Boundary scan, Pseudo-random techniques for test vector generation and responsecompression, Built –in- Self- test, PLA test and DFT.Text Books1. M. Abramovici , M.A Breuer and A.D. Friendman, Digital systems and Testing andTestable Design, Computer Science Press 1990.2. Stanley L. Hurst, VLSI Testing: digital and mixed analogue digital techniquesPub: Inspec / IEE, 1999

MEC 206 DIGITAL IMAGE PROCESSING

L T P Total

4 0 0 4





Unit I

IntroductionSteps in Digital Image Processing, Components of an Image Processing system, Applications.Human Eye and Image Formation; Sampling and Quantization, Basic Relationship amongpixels- neighbour, connectivity, regions, boundaries, distance measures.

Unit II

Image EnhancementSpatial Domain-Gray Level transformations, Histogram, Arithmetic/Logical Operations,Spatial filtering, Smoothing & Sharpening Spatial Filters; Frequency Domain- 2-D Fouriertransform, Smoothing and Sharpening Frequency Domain Filtering; Convolution andCorrelation Theorems;

Unit III

Image RestorationInverse filtering, Wiener filtering; Wavelets- Discrete and Continuous Wavelet Transform,Wavelet Transform in 2-D;Image CompressionRedundancies- Coding, Interpixel, Psycho visual; Fidelity, Source and Channel Encoding,Elements of Information Theory; Loss Less and Lossy Compression; Run length coding,Differential encoding, DCT, Vector quantization, entropy coding, LZW coding; ImageCompression Standards-JPEG, JPEG 2000, MPEG; Video compression;

Unit IV

Image SegmentationDiscontinuities, Edge Linking and boundary detection, Thresholding, Region BasedSegmentation, Watersheds; Introduction to morphological operations; binarymorphologyerosion, dilation, opening and closing operations, applications; basic gray-scalemorphology operations; Feature extraction; Classification; Object recognition.

Unit V

Pattern recognitionIntroduction to pattern recognition, Pattern Recognition Methods, Pattern RecognitionSystem Design, Statistical Pattern recognition – Classification, Principle, Classifier learning,Neural networks for pattern classification.Text Books1. Fundamentals of Digital Image processing- A. K. Jain, Pearson Education2. Digital Image Processing- R. C. Gonzalez and R. E. Woods, Pearson Education3. Digital Image Processing using MATLAB- R. C. Gonzalez , R. E. Woods and S. L Eddins,Pearson Education

MEC 302 EMBEDDED SYSTEM DESIGNL T P Total

4 0 0 4





Unit IMicrocontrollerMicroprocessors vs. Microcontrollers, MCS-51 Family Overview, Important Features,Architecture. 8051 Pin Functions, Architecture, Addressing Modes, Instruction Set,Instruction types, Interrupts.

Unit IIEmbedded Systems:Background and History of Embedded Systems, Definition and Classification, Programminglanguages for embedded systems: desirable characteristics of programming languages forembedded systems, Low-level versus high-level languages, Main language implementationissues: control, Typing. Major programming languages for embedded systems. EmbeddedSystems on a Chip (SoC) and the use of VLSI designed circuits.

Unit IIIReal Time Operating Systems (RTOS):Architecture of an RTOS, Important features of VxWorks and Montavista Linux, EmbeddedSystems Programming, Locks and Semaphores, Operating System Timers and Interrupts,Exceptions, Tasks: Introduction, Defining a task, Task states and scheduling, Task structures,Synchronization, Communication and concurrency, Kernel objects: Semaphores, Queues,Pipes, Event registers, Signals, And condition variables. Real-time clock and system clock,Programmable interval timers, Timer ISRs, Timing wheels, Soft timers.

Unit IV32-Bit RISC Based ARM Architecture:Important features, Instruction set, Programming Examples, Core based Embedded Systems,Soft and Hard Cores, Xilinx FPGA architectures, 8-bit Picoblaze Microcontroller Core, 32-bitMicroblaze Soft Core, Power PC

Text Books1. Mckenzie, Scott, The 8051 Microcontroller, PHIs, (1995) 5th ed.2. Simon, David E., An Embedded System Primer, Pearson Education, (2005) 4th ed.3. K.V.K.K.Prasad, Embedded/Real-time Systems: Concepts, Design and Programming –Dreamtech press.

MEC 207 VLSI DESIGNL T P Total

4 0 0 4





Unit IIntroductionBasic principle of MOSFETs, Introduction MOS models for digital design.MOS InvertersStatic and Dynamic characteristics: Inverter principle, Depletion and enhancement loadinverters, the basic CMOS inverter, transfer characteristics, logic threshold, Noise margins,and Dynamic behavior, transition time, Propagation Delay, Power Consumption.

Unit IIMOS Circuit Layout & SimulationLayout design rules, MOS device layout: Transistor layout, Inverter layout, CMOS digitalcircuits layout & simulation, Circuit Compaction; Circuit extraction and post-layoutsimulation.

Unit IIICombinational MOS Logic DesignStatic MOS design, Complementary MOS, Ratioed logic, Pass Transistor logic, Complexlogic circuits, Transmission gate logic, Adders.

Unit IVDynamic MOS designDynamic logic families and their performance.Sequential MOS Logic DesignStatic latches, Flip flops & Registers, Dynamic Latches & Registers, CMOS Schmitt trigger,Monostable sequential Circuits, Astable Circuits, ROM & RAM cells design

Unit V MOS AmplifierPerformances metrices of amplifier circuits, Common source amplifier, Cascode amplifier,Frequency response of amplifiers and stability.

Text Books1. Kang & Leblebici “CMOS Digital IC Circuit Analysis & Design”- McGraw Hill, 20032. J.M. Rabaey, “Digital Integrated Circuits Design”, Pearson Education, Second Edition,2003References3. B.G. Streetman & S. Banerjee, Solid State Electronics.4. Uyemera, CMOS Logic Circuit Design, Springer India Pvt. Ltd. New Delhi, 2007

MEC 208 MEMS & Microsensor DesignL T P Total

4 0 0 4





Unit IIntroduction to MEMSMEMS Fabrication Technologies, Materials and Substrates for MEMS, Processes forMicromachining, Characteristics, Sensors/Transducers, Piezoresistance Effect,Piezoelectricity, Piezoresistive Sensor.

Unit IIMechanics of Beam and Diaphragm StructuresStress and Strain, Hooke's Law. Stress and Strain of Beam Structures: Stress, Strain in a BentBeam, Bending Moment and the Moment of Inertia, Displacement of Beam Structures UnderWeight, Bending of Cantilever Beam Under Weight.

Unit IIIAir DampingDrag Effect of a Fluid: Viscosity of a Fluid, Viscous Flow of a Fluid, Drag Force Damping,The Effects of Air Damping on Micro-Dynamics. Squeeze-film Air Damping: Reynolds'Equations for Squeeze-film Air Damping, Damping of Perforated Thick Plates. Slide-filmAir Damping: Basic Equations for Slide-film Air Damping, Couette-flow Model, Stokes-flowModel.

Unit IVElectrostatic ActuationElectrostatic Forces, Normal Force, Tangential Force, Fringe Effects, Electrostatic Driving ofMechanical Actuators: Parallel-plate Actuator, Capacitive sensors. Step and AlternativeVoltage Driving: Step Voltage Driving, Negative Spring Effect and Vibration Frequency.Thermal EffectsTemperature coeficient of resistance, Thermo-electricity, Thermocouples, Thermal andtemperature sensors.

Unit VApplications of MEMS in RFMEMS Resonator Design Considerations, One-Port Micromechanical Resonator ModelingVertical Displacement Two-Port Microresonator Modeling, Micromechanical ResonatorLimitations.Text Books1. S.M. Sze, “Semiconductor Sensors”, John Wiley & Sons Inc., Wiley Interscience Pub.2. M.J. Usher, “Sensors and Transducers”, McMillian Hampshire.

MEC-209 NANO-ELECTRONICSL T P Total

3 1 0 4

Credits: 4




Unit IIntroduction of Nano-electronicsThe “Top-Down” Approach; The “Bottom-Up” Approach; Why Nano-electronics;Nanotechnology Potential; MOS Scaling theory-Issues in scaling MOS transistors; Shortchannel effects; Requirements for non-classical MOS transistor; Metal gate transistor-Motivation, requirements, Integration Issues; High-k gate based MOSFETMotivation,requirements, integration issues of high-k.

Unit IIQuantum Mechanics of ElectronsGeneral postulates of quantum mechanics; Time-independent Schrodinger’s equation-boundary conditions on the Wave function; Analogies between quantum mechanics andclassical electromagnetic; probabilistic current density;Multiple particle systems; Spin and angular Momentum.

Unit IIIFree and Confined ElectronsFree Electrons; Free electron gas theory of metals; Electrons confined to a bounded region ofspace and quantum numbers; Partially confined electrons- finite potential wells; Quantumwells; Quantum wires; Quantum dots.Tunnel Junctions and Applications of TunnelingTunneling through a potential barrier; Potential energy profiles for material interfaces;Applications of tunneling; Coulomb blockade, Single-Electron Transistor (SET).

Unit IVGermanium Nano MOSFETsStrain, Quantization; Advantages of germanium over silicon; PMOS versus NMOS;Compound semiconductors - material properties; MESFETs; Compound semiconductorsMOSFETs in the context of channel quantization and strain; Hetero structure MOSFETsexploiting novel materials, strain, quantization.

Unit V

Non-Conventional MOSFET StructuresSOI-PDSOI and FDSOI; Ultrathin body SOI-double gate transistors, integration issues;Vertical transistors – FinFET and Surround gate FET; Carbon Nano-tube Transistors (CNT);Semiconductor Nano-wire FETs and SETs; Molecular SETs and Molecular Electronics.Text Books1. Fundamentals of Modern VLSI Devices, Y. Taur and T Ning, Cambridge University Press.2. Fundamental of Nanoelectronics, George W. Hanson Pearson Education.References1. Silicon VLSI Technology, Plummer, Deal, Griffin, Pearson Education India.2. Encyclopedia of Materials Characterization, Edited by Brundle, C.Richard; Evans,Charles A. Jr.; Wilson, Shaun ; Elsevier.

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