mark raymond - 28/04/061 trip-t and tfb status trip-t schematics trip-t operation at t2k sipm...

Mark Raymond - 28/04/06 1

Trip-t and TFB status

Trip-tschematicsTrip-t operation at T2KSiPM connection and gain considerationsLatest results from version 2 – the final version

TFBconceptual layoutinterfacescomponentselectronic calibrationdata volumes

plans for this year


Trip-t schematics - overview

SKIPB

PROG_IN

PROG_CTRL

PROG_RESET

PROG_CLOCK

PROG_OUT

Q_TEST [0:32]

Q_IN [0:32]

DACOUT

ProgInterface

Front End

A-Pipeline48 x 32 chan

t-Pipeline48 x 32 chan

Dummy OUT [33]

AnalogMUX

AnalogMUX

MUX_CLK

MUX_RESET

DISCRIM [0:31]

DIG_EN_U

DIG_RESET

DIG_EN_L

DigitalMUX

A OUT

t OUT

DISC_OUT[0:15]

taken from Bench test of TRIP-t, Leo Bellantoni, Paul Rubinov, D0 note ##v4

select which group of 16 to outputreset during preamp reset period

trigger pipeline column prior to readout

not used

mux controlsignals

programminginterface

serial analogue output

32 inputs

not used


Trip-t schematics – front end

Q_IN

A OUTPUT

200fF

IBP

1.0 pF

3.0 pF

GAIN[3]

RESET

Z

IFF

IBOPAMP

GAIN[2]

160fF

GAIN[1]

80fF

GAIN[0] 40fF

40fF

+

-

IBOPAMP

V_REF

IFFP2

+

-

IBOPAMP

V_REF

IFFP2

x10

+

-

IB_T

IBCOMP

DISCRIM_OUT

V_TH

PLN_CLK

t OUTPUT

80fF

+

-

taken from Bench test of TRIP-t, Leo Bellantoni, Paul Rubinov, D0 note ##v4

don’t use

x10

set to zero to avoid linearity discontinuity

not used

preamp

disc.thresh

to pipeline


The proposed mode of Trip-t operation for beam spill data acquisition is as follows

during spillintegrate signal for each bunch and store result in pipeline* (15 timeslices for 15 bunches)timestamp high gain channel discriminator outputs that fire and store

after spillcontinue running in same way, for a while, to catch late signals ( decay)readout entire contents of pipelineassemble data block containing hit timestamps and all digitized analogue data and transmit

transmitting all info in this way allows histogramming of single p.e. events to monitor SiPM gainvast majority of data is pedestal + single/double p.e. hits only

Trip-t operation at T2K

5.25 sspill period

2.8 safter spill

active period

74 s (23 cell) readout period(if O/P mux running at 10 MHz)

start of spill end of spill

at this time trip-t switchesto inter-spill operational mode

(cosmic trigger)

*Note: pipeline operated using 2 timeslices/preamp integration period to avoid FIFO overflowproblem, so pipeline length reduced to 24 (explained in http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/FIFOtalk_1_3_06)


SiPM connection

HV(TFB)

1 M

50

thin coax

SiPM

trip-t

100pF

10pF

short length (~20 cm) coax between SiPM and triptSiPM connected between core and coax sheath (core carries bias voltage)50 provides some kind of termination for the cablecharge split between two tript channels using different capacitor values to get high/low gain

330pFHVtrim


Gain considerations

don’t know what final SiPM gain will be, but assume production devices will be quite well matched

in any case will have individual channel gain adjustment by HVtrimDACs

Signal shared between Cadd, Chi and Clo (also some strays)

Choose Cadd to match final SiPM gain (330pF about right for 5x105)Cadd also helps with gain discontinuity when hi gain channel saturates(see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/tript_talk_1_3_06)

HV(TFB)

1 M

50

thin coax

SiPM

trip-tChi100pF

Clo10pF

Cadd330pF

HVtrim


Gain ratio considerations

aim for fullscale signal capability (logain channel) of 500 p.e. (e.g. 40 pC for 5x105 SiPM gain)

let’s assume want discriminator threshold adjustment range 0 – 5 p.e.trade-off between range and threshold adjustment precision here

(see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/tript_talk_1_3_06)fixed x10 gain stage between preamp and comparator means higain fullscale ~ 50 p.e.

so hi:lo gain ratio 10:1

x10

1pF

resetVth

disc. O/P

analoguepipeline

Qin

HV(TFB)

1 M

50

thin coax

SiPM

trip-tChi100pF

Clo10pF

Cadd330pF

HVtrim


Latest Trip-t test results from final version

Trip-t

ProgrammableDigital PatternGenerator

~14 control linespreamp int./resetpipeline, multiplexer,programming

Qinj

ADC

Scope

LabVIEW

VMEck and trig.

level shiftdECL ->

2.5V CMOS

prog.attenuator


Photos

Trip-t board

dECL -> 2.5 V CMOSlevel shift

digital pattern generatordECL outputs

ADC


Tript V1 v. V2 linearity

10.5x103

10.0

9.5

9.0

8.5

AD

C u

nits

543210

Qin [pC]

12

11

10

9

x103

version 1 version 2

Trip-t V1/V2 linearity comparisonversion 2 linearity better but stillsome gain reduction for smallsignals

=> will need calibration


Tript V2 linearity

4000

3000

2000

1000

0

AD

C u

nits

403020100

total external charge injected [pC]

all 16 channels, hi and lo gains

component values as on p. 6/7

lo gain saturates at ~ 40 pC

hi gain saturates at ~ 4 pC


Tript V2 linearity

10

2

3

4

5

678

100

2

3

4

5

678

1000

2

3

4

AD

C u

nits

5 6 7 80.1

2 3 4 5 6 7 81

2 3 4 5 6 7 810

2 3 4


log-log plot of same data

10:1 gain ratio means gain rangechange occurs where logain signalsize already large so no S/N problems


Tript V2 discriminator measurement

1000

800

600

400

200

0

# of

tim

es

disc

. fir

es

0.400.350.300.250.200.150.100.050.00


count the no. of times the discriminator firesfor 1000 preamp integration periodssweep the injected signal size

for 5x105 1p.e. -> 0.08 pC

pk-pk width ~ 1 p.e. also for this measurment

so +/- 0.5 p.e. precision

can improve but trade-off with adjustment range

1 p.e.

discriminator curves for all 16 higain channels


Tript V2 discriminator timewalk

355

350

345

340

335

330

325

aver

age

disc

rimin

ator

firi

ng t

ime

[nse

c]

2.01.51.00.50.0

overall injected charge [pC]

ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15

1 p.e. = 80 fC

large timewalk and chan-to-chan spread forsmall signals

OK for signals > ~ 3 p.e.

could improve but once againtrade-off with discriminatoradjustment range


SiPM/tript version 2 results

Russian SiPM (CPTA – 600 pixels) 39 V bias

led pulsed duringpreamp integrate period-> red distribution

preamp integrate:reset ratio 325ns:75ns

get blue distribution when ledswitched off -> can see 1 and 2 p.e.peaks

3000

2000

1000

0

cou

nts

90008900880087008600850084008300820081008000

ADC units

2000

1500

1000

500

0

higain channel


HVtrim

cal dac

HVtrim

HVtrim

HVtrim

HVtrim

HVtrim

HVtrim

HVtrim

cal dac16

x S

iPM

con

nect

ors

16 x

SiP

M c

onne

ctor

s16

x S

iPM

con

nect

ors

16 x

SiP

M c

onne

ctor

s

powerFE-FPGA

local supplyand T monito-

ring

DAQI/F

trip-t trip-t

trip-ttrip-t

ADC

ADC

TFB – Trip-t Front end Board

picture shows conceptual layout ofmain components

real layout only just beginning onanalogue front end interface need to keep component density high here and take care of signals

propose to use ultra-min. coax connectors SiPM connection needs thought

this picture is conceptual – reality will bedifferent – but we need to decide whatthe reality should be in the near future

need to consider cable routing, how connections can be made, cooling …

aiming for 10 cm x 15 cm


Trip-t pinout

128 pin 14 x 14 mm2

QFP

analog I/Psdigital disc O/Psdigital control I/Psanalog test I/Panalog bias (dec.)analog O/Ptest I/P only+2.5Vgndnot used


Trip-t control signals

Programming interface and O/P mux controlPrgReset resets programming interfacePrgCtrl defines whether programming the chip or running the output MUXPrgIn serial programming info or MUX reset (depending on PrgCtrl)PrgOut serial output to read back programmed register valuesPrgClk shift in serial programming data or MUX clock (depending on PrgCtrl)

Pipeline control and triggeringPlnReset Resets the pipelinePlnClk Pipeline clock SkipB Triggers the pipeline (stops timeslice of interest being overwritten)PR1 Initiates pipeline readout (validated by PlnClk edge)MoveData Clears triggered pipeline column (allows timeslice to be overwritten – validated

by PlnClk edge)

Preamp integrate/reset cyclingPreReset Switches preamplifiers between integrate/resetPre2aReset complement of PreResetPre2bReset complement of PreReset

Discriminator outputs enable and resetDigenL enables one bank of 16 discriminator outputs off-chip (fixed level)DigenU enables the other bank (fixed level)DigResetB resets the discriminators (do this during preamp reset period)

some dualfunctionality

here

14 – 16 control lines depending on whether we fix DigenL/DigenU or leave programmable


Trip-t registers

serial programming interface

chip ID: 01010register address: 5 bitsoperation: 3 bits (read/write/set/reset/default)1 bit spacevalue: 8/10/34 bits

~ 300 bits to send to fullyprogram chip

so for 50k channels, ~3000 trip-t’sneed ~ 900k bits (not that much)

initialising the system from scratchwill not take any significant time


ADCD0 uses AD9201 – seems suitable for us too

dual channel, 20 MHz, 10-bit, single supply (2.7 V min.)parallel O/P but 2 channels data multiplexed onto single 10-bit bus215 mW (+3V supply)

HVtrimDACpropose AD5308

8 channel (2/trip-t), buffered outputs, single supply (2.5V min.)serial load8 bits res’n (could use 10 or 12 bit versions)

ADC and HVtrimDAC

propose to prototype the use of these chips in conjunction with trip-t test board before committing to TFB layout


TRIP-T16 SiPM’s

16 disc.O/P’s

14 control

4 cal lines

HVtrim 4 HVtrim control (2 HVtrimDACs)

10 bits

2 ADC control

TRIP-T16 SiPM’s

16 disc.O/P’s

14 control

4 cal lines

HVtrim

FE-FPGA digital IO per pair of Trip-T’s

((4+16+14+4)x2) + 12 = 88

assuming all control lines independent(some could be shared between trip-t’s but would lead to more complicated pcb track routing)

4 Trip-t’s per TFB => 176 total

more lines required for: local T and supply voltage monitoring cal level generation off-board communication …..

4 HVtrim control (2 HVtrimDACs)

TFB Trip-t I/O


propose something like

electronic chain calibration

Vcal(need another

DAC here)

to 16 trip-t SiPM channelsbefore gain splitting capacitorsevery 4th channel

from FE-FPGA

needs to be prototyped – provision to do this included on trip-t test board


TFB interfaces

4 LVDS pairsClocks input: 100 MHz, 1Hz, Spill/Cosmic triggerData input programming setup (trip-t, HVtrim, CAL levels)Data output read back, spill data, cosmic trigger out, monitoring data, …RF clock synchronization to beam

PowerSiPM HV+2.5 (tript, HVtrimDACs and FPGA)+3.3 (ADC, FPGA)other levels may be necessary?


for programmingtript: ~ 900 kbits for 50k channels HVtrim DACs: 8 bits res’n x 50k chans = 400 kbits

for raw spill data readout (data only)assume 23 integration periods

4 tript’s / TFB32 channels/tript (hi and logain)10 bit ADC

=> ~30k bits /TFB /spill

+ hit timestamp data and associated hit channel addresses

some data volume numbers


Clock and trigger recovery and synchronization - 100 MHz / RF clock / spill trigger / cosmic trigger Tript register programming

SiPM HV-trim - individual HV trim DACs on all SiPM channels need programming Tript and ADC operation sequencing during spill - digital control signals for integrate/reset, pipeline write cycling, pipeline read, output mux cycling and ADC control and readout Hit timestamping (linked to above) - timestamp tript discriminator outputs to 2.5 ns precision Data formatting and transmission - bundle up timestamp information and digitized analogue data into agreed fromat and transmit Cosmic trigger formation - during spill gaps (~ 3 secs) need to cycle chip, look for patterns of discriminator hits from neighbouring channels, transmit trigger off-board, respond with data if trigger returned

local monitoring – temperature, local voltage levels electronic calibration – outside normal physics data taking

TFB FE-FPGA tasks


plans for this year

complete tests with trip-t test boardcalibration cctADCHVtrimDAC

other things to definewhat to monitor locally and how to implement it

1st TFB prototype to be produced by October

in parallel produce firmware to implement main functionality

detailed electrical characterization by end of year

mark raymond - 28/04/061 trip-t and tfb status trip-t schematics trip-t operation at t2k sipm...

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