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Marie: Control for a Simple ComputerJames Gil de LamadridBowie State University
IntroductionThis addendum is based on the Marie computer architecture presented by Null andLobur1. It expands on Chapter 4, describing the control circuitry necessary to implementthe simplest version of the computer. In Chapter 4, the data path of Marie is described inSection 4.2, using a standard bus connection for a set of registers. The reader shouldfamiliarize themselves with this material before preceding. The register set issummarized as follows:
AC: the accumulator.
MAR: the memory address register.
MBR: the memory buffer register.
PC: the program counter.
IR: the instruction register.
InREG: the input registers.
OutREG: the output register
In Section 4.2 a description of the machine instruction set archetecture (ISA) is also given. The register transfer language (RTL) instructions are also given, for each machineinstruction. This information is summarized in Table 1.
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MachineInstruction
RTL Instruction
Load X MAR XMAR M[MAR]AC MBR
Store X MAR XMBR ACM[MAR] MBR
Add X MAR XMBR M[MAR]AC AC + MBR
Subt X MAR XMBR M[MAR]AC AC MBR
Input AC InREG
Output OutREG AC
Halt
Skipcond If IR1110 = 00 and AC < 0 or IR1110 = 01 and AC = 0 or IR1110 = 10 and AC > 0 then PC PC + 1
Jump X PC XTable 1. Machine and RTL Instructions.
In Section 4.3 is more information the reader should familiarize themselves with. Adiscussion is presented on the fetch and decode cycle. The RTL instructions to do thefetch and decode are summarized below.
MAR PC
IR M[MAR], PC PC + 1
MAR IR[110], Decode(IR[1215])
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if operand fetch required then MBR M[MAR]
Section 4.3 also contains information on interrupts and asynchronous I/O. In ourdiscussion we will ignore the intricacies of interrupt driven I/O, in the interest of keepingthe discussion simple.
Finally, a discussion on hardwire and microprogrammed control is presented in Section4.7. The reader should review this material to ensure that they understand the basicconcepts and differences in these two control strategies.
Hardwired Control
With hardwire control, a combinational circuit, called the control unit, produces controlsignals for the bus and registers. Section 4.7 discusses the hardwire control unit briefly,and Figure 4.14 presents a rough diagram of the control unit. In Figure 1. you will find amore thorough diagram of the control unit.
IR11-10
IR15-12
AC
IR
Control SignalsCU
C
Comp
Dec
Dec
Dec
N,Z,P
F2-0
D9-0
T6-0
3
16
Figure 1. Hardwire control unit.
The control unit takes inputs from the IR, the AC, and a new register called C. Theinputs from the IR are run through two decoders. The operation decoder decodes the opcode of the instruction producing output lines D90. Each of these lines are asserted whenan instruction with a corresponding opcode is being executed. For example, D3 wouldbe asserted only if the instruction with opcode 3 (Add) were being executed.
The function decoder is used to decipher the comparison being performed for theSkipcond instruction. Its inputs are bits 10 and 11 of the address field, and its output arelines F20, corresponding to the comparison being performed. For example, if the
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comparison bits are 01, indicating skip if zero, F1 would be asserted.
The AC is fed into a comparator, which produces three output lines: N, Z, and P. Thesebits are status bits indicating that the contents of the AC are negative, zero, or positive,respectively. This comparator circuit is a combinational circuit, shown in Figure 2. InFigure 2, the values of N and P are determined directly from the sign bit. The value of Zis the output of a NOR gate which is asserted only if all bits of the AC are zero.
P
Z
NAC
15
AC16
Figure 2. Comparator circuit and status flags.
A last decoder in Figure 1. is the timing decoder. The timing decoder is connected to aregister, called C. This register, which is more accurately called a counter, is used as asequence register. A threebit register, each new clock cycle it produced the next countin the sequence between 0 and 6. This count is run through the timing decoder anddecoded into timing lines T60. These timing lines are used to break an instruction intosteps. There are possibly 7 steps (0 – 6) to an instruction, and the timing lines indicate tothe control unit which step is currently being performed.
Registers, Memory, ALU, and Bus
In Figure 4.9 the bus architecture of the Marie system is shown. This diagram leaves outmany of the details with which we must concern ourselves. Part of this figure is redrawnin Figure 3, which shows the PC, the memory unit, and their bus connections.
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INLD
3S
MUX
PC
CL
16 16PC
Wt
Memory
Figure 3. Bus architecture of Marie.
Each register is really a counter with operations load (LD), increment (IN), and clear(CL). Corresponding control lines, when asserted, accomplish these tasks. The memoryunit has a write (Wt) control line, that is asserted to perform a write operation. The bus isa communication line, implemented as a multiplexer. Each device on the bus has anaddress (its MUX selection number). The MUX selector lines (S) are used to select theinput device to the bus. The output of the bus is connected to the input of each of thedevices on the bus.
The ALU is similar to the ALU designed in Section 3.5.2. Figure 4. is an abstractdrawing of the ALU. It has two inputs, A and B, an output, C, and a control input, G,which specifies the operation being performed.
16
G
CB
AALU
1616
Figure 4. Pinout diagram of the ALU.
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The ALU performs a different operation, depending on the value of G. Table 2 showsthe operations, and their corresponding function codes.
G Operation
0 C A + B
1 C A BTable 2. ALU operation.
The connections to the AC from Figure 4.9 of the text require a little closer examination.These connections are shown in Figure 5. The MBR has standard connections to andfrom the bus. The AC has a standard connection to the bus, but its input comes from amultiplexer. The multiplexer chooses between Option 0, which is the results of the ALU,and Option 1, which is the contents of the bus. The multiplexer makes its selection basedon the control line SL(AC)
1
0
SL(AC) G bus
MUX AC
MBR
ALU
16
16
16
16
1616
Figure 5. Connections to the AC.
CU Output
We can now design the control unit. The control unit must output control signals forevery device in the processor. Specifically, the processor contains the following controllines:
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Registers: LD, IN, and CL, lines for the registers MAR, PC, MBR, AC, InREG, OutREG, IR, and C
Memory: Wt line for the memory unit.
ALU: G function code line for the ALU.
AC: SL input selection line.
Bus: S20 address selection lines for the bus.
Processor Sequencing
Each machine language instruction is broken into a sequence of steps. Each step is anRTL instruction, performed in one clock cycle. The current step is indicated to theprocessor by the timing signals, T60. The instruction being executed is indicated by theoperation signals D90.
As described in Section 4.3 a machine language instruction is fetched, decoded, andexecuted. The sequence of RTL instruction for the fetch and decode are the same for allmachine instructions, and can be done in four steps (T0 – T3). After the decode,instruction execution varies.
Table 3. shows all RTL instructions for the simple Marie machine, and the decodersignals which trigger them. Also indicated are the control signals which need to beasserted to perform the RTL instructions.
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Operation RTL Control Output
Fetch Instruction T0: MAR PC, C C + 1 LD(MAR), IN(C), S = 010
T1: IR M[MAR], PC PC + 1, C C + 1
LD(IR), IN(PC), IN(C), S = 000
Decode Instruction T2: MAR IR110, D09 Decode(IR1512), F20 Decode(IR1110), C C + 1
LD(MAR), IN(C), S = 111
Fetch Operand T3(D1 +D3 + D4): MBR M[MAR] LD3, S = 000
T3: C C + 1 IN(C)
Load T4D1: AC MBR, C 0 LD(AC), CL(C), S = 011, SL(AC)
Store T4D2: MBR AC, C C + 1 LD(MBR), IN(C), S = 100
T5D2: M[MAR] MBR, C 0 Wt, CL(C), S = 011
Add T4D3: AC AC + MBR, C 0 LD(AC), CL(C), G = 0
Subt T4D4: AC AC MBR, C 0 LD(AC), CL(C), G = 1
Input T4D5: AC InREG, C 0 LD(AC), CL(C), SL(AC)S = 101
Output T4D6: OutREG AC, C 0 LD(OutREG), CL(C), S = 100
Halt T4D7: C 6 LD(C)
Skipcond T4D8F0N: PC PC + 1 IN(PC)
T4D8F1Z: PC PC + 1 IN(PC)
T4D8F2P: PC PC + 1 IN(PC)
T4D8: C 0 CL(C)
Jump T4D9: PC IR011, C 0 LD(PC), CL(C), S = 111
Table 3. Control settings for Marie.
In Table 3, fetch is performed using the RTL instructions necessary. The decode phasedecodes the IR into the two sets of signals, D90, the operation lines, and F20, thecomparison function lines. After the decode, if the operation is D4,3,1, an operand must beloaded. Then at time T4 the machine language instruction is executed. The RTL for most
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instructions is pretty straight forward. However, the Halt and Skipcond instructions are alittle confusing. For the Halt instruction, the sequencer is set to Time 6. This timetriggers no RTL instructions. The result is that the machine will freeze, until the machineis restarted and the sequencer, C, is cleared.
The Skipcond instruction always clears the sequencer. Based on the comparisonfunction, F20, and the status flags, N, Z, and P, either the PC is incremented, or not.
Output of the CU
Table 3. gives all information necessary to build the control unit. One final step remainsin the design of the control unit, and that is to build circuits for each of the control unitoutputs. The major task involved in this, is producing boolean equations for each output.
Deriving an output equation involves inverting Table 3. As an example, we will derivean equation for IN(PC). To do this we examine Table 3. for all entries which assertIN(PC), and form the OR of their input signals. This produces the following equations:
IN(PC) = T1 + T4D8F0N + T4D8F1Z + T4D8F2P = T1 + T4D8(F0N + F1Z + F2P)
As another example, the S2 signal is done in a similar way. We look for entries withoutput S = 1XX (S2 is a 1) specified, and form the equation:
S2 = T2 + T4D2 + T4D5 + T4D6 + T4D9 = T2 + T4(D2 + D5 + D6 + D9)
Output signals which are not found in the table are wired to a 0 signal. For example,
IN(AC) = 0
A complete set of nonzero equations is given in Table 4.
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Output Signal Equation
LD(MAR) T2 + T0
IN(C) T0 + T1 + T2 + T3 + T4 D2
S0 T2 + T4(D1 + D5 + D9) + T5 D2
S1 T0 + T2 + T4(D1 + D9) + T5 D2
S2 T2 + T4(D2 + D5 + D6 + D9)
LD(IR) T1
IN(PC) T1 + T4D8(F0N + F1Z + F2P)
LD(MBR) T3(D1 + D3 + D4) + T4 D2
LD(AC) T4(D1 + D3 + D4 + D5)
CL(C) T4(D1 + D3 + D4 + D5 + D6 + D8 + D9) + T5 D2
Wt T5 D2
G T4 D4
SL(AC) T4 (D1 + D5)
LD(OutREG) T4 D6
LD(C) T4 D7
LD(PC) T4 D9
Table 4. Output equations for the control unit.
Microprogrammed ControlWith microprogrammed control an RTL instruction is viewed as just that; an instruction.Each clock cycle a microinstruction is fetched from a special microinstruction memory,and executed. The execution of the microinstruction, or RTL instruction, involves theusual setting of control lines.
The control unit for a microprogrammed system is shown in Figure 4.15 of the text, andFigure 6 is a more detailed view of the same hardware.
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N,Z,P
F2-0
D9-0
Micro-insructionDecoder
AddressMapper
Micro-instruction
ROM
control output
branch control
M18-0
A3-0
Figure 6. Microprogrammed control unit.
Notice that this control unit does not need a sequence register, C. An address mapperuses the decoded opcode, the decoded comparison function, and the status flags, N, Z,and P, to determine the address of the next microinstruction in the microinstruction ROMunit, called A. That micro instruction is output by the ROM, as M, and decoded. Theresults of the decoding are control signals, sent to the registers and bus, and branchcontrol, used in the calculation of the next microinstruction address.
There are several ways to implement microcontrol. Our choice of implementation isbased purely on simplicity of implementation, and an attempt to match the materialpresented in the book. The first question we consider is what a micro instruction lookslike. A microinstruction for our machine is a numeric instruction with the format shownin Figure 7.
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2 bits4 bits13 bits
seladdresscontrol
Figure 7. Microinstruction format.
The control field specifies control signals sent to the processor data path. The sel andaddress field are used to help specify the address of the next microinstruction to beexecuted.
Address Selection
Our simple implementation of the control unit will have three methods for calculating theaddress of the next instruction. These methods are specified by the sel field, as shown in Table 5.
sel Name Description
00 UNB Unconditional branch to the instruction at the address given in the address field.
01 CBL Conditional branch based on the signals D90, F20, N, Z, P, to operand fetch.
10 CBD Conditional branch based on the signals D4,3,1, from operand fetch.
Table 5. Address selection options.
There are two conditional branch types which implement the two places in machine cyclewhen branches must be performed, as seen in Table 3, and shown in Figure 8. The firstbranch needed is at time T2, at which point either the operand fetch RTL instruction isperformed, or the machine instruction is executed. This choice is conditioned on thevalue of the signals D90, F20, N, Z, and P, and corresponds to the CBL branch. Thesecond branch occurs at time T3, at which point you branch to begin execution of thespecific machine instruction requiring the operand fetch. This choice is conditioned onthe values of D4,3,1, and corresponds to the CBD branch.
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D9-5,2
Execute
MBR M[MAR]
Fetch, DecodeFetch, DecodeFetch, Decode
CBD
CBLD
4,3,1
D4,3,1
Figure 8. Control for microprogram.
Our address field is 4bits. A microinstruction ROM unit of length 16 is needed, and itwill be loaded, as we shall see, with 16 microinstructions which correspond to the 16entries in Table 3.
Control Signals
The control field of the microinstruction. contains a bit for each simple RTL instructionused in the Marie machine. These instructions are listed in Table 6, along with theirmnemonics, and bit position.
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Position RTL Symbolic Name
6 MAR PC PC2AR
7 IR M[MAR] FETCH
8 PC PC + 1 INCPC
9 MAR IR IR2AR
10 MBR M[MAR] MREAD
11 AC MBR LOADAC
12 MBR AC AC2BR
13 M[MAR] MBR MWRITE
14 AC AC + MBR PLUS
15 AC AC MBR MINUS
16 AC InREG IN
17 OutREG AC OUT
18 PC IR JMP
Table 6. Bits in the control field.
The positions start at Bit 6, since Bits 05 are allocated to the sel and address fields. Eachbit, if set, will cause the indicated microinstruction to be executed.
Marie Microinstructions
We now examine the actual microcode used in the Marie machine. We first present it insymbolic form, and then show the binary version. The symbolic “microassembly”version is given in Table 7. It shows the microinstructions, and their location in theROM.
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Location Control Address Sel
F0 (PC2AR) F1 UNB
F1 (FETCH, INCPC) F2 UNB
F2 (IR2AR) CBL
F3 (MREAD) CBD
L0 (LOADAC) F0 UNB
S0 (AC2BR) S1 UNB
S1 (MWRITE) F0 UNB
A0 (PLUS) F0 UNB
SU0 (MINUS) F0 UNB
I0 (IN) F0 UNB
O0 (OUT) F0 UNB
H0 () H0 UNB
SCN0 (INCPC) F0 UNB
SCZ0 (INCPC) F0 UNB
SCP0 (INCPC) F0 UNB
J0 (JMP) F0 UNBTable 7. Marie microprogram.
This microprogram starts at location F0. For any machine instruction, the first RTLinstruction executed will be PC2AR. There is an unconditional branch from thisinstruction to location F1, so that the next clock cycle will see the RTL instructionsFETCH and INCPC being executed. An unconditional branch is then executed tolocation F2, where the RTL instruction IR2AR is executed. At this point a conditionalbranch, based on the machine instruction is taken. For example, if the machineinstruction were a Load instruction, a branch to F3 would be taken. After the MREADRTL instruction is executed, another conditional branch is taken, which would sendexecution to location L0, where the BR2AC instruction is executed, and the branch backto F0 is taken. On the other hand, if the machine instruction were a SkipCondinstruction, with a test for zero, and the Z flag was set, at location F2, the conditionalbranch would take execution directly to SCZ0.
Table 8 gives the same microprogram as Table 7 in binary. It is a straightforwardassembly of the symbolic code into numeric form.
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Location Control Address Sel
0000 0000000000001 0001 00
0001 0000000000110 0010 00
0010 0000000001000 XXXX 01
0011 0000000010000 XXXX 10
0100 0000000100000 0000 00
0101 0000001000000 0110 00
0110 0000010000000 0000 00
0111 0000100000000 0000 00
1000 0001000000000 0000 00
1001 0010000000000 0000 00
1010 0100000000000 0000 00
1011 0000000000000 1011 00
1100 0000000000100 0000 00
1101 0000000000100 0000 00
1110 0000000000100 0000 00
1111 1000000000000 0000 00Table 8. Binary microprogram.
Microinstruction Decoder Design
Table 8 gives us the content of the ROM unit. Referring back to Figure 6, of the devicesshown, two other pieces in the figure remain to be examined: the address mapper, and themicroinstruction decoder. We begin with the microinstruction decoder (MDec).
The MDec receives input from the ROM unit in the form of nineteen signals, called M180.It outputs control for the registers and bus. In addition address information is passed onto the address mapper. This information is bits M50, the address and sel fields of themicroinstruction, which flow straight through the MDec.
Our first step in the design of the MDec is to list all control signals needed for each of themicroinstruction control options. This information is presented in Table 9.
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Control Option Input Output
PC2AR M6 LD(MAR), S = 010
FETCH M7 LD(IR), S = 000
INCPC M8 IN(PC)
IR2AR M9 LD(MAR), S = 111
MREAD M10 LD(MBR), S = 000
LOADAC M11 LD(AC), S = 011, SL(AC)
AC2BR M12 LD(MBR), S = 100
MWRITE M13 Wt, S = 011
PLUS M14 LD(AC), G = 0
MINUS M15 LD(AC), G = 1
IN M16 LD(AC), SL(AC), S = 101
OUT M17 LD(OutREG), S = 100
JMP M18 LD(PC), S = 111Table 9. Control signals for microinstruction control options.
By inverting Table 9, we can derive the output equations for the MDec. From the outputequations, the circuit design is merely a simple exercise. The inverted table is shown inTable 10. All signals not mentioned are wired to a 0 signal.
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Output Input
LD(MAR) M6 + M9
LD(IR) M7
IN(PC) M8
LD(MBR) M10 + M12
LD(AC) M11 + M14 + M15 + M16
Wt M13
LD(OutREG) M17
LD(PC) M18
G M15
SL(AC) M11 + M16
S0 M9 + M11 +M13 + M16 + M18
S1 M6 + M9 + M11 + M13 + M18
S2 M9 + M12 + M16 + M17 + M18
Table 10. Output equations for the MDec.
Address Mapper
The last piece of circuitry needed is the address mapper. The inputs to this combinationalcircuit are M50, F20, D90, N, Z, and P. The output is a fourbit address, A30. An abstractdiagram of the circuit is shown in Figure 9. The circuit is composed of three subcircuits.A MUX chooses between the address field of the microinstruction, for the UNB, or eitherthe output of the mappers for the CBL or CBD. This choice is based on the sel field ofthe microinstruction. It remains to design the two submappers.
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A3-0
4
N,Z,PF
2-0
D9-0
M5-2
CBDMapper
CBLMapper
MUX
D4,3,1
M1-0
Z3-0
W3-0
Figure 9. Structure of the address mapper.
We begin with the design of the CBL Mapper. Table 11 is a truth table for this mapper,and a circuit can be designed from this table using methods which you should know wellby now. In this table the target address, Z, is based only on the decoded opcode, exceptfor the Skipcond instruction, with which the target depends on the function code, and thethe values of the status flags.
The target address in Table 11 is based on information from Table 8. For example, forthe Store instruction, the handler code is located at address 0101, and so this is theaddress given for the D2 entry in the table (0000000100).
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D90 F20 N,Z,P
Z30
0000000010 XXX XXX 0011
0000000100 XXX XXX 0101
0000001000 XXX XXX 0011
0000010000 XXX XXX 0011
0000100000 XXX XXX 1001
0001000000 XXX XXX 1010
0010000000 XXX XXX 1011
0100000000 001 100 1100
0100000000 001 0XX 0000
0100000000 010 010 1101
0100000000 010 X0X 0000
0100000000 100 001 1110
0100000000 100 XX0 0000
1000000000 XXX XXX 1111Table 11. Truth table for CBL mapper.
Finally, the CBD mapper has the truth table shown in Table 12. This table is also derivedfrom Table 8. It has entries, for each of the instructions requiring operand fetches, totheir respective handler instructions. For example, the Load instruction, indicated by D1
(001), has its handler at address 0100.
D4,3,1 W30
001 0100
010 0111
100 1000Table 12. CBD mapper truth table.
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Bibliography1. Null, L., Lobur, J., The Essentials of Computer Organization and Architecture,
Jones and Bartlett Pub., Sudbury, Ma., 2003.
2. Mano, M. M., Computer System Architecture, 3rd Ed., Prentice Hall,Englewood Cliffs, NJ., 1993.
3. Carpinelli, J. D., Computer Systems Organization and Architecture, AddisonWesley, Boston, 2001.
Exercises1. You wish to add the instruction IncAC, that increments the AC register, to the Marie
machine, using hardwire control. Show changes to Table 1 and Table 3 thatimplement this new instruction. The new instruction will have opcode 0.
2. You wish to add the instruction Skipcond if nonnegative, which skips the nextinstruction if the status flags indicate the result is zero or positive. Show changes toTable 1 and Table 3 that implement this new instruction. The new instruction willhave opcode 0.
3. Give a trace of the following program. Show all RTL instructions from Table 3 thatare executed.
Input
Store 0
Input
Add 0
Halt
4. Repeat Exercise 1 for the microprogrammed controller. Make appropriate changes toTables 612.
5. Repeat Exercise 2 for the microprogrammed controller. Make changes to Tables 612.
6. Repeat Exercise 3 for the microprogrammed controller. Show all instructions fromTable 7 that are executed.
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