Israel, May 4, 2010

Timing Closure Using One Machine

Rajeev Madhavan

Chairman and CEO

Magma Design Automation

May 4, 2010

Israel, May 4, 2010

New Challenges for Digital Design

Improved productivity required to meet market-driven design costs and schedules

1997 2001 2004 2008 2010

Silicon Tech. 250nm 130nm 90nm 45nm 32nmMax Design (Inst.) 1M 4M 12M 16M >50MFunctional Modes 2 3 4 5 >10?Power Consumption 1W 500mW 200mW 50mW <25mW?Parasitics CL CLRL CC RD CC, RD CCVia, RDVia

Process Variation 1X 1.1X 1.4X 1.8X >2X? Nominal Yield 95% 85% 75% 50% %?

Investment $2M $5M $20M $50M $100M?

Engineers 2 5 10 25 50?Productivity 1X 1.5X 2X 3X 5X?

Israel, May 4, 2010

Digital Design Complexity Increasing Exponentially

2005 90 nm

2007 65 nm

2009 40 nm

2010 32 nm

2011 22 nm

Operational Modes: 5 @ 65nm 15 @ 22nm

PVT Corners: 25 @ 65nm 50 @ 22nm

IncreasingGate Count

Multi-Modes Multi-Corners

More Timing

Scenarios

Gate Count: 20M @ 65nm 400M @ 22nm

Israel, May 4, 2010

28nm Challenges: Rising # of PVT Corners & Modes

4

Temperature125o C

0o C 40o C

ProcessSS

TypFF

InterconnectCmax

Ctyp

Cmin

Voltage.94V

1.34V1.025V

Func_setupFunc_hold Func_bypass_setup Func_bypass_hold Scan_hold Scan_setup Scan_capture_hold Scan_capture_setup Bist_holdBist_setupBist_pll_setupBist_pll_holdPbist_holdPbist_setupLow_power_setupLow_power_holdTfault_shift_setupTfault_shift_holdTfault_capture_setupTfault_capture_holdDDR_write_setupDDR_write_holdDDR_read_setupDDR_read_hold

Many Corners Many Modes• Increase in process variation requires multiple PVT corners

• Greater functionality requires multiple modes

Many more timing scenarios required for signoff

Israel, May 4, 2010

28nm Challenges: Pessimistic OCV Margins

OCV Margins Lead to

PRO: More robust design

CON: AREA Increase

- More buffers- Larger cells

CON: Worse TAT

- More timing fixes

Setup: 12%Hold: 8%

Setup: 12%Hold: 8%

Setup: 12%Hold: 8%

Traditional OCV margins are too pessimistic

Israel, May 4, 2010

Solving the increasing variability problem

• Approach 1 - SSTA– Block based and path based SSTA

• Challenges in characterization

• New approach – analyzing, interpreting statistical data

• No real integration to P&R, STA, extraction

Israel, May 4, 2010

Solving the increasing variability problem

• Approach 2 - Enabling Timing Closure in 1 Computer– Breakthrough in STA– Performance for large designs– New approach to MMMC

• No new learning curve• Tight integration: P&R, STA, extraction

• Reduce ECO fixes

Israel, May 4, 2010

New STA Architecture Required to Address Complexity

Old STA architectures exhibit performance problems on a

single CPU for designs with:- large # of instances

- large # of constraints

New STA Architecture enables single-CPU performance that scales with design sizes that are increasing by 2x every 18 mos

Min

utes

1 10Millions of Instances

5

60

Hours

New STA architecture’s single CPU scales well for any design

Israel, May 4, 2010

New STA Architecture Near-linear Multi-threading

New Architecture combines single-CPU performance and near-linear scaling for multi-CPU machine

Min

utes

1 10Millions of Instances

5

60

Hours

Single CPU Performance 4-CPU

8-CPU3x on 4-CPUs

6x on 8-CPUs

Israel, May 4, 2010

28nm Solution: The Future of MMMC is on One Machine

Traditional MMMC- Lots of reports- Lots of machines- Lots of ECO’s

Concurrent MMMC- One Machine

...

Scenario 1 Scenario 4Scenario 3Scenario 2

Scenario 5 Scenario nScenario 7Scenario 6SDC-1

SDC-n

spef-1

spef-n

LIB-1 LIB-n

1 Server

... ...

...

Israel, May 4, 2010

28nm Solutions: Concurrent MMMC on a Single Machine

set modes "func bisr_g0 bisr_g1 bisr_g1_pll bisr_g3 bisr_g4 mbist scan_bisr scan_bisr_shift scan_flush_shift scan scan_shift"foreach mod $modes {

force timing scenario create $m ${mod}_scenario –mode $mod –enable –check both –ocv on –crpr on –xtalk on }

enable/disable

setup/hold/both

on/off

on/off

on/off

Flexible configuration of timing scenarios (timing modes * PVT corners)

Onescript

nonono

Configure “on-the-fly” – with updated results in seconds

setupholdsetup

1 Server

Israel, May 4, 2010

MMMC Cockpit Enables Fast Analysis, Efficient ECO’s

Scenario Name WS Hold (ns) TNS Hold (ns) NFE Hold WS Setup (ns)TNS Setup (ns) NFE Setup------------------------- ---------------- ---------------- ---------- -------------- --------------- ---------func_scenario -0.02 -0.13 12 -2.52 -37.77 1255bisr_1_scenario -0.16 -33.21 666 7.68 0 0bisr_2_scenario -0.16 -32.93 662 0.1 0 0ddr_wr_scenario -0.16 -32.93 662 -5.15 -231.14 1142ddr_rd_scenario -0.16 -33.41 670 45.19 0 0ddr_rd2_scenario -0.16 -33.65 673 3.04 0 0mbist_scenario -0.16 -32.03 648 -5.15 -225.35 1140scan_bisr_scenario -0.16 -22.92 494 8.14 0 0scan_2_shift_scenario -0.16 -57.69 1298 0.38 0 0scan_flsh_scenario -0.76 -67.4 1252 2.1 0 0scan_scenario -0.13 -8.79 268 6.37 0 0scan_shift_scenario -0.76 -67.4 1252 2.1 0 0

All Timing Scenarios on One Machine

MMMC Cockpit: Pre-ECO

Implement ECOs for all timing modes, PVT corners on One Machine

Scenario Name WS Hold (ns) TNS Hold (ns) NFE Hold WS Setup (ns)TNS Setup (ns) NFE Setup------------------------- ---------------- ---------------- ---------- -------------- --------------- ---------func_scenario 0.02 0 0 0 0 0bisr_1_scenario 0.02 0 0 0.1 0 0bisr_2_scenario 0.02 0 0 1 0 0ddr_wr_scenario 0.1 0 0 0.15 0 0ddr_rd_scenario 0.002 0 0 0.22 0 0ddr_rd2_scenario 0.3 0 0 0.15 0 0mbist_scenario 0.1 0 0 0.18 0 0scan_bisr_scenario 0.023 0 0 0.023 0 0scan_2_shift_scenario 0.05 0 0 0.9 0 0scan_flsh_scenario -0.1 1 1 0.00023 0 0scan_scenario 0.023 0 0 0.01 0 0scan_shift_scenario -0.15 2 3 1 0 0

MMMC Cockpit: Post-ECO

1 Server

Israel, May 4, 2010

28nm Solutions: Tight Integration of P&R, Extraction, and STA

P&R

ECO Cycles

Sign-off

Tapeout

Extraction

STA

Traditional Approach:

Separate extraction & STA tools result in TCL-based

“What-if” ECO’s

Timing Closure on One Machine: Layout-aware ECO’s

New Approach:

Tight P&R & extraction & STA integration results in faster,

more accurate ECO’s

Extractiontool

P&R tool

Israel, May 4, 2010

28nm Solutions: Reducing Timing MarginsLarger Die Size

More timing fixes Setup: 12%

Hold: 8%Setup: 12%

Hold: 8%Setup: 12%

Hold: 8%

Smaller Die SizeLess timing fixesSetup: 12%

Hold: 6%Setup: 10%Hold: 7.8%

Setup: 10.3%Hold: 6.2%

Traditional OCV

Advanced OCV

Israel, May 4, 2010

28nm Solutions: SPICE Reduces Timing Margins

• Smaller geometries & increased design complexity force designers to pad timing analysis with margins

• Integrated SPICE engine enables – Reduced margins

– Increased accuracy

SPICE Models

Process Variation

Cell Characterization

NLDM/CCSModels

DesignSign-off

Characterization Margin

Modeling Margin

Design Margin+ + = over

design!

Critical paths

Israel, May 4, 2010

Summary

• Timing closure on one machine: The Future is Now

– Breakthrough in STA

– MMMC timing closure on one machine

– Tight integration of P&R, STA, and extraction

– Reduce margins, reduces ECO fixes

Extractiontool

P&R tool

Israel, May 4, 201017 17