magestic: machine-learning for automatic generation of
TRANSCRIPT
© 2019 Cadence Design Systems, Inc. All rights reserved.1 DISTRIBUTION STATEMENT A: Approved for Public Release, Distribution Unlimited
ERI Design: IDEA and POSH
IDEA and POSH Integration Exercise
Detroit, MI
July 17 – July 19, 2019
Cadence Design Systems, NVIDIA and Carnegie Mellon University
MAGESTIC: Machine-Learning for Automatic Generation
of Electronic Systems Through Intelligent Collaboration
This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA). The views, opinions, and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.
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• Team: Cadence Design Systems, NVIDIA and Carnegie Mellon University
• Goals: – No Human in the Loop (NHIL) Design Flow, Silicon Compiler in < 24 hours TAT
– Research in Analog IC Design through Package and PCB Design
– Achieve Automated Design Across a Broad Spectrum of Designs in Year 2
• Agenda for Today:
– Software Demonstration of NHIL Package and PCB Design Progress
– Focus for NHIL Package and PCB Design Research in Year 2
– Software Demonstration of NHIL Analog IC Design Progress
– Focus for NHIL Analog IC Design Research in Year 2
• Visit MAGESTIC Team to see Live Demos of the Design Data Presented Today
MAGESTIC Program
Taylor Hogan
Elias Fallon
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PCB & Package SynthesisERI Conference 2019
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• The Dark Age–Interactive, NAIL
• The Industrial Age–NHIL for Some, Hope
• The Age of Enlightenment–NHIL for All, Explorations
EDA Ages
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The Dark Ages
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The Dark Ages Continue
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The Industrial Age
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Industrial Age Training Neural Networks to Avoid Intractable Computational Problems
GO Floorplan
TRAIN modeNetlist
FloorplansRUDY
congestion
images
CN
N
GR
routability
metric
GO Floorplan
INFERENCE
mode
Netlist
CNN
Design Features
𝐻𝑃𝑊𝐿𝐵𝑜𝑎𝑟𝑑 𝐷𝑖𝑚𝑠
⋮+
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The Industrial Age … Hope
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Industrial Age Continues
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What WorksWhat Does Not Work
55
88
100
60
90
100 100 100 10092
72
100
64
90
42
24
100
89
100
91 91
30
100 100 100 100 100
82 80
90
100
89 90
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Percent Complete
Open
Source
RISC PCB
Complex
Interposer Mobile
PCB
GPU
PCB
Small
Analog
PCB
Complex
Analog
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Achieving NHIL for All Year 2 Goals
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Age of EnlightenmentFeature Sensitivity Analysis
• Development of methods and tools that aid in the interpretability of neural networks by humans
• Explain what features matter
Feature Analysis
Input
Feature
Dataset
Model
Long-Range RUDY
Macros
Pin Density
RUDY Pins
. . .
. . .
Year 2 Goals
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The Age of EnlightenmentData Mining to eliminate typing in the known
Old Designs
Data SheetsDesign parser
Information extraction
database
Machine learning
Model training
Model Prediction
Python models
new
designs
Year 2 Goals
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Analog ICERI Conference 2019
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MAGESTIC Analog
Inte
gra
ted F
low
Analog
Circuit
Analog
Layout
Analog
Circuit Sizing
Floorplanning
Placement
Routing
Layout
Finishing
Verify &
Extract
Electrical
Performance
Exploration and Innovation
Genetic
Optimizing Router
Full Graph-
Embedded RL
Global Router
CMU RL Agent
Global Router
AlphaRoute
Research Dimensions
• Integrated flow− See complex interactions between steps
− Evaluate overall electrical performance
• Exploration and Innovation − Creative research into new approaches
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ML based yield
improvements
Within design
metrics, better yield
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Inte
gra
ted F
low
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Analog
Circuit
Analog
Layout
Analog
Circuit Sizing
Floorplanning
Placement
Routing
Layout
Finishing
Verify &
Extract
Electrical
Performance
Inte
gra
ted F
low
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Analog
Circuit
Analog
Layout
Analog
Circuit Sizing
Floorplanning
Placement
Routing
Layout
Finishing
Verify &
Extract
Electrical
Performance
Inte
gra
ted F
low
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Layout Group Prediction Problem
• It is common practice for layout designers to group devices that need good matching– Grouped devices are placed closely together,
and there may be interdigitation
• Grouping decisions are largely made from experience– Even simulation cannot fully predict effects of grouping
– Can we learn them from good hand-crafted layouts?
• To formulate a machine learning problem, we need to define grouping as a label and predict it from schematic features
M0.1 M1.1
M1.2 M0.2
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Gro
upin
g M
odel
Utiliz
ed
Analog
Circuit
Analog
Layout
Analog
Circuit Sizing
Floorplanning
Placement
Routing
Layout
Finishing
Verify &
Extract
Electrical
Performance
Inte
gra
ted F
low
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But Wait! There’s More!
Figure 3.13 Actual Capacitance v/s Error Percentage plots across all nets.
Parasitic Prediction Graph Neural Networks for
Routing Cost Prediction
AlphaRoute /
AlphaAnalogDesign Updates
Exploration and Innovation
Please stop by during the IDEA Integration Exercise to see a demo
or discuss in more detail many of our other exciting projects
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Grouping Cold Start Problem
0 1
2 3
4 5
6 7
8 9 10 11
Suppose we are given the following (sparse) labels:
- Transistor 0, 4, 6, and 8 will be in different groups
- Transistor 6 & 7 belong to the same group
Can we train a reasonable grouping model using the netlist information?
Exploration and Innovation
Graph Convolutional Network (GCN)
Representation of Circuit
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GCN Training for Grouping Cold Start Model
The learning curve of 10 runs, each with a
maximum of 50 epochs
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Cadence Design Systems, NVIDIA and Carnegie Mellon University
This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA). The views, opinions, and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.