machine basics

8/18/2019 Machine Basics

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1and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Machine-Level ProgrammingI: Basics

!"#$%&"#$: 'ntroduction to Computer Systems!th (ecture, Sep) !, #*!

Instructors:

+andal E) Bryant and avid +) O’Hallaron


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Today: MachineProgramming I: Basics

History of Intel processors andarchitectures

C, assemly, machine code !ssemly Basics: "egisters, operands,

move !rithmetic # logical operations


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Intel $%& Processors

'ominate laptop(des)top(server mar)et

*volutionary design Bac-.ards compati/le up until &*&0, introduced in

12& Added more 3eatures as time goes on

Comple$ instruction set computer +CIC

4any di5erent instructions .ith many di5erent3ormats But, only small su/set encountered .ith (inu6

programs

Hard to match per3ormance o3 +educed 'nstruction

Set Computers 7+'SC8 But, 'ntel has done 9ust that


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Intel $%& *volution: Milestones

Name Date Transistors MHz %.%& /01% 203 4-/.

;irst 0"/it 'ntel processor) Basis 3or 'B4 PC < OS

4B address space

5%& /0%4 2143 /&-55 ;irst $# /it 'ntel processor , re3erred to as 'A$#

Added =>at addressing?, capa/le o3 running @ni6

Pentium 6* 2..6 /24M 2%..-

5%.. ;irst 0"/it 'ntel 6&0 processor, re3erred to as 6&0"0

Core 2 2..& 20/M /.&.-54..

;irst multi"core 'ntel processor Core i1 2..% 15/M /1..-


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Intel $%& Processors, cont7 Machine *volution

$&0 1&! *)$4

Pentium 11$ $)4

Pentium%44 112 )!4

PentiumPro 11! 0)!4

Pentium ''' 111 &)#4

Pentium #** #4 Core # uo #**0 #14

Core i2 #**& 2$4

!dded 8eatures

'nstructions to support multimedia operations 'nstructions to ena/le more ecient conditional

operations

Transition 3rom $# /its to 0 /its

4ore cores


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2./4 tate of the !rt Core i2 Broad.ell #*!

'es)top Model cores

'ntegrated graphics

$)$"$)& DH

0!F

erver Model & cores

'ntegrated '%O

#"#)0 DH

!F


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$%& Clones: !dvanced Micro'evices +!M'

HistoricallyA4 has 3ollo.ed 9ust /ehind 'ntel

A little /it slo.er, a lot cheaper

Then

+ecruited top circuit designers 3rom igital EGuipmentCorp) and other do.n.ard trending companies

Built Opteron: tough competitor to Pentium

eveloped 6&0"0, their o.n e6tension to 0 /its

"ecent 9ears

'ntel got its act together (eads the .orld in semiconductor technology

A4 has 3allen /ehind +elies on e6ternal semiconductor manu3acturer


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Intels &6-Bit History 2../: Intel !ttempts "adical hift from

I!52 to I!&6 Totally di5erent architecture 7'tanium8

E6ecutes 'A$# code only as legacy

Per3ormance disappointing

2..5: !M' teps in ;ith *volutionaryolution 6&0"0 7no. called =A40?8

Intel 8elt


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C i M ll


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'e=nitions

!rchitecture: +also I!: instruction setarchitecture The parts of a processordesign that one needs to understand or;rite assemly(machine code7

E6amples: instruction set specication, registers) Microarchitecture: Implementation of the

architecture7 E6amples: cache sies and core 3reGuency)

Code 8orms: 4achine Code: The /yte"level programs that a

processor e6ecutes

Assem/ly Code: A te6t representation o3 machinecode

C i M ll


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CP>

!ssemly(Machine Code?ie;

Programmer-?isile tate PC: Program counter

Address o3 ne6t instruction Called =+'P? 76&0"08

"egister =le Heavily used program data

Condition codes Store status in3ormation a/out

most recent arithmetic or logicaloperation

PC

"egisters

Memory

Code'atatac)

Addresses

ata

'nstructionsConditionCodes

Memory Byte addressa/le array

Code and user data

Stac- to supportprocedures


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C i M ll


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Compiling Into !ssemlyC Code

+sum7clong plus(long x, long y);

void sumstore(long x, long y,

long *dest)

long t ! plus(x, y);

*dest ! t;"

Aenerated $%&-&6

!ssemlysumstore# pus$% &r'x mov% &rdx, &r'x

call plus

mov% &rax, (&r'x)

pop% &r'x

ret


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!ssemly Characteristics: 'ataTypes

FIntegerG data of /, 2, 6, or % ytes ata values Addresses 7untyped pointers8

8loating point data of 6, %, or /. ytes

Code: Byte seuences encoding series ofinstructions

o aggregate types such as arrays orstructures Lust contiguously allocated /ytes in memory


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Code for

sumstorex+#x

x

x+

xd

xe

x2 x

x

x

x

x+

x

x'

xc


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Machine Instruction*$ample C Code

Store value t .heredesignated /y dest

!ssemly 4ove &"/yte value to

memory

Muad .ords in 6&0"0parlance

Operands:

t: +egister &rax

dest: +egister &r'x

*dest: 4emory MJ&r'x/


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'isassemled

'isassemling


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'isassemled

4ump o assem'ler code or unction sumstore#

x+ 5# pus$ &r'x

x+3 51# mov &rdx,&r'x

x++ 5# call% x+ plus

x+e 5+# mov &rax,(&r'x)

xa1 512#pop &r'x xa2 51#ret%

!lternate 'isassemly

ithin gd 'eugger

gd' sum disassem'le sumstore

isassem/le procedure

x61x' sumstore

E6amine the /ytes starting atsumstore


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hat Can e'isassemledK

!nything that can e interpreted ase$ecutale code

'isassemler e$amines ytes and

& o'0dump -d 7897O:4.


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Carnegie Mellon


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g


rsp

$%&-&6 Integer "egisters

Can re3erence lo."order /ytes 7also lo."order

< # /ytes8

ea$

e$

ec$

ed$

esi

edi

esp

ep

r%d

r0d

r/.d

r//d

r/2d

r/5d

r/6d

r/4d

r%

r0

r/.

r//

r/2

r/5

r/6

r/4

ra$

r$

rc$

rd$

rsi

rdi

rp

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g


ome History: I!52"egisters

&eax

&ecx

&edx

&e'x

&esi

&edi

&esp

&e'p

&ax

&cx

&dx

&'x

&si

&di

&sp

&'p

&a$

&c$

&d$

&'$

&al

&cl

&dl

&'l

/&-it virtual registers+ac);ards compatiility

g e n e r a

l p u r p o s e

accumulate

counter

data

base

source

index

destination

index

stack

pointer

base

pointer


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g


Moving 'ata Moving 'ata

mov% Source, Dest :

x, >- (i-e C constant, /ut pre6ed .ith ?>@ Encoded .ith , #, or /ytes

Register: One o3 0 integer registers E6ample: &rax, &r1

But &rsp reserved 3or special use Others have special uses 3or particular instructions

Memory: & consecutive /ytes o3 memory at addressgiven /y register Simplest e6ample: (&rax)

Narious other =address modes?

&rax

&rcx

&rdx

&r'x

&rsi

&rdi&rsp

&r'p

&r9

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g


mov%


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imple Memory!ddressing Modes

ormal +" MemJ"egJ" +egister + species memory address

Aha Pointer dere3erencing in C

mov% (&rcx),&rax

'isplacement'+" MemJ"egJ"N'

+egister + species start o3 memory region

Constant displacement species o5set

mov% (&r'p),&rdx

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* l f i l


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*$ample of imple!ddressing Modes

void sBap

(long *xp, long *yp)

long t ! *xp;

long t1 ! *yp;

*xp ! t1; *yp ! t;

"

sBap#

mov% (&rdi), &rax

mov% (&rsi), &rdx

mov% &rdx, (&rdi) mov% &rax, (&rsi)

ret

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&rdi

&rsi

&rax

&rdx

>nderstanding SBap+

void sBap

(long *xp, long *yp)

long t ! *xp;

long t1 ! *yp;

*xp ! t1;

*yp ! t;

"

Memory

"egister ?alue

&rdi xp

&rsi yp

&rax t

&rdx t1

sBap#

mov% (&rdi), &rax C t ! *xp

mov% (&rsi), &rdx C t1 ! *yp

mov% &rdx, (&rdi) C *xp ! t1

mov% &rax, (&rsi) C *yp ! t

ret

"egisters

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>nderstanding SBap+

12

64&

&rdi

&rsi

&rax

&rdx

x12

x1

"egisters

Memory

sBap#


mov% (&rsi), &rdx C t1 ! *yp mov% &rdx, (&rdi) C *xp ! t1


ret

x12

x11

x11

x1

x1

!ddress

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>nderstanding SBap+

12

3

&rdi

&rsi

&rax

&rdx

x12

x1

12

"egisters

Memory

sBap#




ret

x12

x11

x11

x1

x1

!ddress

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>nderstanding SBap+

12

3

&rdi

&rsi

&rax

&rdx

x12

x1

12

3

"egisters

Memory

sBap#




ret

x12

x11

x11

x1

x1

!ddress

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>nderstanding SBap+

3

3

&rdi

&rsi

&rax

&rdx

x12

x1

12

3

"egistersMemory

sBap#




ret

x12

x11

x11

x1

x1

!ddress

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>nderstanding SBap+

3

/25

&rdi

&rsi

&rax

&rdx

x12

x1

12

3

"egistersMemory

sBap#




ret

x12

x11

x11

x1

x1

!ddress

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imple Memory!ddressing Modes

ormal +" MemJ"egJ" +egister + species memory address

Aha Pointer dere3erencing in C

mov% (&rcx),&rax

'isplacement'+" MemJ"egJ"N'

+egister + species start o3 memory region

Constant displacement species o5set

mov% (&r'p),&rdx

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Complete Memory !ddressingModes

Most Aeneral 8orm

'+","i,MemJ"egJ"NO"egJ"iN ' : Constant =displacement? , #, or /ytes

+/: Base register: Any o3 0 integer registers

+i: 'nde6 register: Any, e6cept 3or &rsp

S: Scale: , #, , or & 7why these numbers?8

pecial Cases

+","i MemJ"egJ"N"egJ"i

'+","i MemJ"egJ"N"egJ"iN'

+","i, MemJ"egJ"NO"egJ"i

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E6pressionAddressComputation

Address

*6&7rd68

7rd6,rc68

7rd6,rc6,8

*6&*7,rd6,#8

!ddress Computation*$amples

E6pressionAddressComputation

Address

*6&7rd68 *63*** *6& *63**&

7rd6,rc68 *63*** *6** *63**

7rd6,rc6,8 *63*** Q*6** *63**

*6&*7,rd6,#8 #Q*63*** *6&* *6e*&*

rd6 *63***

rc6 *6***

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!ddress ComputationInstruction

lea rc, 'st Src is address mode e6pression

Set st to address denoted /y e6pression

>ses Computing addresses .ithout a memory re3erence

E)g), translation o3 p R


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ome !rithmetic


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ome !rithmetic


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!rithmetic *$pression*$ample

Interesting Instructions lea% : address computation

sal% : shi3t

imul% : multiplication But, only used once

long arit$

(long x, long y, long D)

long t1 ! x5y;

long t2 ! D5t1;

long t ! x5; long t ! y * ;

long t ! t 5 t;

long rval ! t2 * t;

return rval;

"

arit$#

lea% (&rdi,&rsi), &rax add% &rdx, &rax

lea% (&rsi,&rsi,2), &rdx

sal% >, &rdx

lea% (&rdi,&rdx), &rcx

imul% &rcx, &rax

ret


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Machine Programming I:ummary

History of Intel processors andarchitectures Evolutionary design leads to many Guir-s and arti3acts

C, assemly, machine code Je. 3orms o3 visi/le state: program counter,

registers, )))

Compiler must trans3orm statements, e6pressions,procedures into lo."level instruction seGuences

!ssemly Basics: "egisters, operands,

move The 6&0"0 move instructions cover .ide range o3

data movement 3orms

!rithmetic C compiler .ill gure out di5erent instruction

machine basics

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