mac controller implementation
DESCRIPTION
MAC Controller Implementation. Delta Network ASIC Division Project Manager Roger Lin. Content. Project Initialization System Specification Data Flow ASIC Specification ASIC Block Diagram Implementation Target Design Flow. Content. Interface Definition MAC Controller Sub-Block - PowerPoint PPT PresentationTRANSCRIPT
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MAC Controller Implementation
Delta Network ASIC Division
Project Manager
Roger Lin
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Content
• Project Initialization
• System Specification
• Data Flow
• ASIC Specification
• ASIC Block Diagram
• Implementation Target
• Design Flow
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Content
• Interface Definition
• MAC Controller Sub-Block
• Design Phase
• Synthesis Phase
• Backend Phase
• System Engineering
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Project Initialization
• Target : Ethernet Switch• Evolve from Multi-port Bridge• Kapana Network• Market v.s. Technical• Information Re-assembly
– International Showcase– DataBook– Standards
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Product Hierarchic
Internet
RouterBridge
TP-HUB
Intranet
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Application Trend
• Standalone Computer Process
• Database Share Localization
• Centralize Information Maintain
• Internet Access
• Remote Branch Office Handle
• E-Commerce
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Multi-port Bridge
High-EndRISC CPUHigh-EndRISC CPU
MAC ControllerMAC Controller
SRAMSRAM SRAMSRAM SRAMSRAM
CAMCAMEEPROMEEPROM
PHYChipSet
PHYChipSet
PHYChipSet
PHYChipSet
PHYChipSet
PHYChipSet
PHYChipSet
PHYChipSet
RJ-45 BNC RJ-45 RJ-45
SerialPort
MAC ControllerMAC ControllerMAC ControllerMAC Controller MAC ControllerMAC Controller
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System Specification
• Same with Multi-port Bridge– 802.3 MAC– 802.1D Bridging
• Switching Technology– Hardware Forward– Cut Through/Store and Forward– Unique Media Access
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Media Access Control
• Ethernet/802.3
• Token Ring
• Token Bus
• FDDI
LLC
802.3TokenBus
TokenRing
FDDI
10B2 10B5 TP
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Ethernet/802.3Transmit
Deferon ?
Start Tx
Deferon ?
Send jam
Incrementattempts
ComputeBackoff
Deferon ?
Wait backofftime
Txdone ?
Done:excessiveColError
Done:OK
Y
Y
Y
Y
Receive
Rxdone ?
FrameSmall ?(Col)
Recogaddr ?
ValidFCS ?
ValidLengh Field ?
Extra bits ?
Done:Align Error
Done:OK
Done:FCS Error
Done:Length Error
Y
Y
Y
Y
Y
Y
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802.1D Bridging
• Forwarding– Outgoing Port
• Learning– Host Location
• Database– Network Topology
• Spanning Tree– solve loop
RELAY
PHY
MAC MAC
PHY
B B
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Ethernet Switch System Block
Low-EndCPU
Low-EndCPU
MAC Controller
MAC Controller
SRAMSRAMEEPROMEEPROM
PHYChipSet
PHYChipSet
PHYChipSet
PHYChipSet
PHYChipSet
PHYChipSet
PHYChipSet
PHYChipSet
RJ-45 BNC RJ-45 RJ-45
SerialPort
MAC Controller
MAC Controller
MAC Controller
MAC Controller
MAC Controller
MAC Controller SRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAM
Switching Fabric
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Data Flow
• Multi-port Bridge– Concentrate on the High-End CPU– Compute and Move Data by CPU
• Ethernet Switch– Multiple Channel in Switch Fabric– Dynamic Connect by Hardware
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ASIC Specification
• New MAC Controller– Major Function of CSMA/CD– Major Function of Bridging– Interface with Switch Fabric
• Switch Fabric– Crossbar– Share Bus– Share Memory
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New MAC Block Diagram
802.3TransmitController
802.3TransmitController
802.3Receive
Controller
802.3Receive
Controller
Carrier Handle ControllerCarrier Handle Controller
Packet BufferWrite
Controller
Packet BufferWrite
Controller
Packet BufferRead
Controller
Packet BufferRead
Controller
Packet BufferRead
Controller
Packet BufferRead
Controller
Packet BufferWrite
Controller
Packet BufferWrite
Controller
To SwitchInterface
To SwitchInterface
From SwitchInterface
From SwitchInterface
MemoryAccess
Interface
MemoryAccess
Interface
CPU InterfaceController
CPU InterfaceController
BridgingFunction
Controller
BridgingFunction
Controller
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ASIC Block Diagram
• Separate MAC Controller Module– Easy to Re-use/Replace
• Mirror Packet Buffer Controller– Reduce the Corner Case
• Separate Bridging Controller– Easy to Upgrade to Layer 3 Operation
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Implementation Target
• FPGA v.s. ASIC– Low Development Cost– Short Time-to-Market– Easy to Debug– Bad Timing Budget– More Effort to Partition– Proprietary “Generic Logic Block”– Difficult to Estimate
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Design FlowHDL Coding
FunctionalVerification
Synthesis
FloorPlan
Pre-SimulationStatic Timing Analysis
Layout
Post-Simulation(STA)
Easy to Maintain,Re-use and Expand
Critical pointto Success
Library Survey
First Step forLink-to-Layout
Toggle Rate for pattern driven,
STA for SynchronousDesign
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802.3 Receive ControllerHighlights
• Collision Handle– Collision Drop– Late Collision to CPU
• Physical Layer Error Handle - Drop
• Runt Frame Handle - to Packet Buffer
• Long Frame Handle - to Packet Buffer
• Frame Check Sum Error Handle - Drop
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802.3 Receive ControllerHighlights
• Alignment Error Handle - Drop
• Clock Synchronization
• Lose by Packet Alignment
• Wire Speed Receive
• Interface with Packet Buffer Controller
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802.3 Transmit ControllerHighlights
• Collision Handle– Re-transmit Function– Skip Transmit Function
• Jam Function
• Backoff Function– [0, 2ek) where k = min (n, 10)
• Defer Function
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802.3 Transmit ControllerHighlights
• Wire Speed Transmit
• Clock Synchronization
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Interface Definition
Packet BufferWrite
Controller
802.3Receive
Controller
802.3Transmit
Controller
Packet BufferRead
Controller
DATA[7:0]
DATA_VALID
DATA_END
DATA_ERR
TXD[7:0]
TXS[1:0]
TXACK[1:0]
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Interface Definition - RX
Network Data Payload
MII[3:0]
DATA[7:0]
DATA_VALID
DATA_END
Network Data Payload
MII[3:0]
DATA[7:0]
DATA_VALID
DATA_ERR
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Interface Definition - TX
Network Data Payload
MII[3:0]
TXD[7:0]
TXS[1:0]
TXACK[1:0]
Valid Idle Valid
Valid Idle Valid
End
Idle Valid
Network Data Payload
MII[3:0]
TXD[7:0]
TXS[1:0]
TXACK[1:0]
Valid Idle Valid
Valid Idle Re/Sk
Idle
Idle
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RX/TX Block Diagram
MII TXControllerMII TX
ControllerNibble to
WordNibble to
Word
Carrier Handle ControllerCarrier Handle Controller
ClockSynchronization
ClockSynchronization
FIFOFIFO
Word toByte
Word toByte
Byte toWord
Byte toWord
To PacketBuffer
Write Interface
To PacketBuffer
Write Interface
InterfaceCommandDecoder
InterfaceCommandDecoder
CRC CheckCRC Check
BackoffBackoff
DeferDefer
PhyManagement
PhyManagement
StatisticCounterStatisticCounter
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Design Phase
• Clock Domain Partition– Meta Stable
• State Machine– Merely– Moore – One-hot
• Combinational– Product Term
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Design Phase
• Naming Rule
• Exclusion Logic
• Datapath Sharing
• Power Consumption– FlipFlop– Gated Clock– State Bit Transition
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tx_ctrl tx_ctrl (.txack(txack[1:0]),.data_shift(data_shift),.pre_end(pre_end),.vartest4(vartest4),
.txs(txs[1:0]),
.fifo_full(fifo_full),
.err(err),
.retx(retx),
.montx(montx),
.CP(CP), //load 3
.NC(NC));tx_write tx_write (
.tx_cmd_write(tx_cmd_write),
.vartest5(vartest5),
.data_shift(data_shift),
.endtag(tx_cmd_data[8]),
.full(fifo_full),
.err(err),
.CP(CP), //load 3
.NC(NC));
dffex8 DFFEx8_1( .Q(bus1[7:0]),
.QN(),
.D(txd[7:0]), .E(data_shift), .NC(NC), .CP(CP) //load 8);dffex9 DFFEx9_2( .Q(tx_cmd_data[8:0]),
.QN(),
.D({pre_end, bus1[7:0]}), .E(data_shift), .NC(NC), .CP(CP) //load 8);
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assign vartest4 = {data_shift, stateQ};assign
txack[1] = (stateQ == x_start) //idle| (stateQ == x_valid) //valid| (stateQ == x_err) //idle| (stateQ == x_idle), //idle
txack[0] = (stateQ == x_start)| (stateQ == x_err) //idle| (stateQ == x_idle)| (stateQ == x_sktx),
pre_end = (txs == 2'b01) & (txack == 2'b10),data_shift = ((txs == 2'b10) | (txs == 2'b01))
& (txack == 2'b10) & (stateQ == x_valid);
always @(txs orfifo_full orerr orretx ormontx or stateQ)
beginstateD = stateQ;case (stateQ) // synopsys parallel_case
x_start :if (txs == 2'b10 & montx & ~err & ~fifo_full)
stateD = x_valid;x_valid :
if (err)stateD = x_err;
else if (txs == 2'b01)stateD = x_start;
else if (fifo_full)stateD = x_idle;
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x_idle :if (~fifo_full)
stateD = x_valid;x_err :
if (retx)stateD = x_retx;
else if (~retx)stateD = x_sktx;
x_retx :stateD = x_start;
x_sktx :stateD = x_start;
default :stateD = x_start;
endcaseend
//----------------------FLIP FLOP AREA------------------always @(
posedge CP or negedge NC )
beginif (~NC)
stateQ[2:0] = #2 3'h0;else
stateQ[2:0] = #2 stateD[2:0];end//DFFC_d1 DFF0 (.Q(stateQ[0]), .D(stateD[0]), .CP(CP), .NC(NC));//DFFC_d1 DFF1 (.Q(stateQ[1]), .D(stateD[1]), .CP(CP), .NC(NC));//DFFC_d1 DFF2 (.Q(stateQ[2]), .D(stateD[2]), .CP(CP), .NC(NC));
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Synthesis Phase
• Strategy– Bottom Up– Synthesis - Characterize - Re-synthesis
• Critical Path
• Fine Tune Constraint
• Register Re-timing
• Re-code RTL
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Backend Phase
• Floor Plan
• ECO ( Engineering Change Order )
• Clock Skew
• Layout Density
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System Engineering
• Test Environment
• Q & A