m5235evb user’s manual - nxp · 2016. 11. 23. · m5235evb user’s manual, rev. 2 2 freescale...

Freescale SemiconductorUser’s Manual

M5235EVBUMRev. 2, 08/2007

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1M523xEVB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 MCF5235 Microprocessor . . . . . . . . . . . . . . . . . . . . 42.2 System Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.3 Support Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.4 Communication Ports . . . . . . . . . . . . . . . . . . . . . . 142.5 Connectors and User Components . . . . . . . . . . . . 21Initialization and Setup . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1 System Configuration . . . . . . . . . . . . . . . . . . . . . . 263.2 Installation and Setup . . . . . . . . . . . . . . . . . . . . . . 273.3 System Power-up and Initial Operation . . . . . . . . . 323.4 Using The BDM Port . . . . . . . . . . . . . . . . . . . . . . . 33Using the Monitor/Debug Firmware. . . . . . . . . . . . . . . . 33

4.1 What is dBUG? . . . . . . . . . . . . . . . . . . . . . . . . . . . 334.2 Operational Procedure . . . . . . . . . . . . . . . . . . . . . 344.3 Command Line Usage. . . . . . . . . . . . . . . . . . . . . . 364.4 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.5 TRAP #15 Functions . . . . . . . . . . . . . . . . . . . . . . . 71Configuring dBUG for Network Downloads . . . . . . . . . . 73

5.1 Required Network Parameters . . . . . . . . . . . . . . . 735.2 Configuring dBUG Network Parameters . . . . . . . . 745.3 Troubleshooting Network Problems . . . . . . . . . . . 75Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Evaluation Board BOM . . . . . . . . . . . . . . . . . . . . . . . . . 93

M5235EVB User’s Manualby: Microcontroller Division

1 PrefaceEMC information:

• This product, as shipped from the factory with associated power supplies and cables, has been tested and meets with requirements of EN5022 and EN 50082-1: 1998 as a CLASS A product.

• This product is designed and intended for use as a development platform for hardware or software in an educational or professional laboratory.

• In a domestic environment this product may cause radio interference in which case you may be required to take adequate measures.

• Anti-static precautions must be adhered to when using this product.

• Attaching additional cables or wiring to this product or modifying the products operation from the factory default as shipped may effect its performance and also cause interference with

12

3

4

5

67

© Freescale Semiconductor, Inc., 2007. All rights reserved.

other apparatus in the immediate vicinity. If such interference is detected, suitable mitigating measures should be taken.

WARNINGThis board generates, uses, and can radiate radio frequency energy and, if not installed properly, may cause interference to radio communications. As temporarily permitted by regulation, it has not been tested for compliance with the limits for class a computing devices pursuant to Subpart J of Part 15 of FCC rules, which are designed to provide reasonable protection against such interference. Operation of this product in a residential area is likely to cause interference, in which case you, at your own expense, are required to correct the interference.

2 M523xEVBThis document details the setup and configuration of the ColdFire M523xEVB evaluation board (hereafter referred to as the EVB). The EVB is intended to provide a mechanism for easy customer evaluation of the MCF523x family of ColdFire microprocessors and to facilitate hardware and software development. The EVB can be used by software and hardware developers to test programs, tools, or circuits without having to develop a complete microprocessor system themselves. All special features of the MCF523x family are supported.

The heart of the evaluation board is the MCF5235. All the other M523x family members have a subset of the MCF5235 specification and therefore can be fully emulated using the MCF5235 device. Table 1 below details the full product family.

All of the devices in the same package are pin-compatible.

The EVB provides low cost software testing using a ROM-resident debug monitor, dBUG, programmed into the external flash device. Operation allows you to load code in the on-board RAM, execute applications, set breakpoints, and display/modify registers or memory. No additional hardware or software is required for basic operation.

Table 1. M523x Product Family

Part Number Package eTPU FEC Crypto CAN

MCF5232CAB80 160 QFP 16-channel No No 1

MCF5232CVM100 196 MAPBGA 16-channel No No 1




MCF5234CVM100 256 MAPBGA 16-channel Yes No 1

MCF5234CVM150 256 MAPBGA 16-channel Yes No 1

MCF5235CVM100 256 MAPBGA 16-channel Yes Yes 2

MCF5235CVM150 256 MAPBGA 16-channel Yes Yes 2

M5235EVB User’s Manual, Rev. 2

2 Freescale Semiconductor

Specifications:• Freescale MCF5235 Microprocessor (150 MHz max core frequency)• External Clock source: 25 MHz • Operating temperature: 0°C to +70°C• Power requirement: 7–14V DC @ 300 ma Typical• Power output: 5V, 3.3V and 1.5V regulated supplies• Board Size: 10.00 × 5.40 inches, 8 layers

Memory Devices:• 16-Mbyte SDRAM• 2-Mbyte (512K × 16) page mode flash or 4-Mbyte (512K × 32) page mode flash• 1-Mbyte MRAM • 64-Kbyte SRAM internal to MCF523x device

Peripherals:• Ethernet port 10/100Mbps (dual-speed Fast Ethernet transceiver with MII)• UART0 (RS-232 serial port for dBUG firmware)• UART1 (auxiliary RS-232 serial port)• UART2 (auxiliary1 RS-232 serial port jumper selectable with FlexCAN1)• Enhanced Time Processor Unit (eTPU)• I2C interface• QSPI interface to ADC• FlexCAN0 interface• USB Host and Device Interface• BDM/JTAG interface

User Interface:• Reset logic switch (debounced)• Boot logic selectable (dip switch)• Abort/IRQ7 logic switch (debounced)• PLL Clocking options—Oscillator, Crystal or SMA for external clocking signals• LEDs for power-up indication, general purpose I/O, and timer output signals• Expansion connectors for daughter card • UNI-3 connector for motor control cards

Software:• Resident firmware package that provides a self-contained programming and operating

environment (dBUG)


Freescale Semiconductor 3

*A jumper chooses between 16 eTPU channels and Ethernet or 32 eTPU channels and no Ethernet

Figure 1. M523xEVB Block Diagram

2.1 MCF5235 MicroprocessorThe microprocessor used on the EVB is the highly integrated Freescale MCF5235 32-bit ColdFire variable-length RISC processor. The MCF5235 implements a Version 2 ColdFire core with a maximum core frequency of 150 MHz and external bus speed of 75 MHz. Features of the MCF5235 include:

• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC) providing 144 (Dhrystone 2.1) MIPS @ 150 MHz

• eTPU with 16 or 32 channels, 6 Kbytes of code memory and 1.5 Kbytes of data memory with debug support

• 64 Kbytes of internal SRAM• External bus speed of one half the CPU operating frequency (75 MHz bus @ 150 MHz core)• 10/100 Mbps bus-mastering Ethernet controller

ColdFire MCF523X

RS-232 transceivers (2)

DB-9 (2) connector

Ethernet Transceiver*

RJ-45 connector

25 MHz Osc.

(4) 60 pin Daughter Card expansion connectors

Dat

a [3

1:0]

Add

ress

[23:

0]

Con

trol S

igna

ls

SDRAM16 Mbytes

Flash2-4 Mbytes

ASRAM 1 Mbyte

Perip

hera

l sig

nals

CAN Transceiver DB-9 connector

RS-232 / CAN Transceiver

DB-9 connector

26-pin Debug Header

Clocking circuitry

25 MHz Osc.

ADC

USB 2.0 Host & Device

ETPU Headers*

MRAM1 Mbyte



• 8 Kbytes of configurable instruction/data cache• Three universal asynchronous receiver/transmitters (UARTs) with DMA support• Controller area network 2.0B (FlexCAN module)

— Optional second FlexCAN module multiplexed with the third UART• Inter-integrated circuit (I2C) bus controller• Queued serial peripheral interface (QSPI) module• Hardware cryptography accelerator (optional)

— Random number generator— DES/3DES/AES block cipher engine— MD5/SHA-1/HMAC accelerator

• Four channel 32-bit direct memory access (DMA) controller• Four channel 32-bit input capture/output compare timers with optional DMA support• Four channel 16-bit periodic interrupt timers (PITs)• Programmable software watchdog timer• Interrupt controller capable of handling up to 126 interrupt sources• Clock module with Phase Locked Loop (PLL)• External bus interface module including a 2-bank synchronous DRAM controller• 32-bit non-multiplexed bus with up to 8 chip select signals that support page-mode flash memories

The MCF5235 communicates with external devices over a 32-bit wide data bus, D[31:0]. The MCF5235 can address a 32-bit address range. However, only 24 bits are available on the external bus, A[23:0]. There are internally generated chip selects to allow the full 32-bit address range to be selected. There are regions that can be decoded to allow supervisor, user, instruction, and data each to have the 32-bit address range.

All the processor's signals are available via daughter card expansion connectors. Refer to the Section 6, “Schematics” for their pin assignments.

The MCF5235 processor supports BDM and JTAG. These ports are multiplexed and can be used with third party tools to allow you to download code to the board. The board is configured to boot up in the normal/BDM mode of operation. The BDM signals are available at the port labeled BDM.



Figure 2 shows the MCF5235 processor block diagram.

Figure 2. MCF5235 Block Diagram

64 KbytesSRAM

(8Kx16)x4

EIM

ETHERNET

V2 ColdFire CPU

INTC0

Watchdog

PIT0

JTAGTAP

CACHE(1Kx32)x2

PIT1 PIT2 PIT3

4 CH DMA

UART0

UART1 I2C QSPI

DTIM0

DTIM1

DTIM2

DTIM3

Timer

PAD

I

PLLCLKGEN

UART2

8 Kbytes

EdgePort

SDRAMC

CHIP

EBI

SELECTS

(To/From PADI)

(To/From

FAST

CONTROLLER(FEC)

FEC

TnIN

TnOUT

UnRXD

UnTXD

SDA

SCL

SDRAMC

QSPI

UnRTS

UnCTS

PORTSCIM(GPIO)

D[31:0]

A[23:0]

R/W

CS[3:0]

TA

TSIZ[1:0]

TEA

BS[3:0]

DIV EMAC

DREQ[2:0]

INTC1Arbiter

(To/From SRAM backdoor)

(To/From Arbiter)

SKHA

RNGA

MDHA

(To/From PADI)

CryptographyModules

DACK[2:0]

BD

M

(To/From INTC)

MU

X

PADI)

JTAG_EN



2.2 System MemoryThe following diagram shows the external memory implementation on the EVB.

Figure 3. External Memory Scheme

NOTEThe external bus interface signals to the external MRAM and flash (and USB) are buffered. This is in order not to exceed the maximum output load capacitance of the microprocessor on the EVB. The signals to the expansion connectors remain unbuffered to provide a true interface.

2.2.1 External Flash

The EVB is fitted with a single 512K × 16 page-mode flash memory (U19) giving a total memory space of 2Mbytes. Alternatively, a footprint is available for you to upgrade this device to a 512K × 32 page-mode flash memory (U35), doubling the memory size to 4 Mbytes. U19 or U35 should be fitted on the board. Both devices cannot be populated at the same time. Refer to the specific device data sheet and sample software provided for configuring the flash memory.

NOTEThe debug monitor firmware is installed in this flash device. Development tools or your application programs may erase or corrupt the debug monitor. If the debug monitor becomes corrupted and it’s operation is desired, the firmware must be programmed into the flash by applying a development port tool such as BDM. Use caution to avoid this situation. The M523xEVB dBUG debugger/monitor firmware is programmed into the lower sectors of flash (0xFFE0_0000–0xFFE2_FFFF for 2 Mbytes of flash or 0xFFC0_0000–0xFFC2_FFFF for 4 Mbytes of flash).

ExpansionConnectors

SDRAM(16 Mbytes)

MRAM(1 Mbyte)

Flash(512K × 16

or512K × 32)

BuffersMPU

Data

Address

Control



By default with U19 fitted on the EVB, jumper 64 (JP64) provides an alternative hardware mechanism for write protection.

If you replaced U19 with the 32-bit flash device (U35), jumper 31 (JP31) has the same functionality as JP64. U35 also has it’s own hardware write protect pin (C5) that protects the bottom boot sector when pulled to ground.

2.2.2 SDRAM

The EVB is populated with 16 Mbytes of SDRAM. This is done with two devices (Micron MT48LC4M16A2TG) each with a 16 bit data bus. Each device is organized as 1 Meg × 16 × 4 banks with a 16 bit data bus. One device stores the upper 16-bit word and the other the lower 16 bit word of the MCF523x 32 bit data bus.

2.2.3 MRAM

The EVB is populated with two 512K × 16 MRAM devices (Freescale MR2A16A). Also see Section 2.2.5, “M523xEVB Memory Map”.

2.2.4 Internal SRAM

The MCF5235 processor has 64-Kbytes of internal SRAM memory that may be used as data or instruction memory. This memory is mapped to 0x2000_0000 and configured as data space, but is not used by the dBUG monitor except during system initialization. After system initialization is complete, the internal memory is available to you. The memory is relocatable to any 32-Kbyte boundary within the processor’s four gigabyte address space.

2.2.5 M523xEVB Memory Map

Interface signals to support the interface to external memory and peripheral devices are generated by the memory controller. The MCF5235 supports eight external chip selects: CS[1:0] are used with external memories, CS2 is used for the USB controller, and CS[7:3] are easily accessible to you via the daughter card expansion connectors. CS0 also functions as the global (boot) chip-select for booting out of external flash.

Because the MCF5235 chip selects are fully programmable, the memory banks may be located at any 64-Kbyte boundary within the processor’s four gigabyte address space.

The default memory map for this board, as configured by the debug monitor, is found in Table 2. The internal memory space of the MCF5235 is detailed further in the MCF5235 Reference Manual. Chip selects 0 and 1 can be changed by your software to map the external memory in different locations, but the chip select configuration such as wait states and transfer acknowledge for each memory type should be maintained.

Chip Select Usage:External flash Memory CS0External MRAM Memory CS1



Table 2 shows the M523xEVB memory map.

2.2.5.1 Reset Vector Mapping

Asserting the reset input signal to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered.

The reset exception places the processor in the supervisor mode by setting the S-bit and disables tracing by clearing the SR[T] bit. This exception also clears the M bit and sets the processor’s interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero (0x0000_0000). The control registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly to the processor are disabled.

After the processor is granted the bus, it then performs two longword read bus cycles. The first longword at address 0x0000_0000 is loaded into the stack pointer and the second longword at address 0x0000_0004 is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault halted state.

The memory size that the MCF5235 accesses at address 0x0000_0000 is determined at reset by sampling D[20:19].

2.3 Support Logic

2.3.1 Reset Logic

The reset logic provides system initialization. Reset occurs at power-on or by asserting RESET via SW6.

Table 2. Default M523xEVB Memory Map

Address Range Signal and Device

0x0000_0000–0x00FF_FFFF 16 Mbyte SDRAM

0x2000_0000–0x2000_FFFF 64 Kbytes Internal SRAM

0x3000_0000–0x300F_FFFF External MRAM

0xFFE0_0000–0xFFFF_FFFFor

0xFFC0_0000–0xFFFF_FFFF

2 Mbytes External Flashor

4 Mbytes External Flash

Table 3. D[20:19] External Boot Chip Select Configuration

D[20:19] Boot Device/Data Port Size

00 External (32-bit)


10 External (8-bit)




dBUG configures the MCF5235 microprocessor internal resources during initialization.• Instruction cache is invalidated and disabled• Vector base register (VBR) contains an address that initially points to the flash memory• Contents of the exception table are written to address 0x0000_0000 in the SDRAM• Software watchdog timer is disabled• Bus monitor is enabled• Internal timers are placed in a stop condition• Interrupt controller registers are initialized with unique interrupt level/priority pairs

If the external RCON pin is asserted during reset (SW7-1 ON), then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins. See tables below on settings for reset configurations.

If RCON is not asserted during reset (SW7-1 OFF), the chip configuration and the reset configuration pin functions after reset are determined by the RCON register or fixed defaults, regardless of the states of the external data pins.

Table 4. SW7-1 RCON

SW7-1 Reset Configuration

OFF RCON not asserted, Default Chip configuration or RCON register settings

ON RCON is asserted, Chip functions, including the reset configuration after reset, are configured according to the levels driven onto the external data pins.

Table 5. SW7-2 JTAG_EN

SW1-2 JTAG Enable

OFF JTAG interface enabled

ON BDM interface enabled

Table 6. SW7-[4:3] Encoded Clock Mode

SW7-3 SW7-4 Clock Mode

OFF OFF External clock mode- (PLL disabled)

OFF ON 1:1 PLL

ON OFF Normal PLL mode with external clock reference

ON ON Normal PLL mode w/crystal oscillator reference



2.3.2 Clock Circuitry

There are three options to supply the clock to the CPU. These options are configured by setting JP[35:37].

Table 7. SW7-5 Chip Configuration Mode

SW7-5 RCON (SW7-1) Mode

OFF ON Reserved

ON ON Master

X OFF Master

Table 8. SW7-[7:6] Boot Device

SW7-6 SW7-7 RCON (SW7-1) Boot Device

OFF OFF ON External (32-bit)

OFF ON ON External (8-bit)

ON OFF ON External (16-bit)

ON ON ON External (32-bit)

X X OFF External (32-bit)

Table 9. SW7-8 Bus Drive Strength

SW7-8 RCON (SW7-1) Drive Strength

OFF ON Partial Bus Drive

ON ON Full Bus Drive

X OFF Partial Bus Drive

Table 10. SW7-[10:9] Address/Chip Select Mode

SW7-9 SW7-10 RCON (SW7-1) Mode

OFF OFF ON PADDR[7:5] = CS[6:4]

OFF ON ON PADDR[7] = CS6, PADDR[6:5] = A[22:21]

ON OFF ON PADDR[7:6] = CS[6:5], PADDR[5] = A21

ON ON ON PADDR[7:5] = A[23:21]

X X OFF PADDR[7:5] = A[23:21]

Table 11. M523xEVB Clock Source Selection

JP35 JP36 JP37 Clock Selection

1-2 1-2 ON 25 MHz Oscillator (default setting)

2-3 1-2 ON 25 MHz External Clock

X 2-3 OFF 25 MHz Crystal (not populated)



The 25-MHz oscillator (U23) also feeds the Ethernet chip (U11).

There is also a 12-MHz crystal feeding the USB controller (U33).

2.3.3 Watchdog Timer

The dBUG firmware does not enable the watchdog timer on the MCF5235.

2.3.4 Exception Sources

The ColdFire family of processors supports seven levels of interrupt priorities. When the processor receives an interrupt with a higher priority than the current interrupt mask (in the status register), it performs an interrupt acknowledge cycle at the end of the current instruction cycle. This interrupt acknowledge cycle tells the interrupt source that the request is acknowledged and the source should provide the vector number to indicate where the service routine for this interrupt level is located. If the interrupt source is not capable of providing a vector, its interrupt should be set up as an auto-vector interrupt that directs the processor to a predefined entry in the exception table (refer to the MCF5235 Reference Manual).

The processor goes to an exception routine via the exception table. This table is stored in the flash EEPROM and its address location is stored in the VBR. The dBUG ROM monitor writes a copy of the exception table into the RAM starting at 0x0000_0000. To set an exception vector, place the address of the exception handler in the appropriate vector in the vector table and then point the VBR to 0x0000_0000.

The MCF5235 microprocessor has seven external interrupt request lines IRQ[7:1]. The interrupt controller is capable of providing up to 63 interrupt sources. These sources are:

• External interrupt signals IRQ[7:1] (EPORT)• Software watchdog timer module• Timer modules• UART modules 0, 1 and 2• I2C module• DMA module• QSPI module• FEC module• PIT• Security module• FlexCAN0 and FlexCAN1• eTPU

All external interrupt inputs are edge sensitive. The active level is programmable. An interrupt request must be held valid until an IACK cycle starts to guarantee correct processing. Each interrupt input can have its priority programmed by setting the xIPL[2:0] bits in the interrupt control registers except interrupts 1–7 because they have a fixed priority.



No interrupt sources should have the same level and priority as another. Programming two interrupt sources with the same level and priority results in undefined operation.

The M523xEVB hardware uses IRQ7 to support the ABORT function using the ABORT switch (SW5). This switch is used to force an interrupt (level 7, priority 3) if your program execution should be aborted without issuing a reset (refer to Section 4, “Using the Monitor/Debug Firmware”, for more information on ABORT). Because the ABORT switch is not capable of generating a vector in response to a level seven interrupt acknowledge from the processor, the dBUG programs this interrupt request for autovector mode.

Refer to the MCF5235 Reference Manual for more information about the interrupt controller.

2.3.5 TA Generation

The processor starts a bus cycle by asserting CSx with the other control signals. The processor then waits for a transfer acknowledgment (TA) from within (auto-acknowledge, AA mode) or from the externally addressed device before it can complete the bus cycle. TA is indicates the completion of the bus cycle. It also allows devices with different access times to communicate with the processor properly asynchronously.

The MCF5235 processor, as part of the chip-select logic, has a built-in mechanism to generate TA for all external devices that cannot generate this signal. For example, the flash ROM cannot generate a TA signal. The chip-select logic is programmed by the dBUG ROM monitor to generate TA internally after a pre-programmed number of wait states. To support future expansion of the M523xEVB, the TA input of the processor is also connected to the processor expansion bus (J9, pin 44). This allows any expansion boards to assert this line to provide a TA signal to the processor. On the expansion boards this signal should be generated through an open collector buffer with no pull-up resistor; a pull-up resistor is included on this board. All TA signals from expansion boards should be connected to this line.

2.3.6 User’s Program

JP64 on the 16-Mbit flash (U19) or JP31 if using 32-Mbit flash (U35) allows you to test code from boot/POR without having to overwrite the ROM monitor.

When the jumper is set between pins 1 and 2, the behavior of the system is normal: dBUG boots and then runs from 0xFFE0_0000 (0xFFC0_0000). When the jumper is set between pins 2 and 3, the board boots from the top half of the flash (0xFFF0_0000).

Procedure:1. Compile and link as though the code was to be placed at the base of the flash.2. Set up the jumper JP64 (JP31) for normal operation, pin 1 connected to pin 2. 3. Download to SDRAM. (If using serial or Ethernet, start the ROM monitor first. If using BDM via

a wiggler cable, download first, then start ROM monitor by pointing the program counter (PC) to 0xFFE0_0400 (0xFFC0_0400) and run.)

4. In the ROM monitor, execute the 'FL write <dest> <src> <bytes>' command.5. Move jumper JP64 (JP31) to pin 2 connected to pin 3 and push the reset button (SW6). Your code

should now be running from reset/POR.



2.4 Communication PortsThe EVB provides external communication interfaces for two UART serial ports, a UART/FlexCAN1 port, FlexCAN0 port, QSPI, I2C port, 10/100T Ethernet port, eTPU port (including UNI3 and HS/ENCO connectors for auxiliary motor control cards), USB host port, USB device port, and BDM/JTAG port.

2.4.1 UART0 and UART1 Ports

The MCF5235 device has three built in UARTs, each with its own software-programmable baud rate generator. Two of these UART interfaces are brought out to RS232 transceivers. One channel is the ROM monitor to terminal output and the other is available to you. The ROM monitor programs the interrupt level for UART0 to level 3, priority 2 and autovector mode of operation. The interrupt level for UART1 is programmed to level 3, priority 1 and autovector mode of operation. The signals from these channels are available on expansion connectors J7 and J8. The UART0 and UART1 signals are passed through the RS-232 transceivers (U30) & (U31) and are available on DB-9 connectors (P4) and (P5).

Refer to the MCF5235 Reference Manual for programming the UARTs and their register maps.

2.4.2 UART2/FlexCAN1 Port

The third UART on the MCF5235 is multiplexed with the second FlexCAN module (FlexCAN1). The functionality of these ports is jumper-selectable on the EVB. Table 12 shows the jumper configuration to activate UART2 or FlexCAN1.

The signals of UART2 are passed through RS-232 transceiver U32 and are jumper-selectable (see Table 12) on DB-9 connector P6.

The CAN1TX and CAN1RX signals from FlexCAN1 are brought out to a 3.3-V CAN transceiver (Texas Instruments SN65HVD230D) and are jumper-selectable (see Table 12) on DB-9 connector P6. Jumpers JP3 and JP4 control the CAN hardware configuration.

Table 12. UART2/FlexCAN1 Jumper Configuration

Jumper UART2 Setting FlexCAN1 Setting

JP7 1-2 2-3

JP12 1-2 2-3

JP25 2-3 X

JP26 2-3 X

JP50 2-3 1-2

JP51 2-3 1-2

JP52 2-3 1-2



2.4.3 FlexCAN0 Port

The EVB provides one dedicated CAN transceiver. The CAN0TX and CAN0RX signals are brought out to a 3.3V CAN transceiver (Texas Instruments SN65HVD230D). Jumper JP1 and JP2 control the CAN hardware configuration.

The CANL and CANH signals are brought out from the CAN transceiver to a female DB-9 connector (P1) in the configuration below.

2.4.4 10/100T Ethernet Port

The MCF5235 microprocessor populated on the EVB is a superset device of the MCF523x family. The upper 16 eTPU channels are multiplexed with the ethernet port giving you the choice of using the full 32-channels of eTPU or 16-channels of eTPU with the Fast Ethernet controller (FEC) activated. Pin M4 on the MCF5235 configures the internal functionality of these 16 pins. If you are using the FEC, pin M4 must be pulled low by setting SW7-11 to the ON position.

These 16 pins are also jumper-selectable between the eTPU and the FEC to isolate the external circuitry required to implement the functionality of these modules. Table 16 lists the appropriate jumper settings to enable eTPU or FEC functionality on these pins.

The MCF5235 device performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions. The MCF5235 Ethernet controller requires an external interface adaptor and

Table 13. FlexCAN1 Jumper Configuration

Jumper Function ON OFF

JP3 Transceiver mode Standby High Speed(No Slope Control)

JP4 CAN Termination Terminating resistor between CANL and CANH

No terminating resistor

Table 14. FlexCAN0 Jumper Configuration

Jumper Function ON OFF

JP1 Transceiver mode Standby High Speed (No Slope Control)

JP2 CAN Termination Terminating resistor between CANL and CANH

No terminating resistor

Table 15. CAN Bus Connector Pinout

DB-9 pin Signal

1,4-6,7-9 Not Connected

2 CANL

3 Ground

7 CANH



transceiver function to complete the interface to the ethernet media. The MCF5235 Ethernet module also features an integrated fast (100baseT) Ethernet media access controller (MAC).

The Fast Ethernet controller (FEC) incorporates the following features:• Support for three different Ethernet physical interfaces:

— 100-Mbps IEEE 802.3 MII— 10-Mbps IEEE 802.3 MII— 10-Mbps 7-wire interface (industry standard)

• IEEE 802.3 full duplex flow control• Programmable max frame length supports IEEE 802.1 VLAN tags and priority• Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate of

50 MHz• Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of

25 MHz• Retransmission from transmit FIFO following a collision (no processor bus utilization)• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address

recognition rejects (no processor bus utilization)• Address recognition

— Frames with broadcast address may be always accepted or always rejected— Exact match for single 48-bit individual (unicast) address— Hash (64-bit hash) check of individual (unicast) addresses— Hash (64-bit hash) check of group (multicast) addresses— Promiscuous mode

For more details see the MCF5235 Reference Manual. The on-board ROM monitor is programmed to allow you to download files from a network to memory in different formats. The current compiler formats supported are S-Record, COFF, ELF or Image.

Table 16. Ethernet/eTPU Jumper Configuration

Jumper PinEthernet Setting

Ethernet Signal

eTPU Setting

eTPU Channel

JP5 D5 2-3 ERXER 1-2 23

JP9 C5 2-3 ETXCLK 1-2 22

JP10 B5 2-3 ETXD2 1-2 18

JP11 A5 2-3 ETXD1 1-2 17

JP13 D6 2-3 ETXEN 1-2 21

JP14 C6 2-3 ETXER 1-2 20

JP15 B6 2-3 ETXD3 1-2 19

JP16 C4 2-3 ERXD0 1-2 24

JP17 B7 2-3 ETXD0 1-2 16

JP18 C3 2-3 ERXD1 1-2 25



2.4.5 eTPU

The eTPU is an intelligent programmable I/O controller with its own core and memory system, allowing it to perform complex timing and I/O management independently of the CPU. The eTPU is essentially a co-processor designed for timing control, I/O handling, serial communications, motor control. and engine control applications and accesses data without the host CPU’s intervention. Consequently, the host CPU setup and service times for each timer event are minimized or eliminated.

The eTPU is an enhanced version of the TPU module implemented on the MC68332 and MPC500 products. Enhancements of the eTPU include a more powerful processor that handles high-level C code efficiently and has more functionality and increased performance. Although there is no compatibility at the microcode level, the eTPU maintains several features of older TPU versions and is conceptually almost identical. The eTPU library is a superset of the standard TPU library functions modified to take advantage of enhancements in the eTPU. These, along with a C compiler, make it relatively easy to port older applications. By providing source code for the Freescale library, it is possible for the eTPU to support your own function development.

The eTPU has up to 32 timer channels in addition to having 6 Kbytes of code memory and 1.5 Kbytes of data memory that stores software modules downloaded at boot time and that can be mixed and matched as required for any specific application.

As mentioned in Section 2.4.4, “10/100T Ethernet Port,” the upper 16-channels of the eTPU are multiplexed with the Fast Ethernet controller. Refer to Table 16 to set the appropriate jumpers to enable 16 or 32-channels. To configure the device to operate with the top 16-channels of the eTPU activated, pin M4 must be pulled high by setting SW7-11 to the OFF position.

All 32 eTPU channels are available on a 0.1 2x20 Molex connector providing easy access to the eTPU.

JP19 D4 2-3 ERXD2 1-2 26

JP20 D3 2-3 ERXD3 1-2 27

JP21 E3 2-3 ERXCLK 1-2 29

JP22 E4 2-3 ERXDV 1-2 28

JP23 F3 2-3 ECOL 1-2 31

JP24 F4 2-3 ECRS 1-2 30

Table 17. eTPU Header Pin Assignment

Pin eTPU Signal Pin eTPU Signal

1 +3.3V 2 +5V

3 TPUCH16 4 UTPUODIS

5 TPUCH17 6 LTPUODIS

7 TPUCH18 8 TPUCH0

Table 16. Ethernet/eTPU Jumper Configuration (continued)

Jumper PinEthernet Setting

Ethernet Signal

eTPU Setting

eTPU Channel



There is a UNI3 connector and HS/ENCO connector on the EVB for connection to an auxiliary card. The auxiliary card is intended for evaluation of the eTPU functionality.

2.4.6 BDM/JTAG Port

The MCF5235 processor has a background debug mode (BDM) port, which supports real-time trace and real-time debug. The signals necessary for debug are available at connector J1 as shown in Figure 4.

The BDM connector can also be used to interface to JTAG signals. On reset, the JTAG_EN signal selects between multiplexed debug module and JTAG signals. See Table 5.

9 TPUCH19 10 TPUCH1

11 TPUCH20 12 TPUCH2












35 GND 36 TPUCH14

37 TCRCLK 38 TPUCH15

39 GND 40 GND

Table 17. eTPU Header Pin Assignment (continued)

Pin eTPU Signal Pin eTPU Signal



Figure 4. J1- BDM Connector Pin Assignment

2.4.7 I2C

The MCF5235’s I2C module includes the following features:• Compatibility with the I2C bus standard version 2.1• Multi-master operation• Software programmable for one of 50 different clock frequencies• Software selectable acknowledge bit• Interrupt driven byte by byte data transfer• Arbitration-lost interrupt with automatic mode switching from master to slave• Calling address identification interrupt• Start and stop signal generation and detection• Repeated start signal generation• Acknowledge bit generation and detection• Bus busy detection

Please see the MCF5235 Reference Manual for more details. The I2C signals from the MCF5235 device are brought out to expansion connector J13.

The I2C functionality of the MCF5235 is multiplexed on the same pins as the QSPI. Jumpers JP6 and JP8 are used to connect/disconnect the I2C signals, SDA and SCL. To enable I2C set JP6 and JP8 between pins 2 and 3.

1

3

5

7

9

11

13

15

17

19

21

23

25

2

4

6

8

10

12

14

16

18

20

22

24

26

BKPT

DSCLK

Developer Reserved

DSI

DSO

PST3

PST1

DDATA3

DDATA1

GND

Freescale Reserved

PSTCLK

TA

GND

GND

RESET

GND

PST2

PST0

DDATA2

DDATA0

Freescale Reserved

GND

Core Voltage

Developer Reserved

I/O or Pad Voltage



2.4.8 Queued Serial Peripheral Interface (QSPI)

The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to 16 stacked transfers at one time, minimizing CPU intervention between transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers.

Functionality is very similar to the QSPI portion of the QSM (queued serial module) implemented in the MC68332 processor.

• Programmable queue to support up to 16 transfers without user intervention• Supports transfer sizes of eight to 16 bits in one bit increments• Four peripheral chip-select lines for control of up to 15 devices• Baud rates from 147.1-Kbps to 18.75-Mbps at 75 MHz.• Programmable delays before and after transfers• Programmable QSPI clock phase and polarity• Supports wrap-around mode for continuous transfers

Please see the MCF5235 Reference Manual for more details. The QSPI signals from the MCF5235 device are brought out to expansion connector J12.

Some of the QSPI signals are multiplexed with the I2C module. Set JP6 and JP8 between pins 1 and 2 to enable the QSPI module.

The EVB features an analog-to-digital converter (ADC) interfaced to the CPU via the QSPI. The ADC uses QSPI chip select 0. This chip select has a jumper that can be removed if you are not using the ADC and wish to connect QSPI_CS0 to an alternate device.

2.4.9 USB Host and Device

The EVB features a USB controller interfaced externally to the MCF5235 via the DMA and external bus modules. The USB controller can be configured to run in Host or Device mode.

There is a series A connector (host) and a series B connector (device) populated on the EVB. Either can be used depending on whether the USB controller is configured to run in host or device mode. Set JP56 between pins 2 and 3 to configure the controller for host mode or between pin 1 and 2 to configure the controller for device mode.

The USB controller also has On-The-Go (OTG) functionality. There is a footprint on the EVB for an OTG Mini-AB connector if you want to use USB OTG. If using OTG, JP55 must be fitted.

For more details see the Philips Semiconductor datasheet for the ISP1362 USB OTG controller.

There are a series of jumpers connected to the USB controller allowing you to disconnect the DMA and interrupt signals between the CPU and the USB controller if the USB controller is not in use. This gives you access to the DMA timer module channels 1 and 2 and an extra interrupt signal. Table 18 details these jumper settings.



2.5 Connectors and User Components

2.5.1 Daughter Card Expansion Connectors

Four, 60-way SMT connectors (J7, J8, J9 and J10) provide access to all MCF5235 signals. These connectors are ideal for interfacing to a custom daughter card or for simple probing of processor signals. Below is a pinout description of these connectors.

Table 18. USB DMA Enable and Disable Settings

Jumper Functionality when Jumper is Fitted Functionality when Jumper is NOT Fitted

JP57 USB DMA request signal DMA Timer 1 input enabled

JP58 USB DMA request signal DMA Timer 2 input enabled

JP59 USB DMA acknowledge signal DMA Timer 2 output enabled

JP60 USB DMA acknowledge signal DMA Timer 1 output enabled

JP61 DACK1 not in use - pulled high DMA acknowledge 1 enabled

JP62 Interrupt 4 enabled for USB Interrupt 4 disabled from USB

JP63 DACK2 not in use - pulled high DMA acknowledge 2 enabled

Table 19. J7

Pin Signal Pin Signal

1 +5V 2 +5V

3 +3.3V 4 +3.3V

5 +3.3V 6 +3.3V

7 GND 8 GND

9 TPUCH24 10 TPUCH6







23 TPUCH21 24 GND

25 TPUCH16 26 EMDIO

27 U2CTS 28 EMDC

29 I2C_SCL 30 I2C_SDA

31 QSPI_SCK 32 QSPI_DIN

33 BS3 34 QSPI_DOUT



35 BS2 36 QSPI_PCS0

37 BS1 38 SD_SCKE

39 BS0 40 CAN1RX

41 U2RTS 42 U2RXD

43 QSPI_PCS1 44 U1CTS

45 U1RTS 46 CAN1TX

47 U1RXD 48 U2TXD

49 U1TXD 50 CS2

51 CS3 52 CS7

53 CS6 54 CS5

55 CS1 56 CS0

57 CS4 58 A23

59 GND 60 GND

Table 20. J8


1 +5V 2 +1.5V

3 +3.3V 4 +3.3V

5 TPUCH8 6 TPUCH7

7 TPUCH10 8 TPUCH9





17 TPUCH28 18 TCRCLK


21 TPUCH30 22 GND

23 GND 24 U0CTS

25 U0RXD 26 DTOUT0

27 DTIN0 28 U0TXD

29 U0RTS 30 GND

31 CLKMOD0 32 +3.3V

33 CLKMOD1 34 GND

Table 19. J7 (continued)




35 GND 36 D28

37 D30 38 D29

39 D31 40 D24

41 D26 42 D25

43 D27 44 D21

45 D23 46 D22

47 EXT_RSTIN 48 D19

49 GND 50 GND

51 D13 52 D20

53 D9 54 D17

55 D12 56 D18

57 D15 58 D16

59 GND 60 GND

Table 21. J9


1 +5V 2 +1.5V

3 +3.3V 4 +3.3V

5 +3.3V 6 +3.3V

7 GND 8 GND

9 A21 10 A22

11 A19 12 A20

13 A17 14 A18

15 A16 16 A14

17 A15 18 A11

19 A13 20 GND

21 GND 22 A10

23 A12 24 A8

25 A9 26 A7

27 A6 28 A4

29 A5 30 GND

31 A2 32 A0

33 A3 34 A1





35 GND 36 GND

37 DTIN3 38 UTPUODIS

39 DTOUT3 40 LTPUODIS

41 TIP 42 TEA

43 TS 44 TA

45 CAN0RX 46 SD_WE

47 R/W 48 CAN0TX

49 SD_CAS 50 SD_CS0

51 CLKOUT 52 SD_RAS

53 SD_CS1 54 DDATA3

55 XTAL 56 EXTAL

57 GND 58 GND

59 GND 60 GND

Table 22. J10


1 +5V 2 +1.5V

3 +3.3V 4 +3.3V

5 D14 6 D10

7 D11 8 D6

9 D7 10 D8

11 D5 12 D4

13 GND 14 GND

15 D1 16 D2

17 D3 18 OE

19 D0 20 DTOUT1

21 DTIN1 22 +3.3V

23 +3.3V 24 IRQ6

25 IRQ7 26 TSIZ0

27 TSIZ1 28 IRQ2

29 IRQ3 30 IRQ4

31 IRQ5 32 TCLK/PSTCLK

33 DTOUT2 34 DTIN2





2.5.2 Reset Switch (SW6)

The reset logic provides system initialization. Reset occurs at power-on or by asserting RESET via SW6.

A hard reset and voltage sense controller (U25) is used to produce an active low power-on reset signal. The reset switch (SW6) is fed into U25 that generates the signal tied to the MCF5235’s RESET. RESET is an open collector signal. Therefore, it can be wire-OR’ed with other reset signals from additional peripherals. On the EVB, RESET is wire OR’d with the BDM reset signal and a reset signal is available on the expansion connectors for use with your hardware.

See Section 2.3.1, “Reset Logic”, for more details on reset.

2.5.3 User LEDs

There are eight LEDs available to you. Each of these LEDs are pulled to +3.3V through a 10 Ω resistor and can be illuminated by driving a logic 0 on the appropriate signal to sink the current. Each of these signals can be disconnected from its associated LED with a jumper. The table below details which MCF5235 signal is associated with which LED.

35 IRQ1 36 TDI/DSI

37 TDO/DSO 38 TMS/BKPT

39 TRST/DSCLK 40 GND

41 GND 42 PST3

43 PST1 44 PST2

45 PST0 46 DDATA0

47 DDATA2 48 DDATA1

49 GND 50 GND

51 JTAG_EN 52 RCON

53 GND 54 RSTOUT

55 GND 56 RESET

57 GND 58 GND

59 GND 60 GND

Table 23. User LEDs

LED MCF5235 Signal Jumper to disconnect

D25 DTOUT0 JP38

D26 DTIN0 JP39

D27 DTOUT1 JP40

D28 DTIN1 JP41





2.5.4 Other LEDs

There are several other LEDs on the M523xEVB to signal various board/processor/component states. Below is a list of those LEDs and their functions:

3 Initialization and Setup

3.1 System ConfigurationThe M523xEVB board requires the following items for minimum system configuration:

• The M523xEVB board (provided).• Power supply, +7V to 14V DC with minimum of 300 mA.• RS232C compatible terminal or a PC with terminal emulation software.• RS232 communication cable (provided).

D29 DTOUT2 JP42

D30 DTIN2 JP43

D31 DTOUT3 JP44

D32 DTIN3 JP45

Table 24. LED Functions

LED Function

D1–D4 Ethernet Phy functionality

D5–D12 eTPU functionality

D14 +3.3V Power Good

D17 +5V Power Good

D23 Abort (IRQ7) asserted

D24 Reset (RSTI) asserted

D25–D32 User LEDs (See Table 23)

Table 23. User LEDs (continued)

LED MCF5235 Signal Jumper to disconnect



Figure 5 displays the minimum system configuration.

Figure 5. Minimum System Configuration

3.2 Installation and SetupThe following sections describe all the steps needed to prepare the board for operation. Please read the following sections carefully before using the board. When you are preparing the board for the first time,

dBUG>

+7 to +14 VDCInput Power

RS-232 Terminalor PC



check that all jumpers are in the default locations. Default jumper markings are documented on the master jumper table and printed on the underside of the board. After the board is functional in its default mode, the Ethernet interface may be used by following the instructions provided in Section 5, “Configuring dBUG for Network Downloads”.

3.2.1 Unpacking

Unpack the computer board from its shipping box. Save the box for storing or reshipping. Refer to the following list and verify that all the items are present. You should have received:

• M523xEVB Single Board Computer• M5235EVB User's Manual (this document)• One RS232 communication cable• One BDM (background debug mode) wiggler cable• MCF5235 Reference Manual• ColdFire® Programmers Reference Manual• A selection of third party developer tools and literature

NOTEAvoid touching the MOS devices. Static discharge can damage these devices.

After you have verified that all the items are present, remove the board from its protective jacket and anti-static bag. Check the board for any visible damage. Ensure that there are no broken, damaged, or missing parts. If you have not received all the items listed above or they are damaged, please contact Freescale Semiconductor immediately. For contact details, please see the end of this manual.

3.2.2 Preparing the Board for Use

The board, as shipped, is ready to be connected to a terminal and power supply without any need for modification. Figure 9 shows the position of the jumpers and connectors.

3.2.3 Providing Power to the Board

The EVB requires an external supply voltage of 7–14 V DC, minimum 1 Amp. This is regulated on-board using three switching voltage regulators to provide the necessary EVB voltages of 5V, 3.3V and 1.5V. There are two different power supply input connectors on the EVB: connector P2 is a 2.1mm power jack (Figure 6), P3 is a lever actuated connector (Figure 7).



Figure 6. 2.1mm Power Connector

Figure 7. 2-Lever Power Connector

3.2.4 Power Switch (SW4)

Slide switch SW4 isolates the power supply input from the EVB voltage regulators if required:• Moving the slide switch to the left (towards connector P3) turns the EVB on.• Moving the slide switch to the right (away from connector P3) turns the EVB off.

3.2.5 Power Status LEDs and Fuse

When power is applied to the EVB, green power LEDs adjacent to the voltage regulators show the presence of the supply voltage as follows:

If no LEDs are illuminated when the power is applied to the EVB, it is possible that power switch SW4 is in the OFF position or that the fuse F1 has blown. This can occur if power is applied to the EVB in reverse-bias where a protection diode ensures that the fuse blows rather than causing damage to the EVB. Replace F1 with a 20mm 1A fast-blow fuse.

Table 25. Power LEDs

LED Function

D17 Indicates that the +5V regulator is working correctly

D14 Indicates that the +3.3V regulator is working correctly

V+(7-14V)

GND



3.2.6 Selecting Terminal Baud Rate

The serial channel UART0 of the MCF5235 is used for serial communication and has a built in timer. This timer is used by the dBUG ROM monitor to generate the baud rate used to communicate with a serial terminal. A number of baud rates can be programmed. On power-up or manual reset, the dBUG ROM monitor firmware configures the channel for 19200 baud. When the dBUG ROM monitor is running, a SET command may be issued to select any baud rate supported by the ROM monitor.

3.2.7 The Terminal Character Format

The character format of the communication channel is fixed at power-up or reset. The default character format is eight bits per character, no parity, and one stop bit with no flow control. It is necessary to ensure that the terminal or PC is set to this format.

3.2.8 Connecting the Terminal

The board is now ready to be connected to a PC/terminal. 1. Use the RS-232 serial cable to connect the PC/terminal to the M523xEVB PCB. The cable has a

9-pin female D-sub terminal connector at one end and a 9-pin male D-sub connector at the other end.

2. Connect the 9-pin male connector to connector P4 on the M523xEVB board. 3. Connect the 9-pin female connector to one of the available serial communication channels

normally referred to as COM1 (COM2, etc.) on the PC running terminal emulation software. The connector on the PC/terminal may be male 25-pin or 9-pin. It may be necessary to obtain a 25 pin-to-9 pin adapter to make this connection. If an adapter is required, refer to Figure 8.

3.2.9 Using a Personal Computer as a Terminal

A personal computer may be used as a terminal provided a terminal emulation software package is available. Examples of this software are PROCOMM, KERMIT, QMODEM, Windows 95/98/2000/XP Hyper Terminal or similar packages. The board should then be connected as described in Section 3.2.8, “Connecting the Terminal”.

After the connection to the PC is made, power may be applied to the PC and the terminal emulation software can be run. In terminal mode, it is necessary to select the baud rate and character format for the channel. Most terminal emulation software packages provide a command known as Alt-p (press the p key while pressing the Alt key) to choose the baud rate and character format. The character format should be 8 bits, no parity, one stop bit as described in Section 3.2.7, “The Terminal Character Format”. The baud rate should be set to 19200. Power can now be applied to the board.

Figure 8. Pin Assignment for Female (Terminal) Connector

1

69

5



Pin assignments are as follows:Table 26. Pin Assignment for Female (Terminal) Connector

DB9 Pin Function

1 Data Carrier Detect, Output (shorted to pins 4 and 6)

2 Receive Data, Output from board (receive refers to terminal side)

3 Transmit Data, Input to board (transmit refers to terminal side)

4 Data Terminal Ready, Input (shorted to pin 1 and 6)

5 Signal Ground

6 Data Set Ready, Output (shorted to pins 1 and 4)

7 Request to Send, Input

8 Clear to send, Output

9 Not connected



Figure 9 shows the jumper locations for the board.

Figure 9. Jumper Locations

3.3 System Power-up and Initial OperationWhen all of the cables are connected to the board, power may be applied. The dBUG ROM monitor initializes the board and then displays a power-up message on the terminal, which includes the amount of memory present on the board.Hard ResetDRAM Size: 16M

ColdFire MCF5235 on the M523xEVB Firmware v3b.1a.xx (Built on xxx xx xxxx xx:xx:xx)



Copyright 1995-2004 Freescale Semiconductor, Inc.

Enter 'help' for help.dBUG>

The board is now ready for operation under the control of the debugger as described in Section 4, “Using the Monitor/Debug Firmware”. If you do not get the above response, perform the following checks:

1. Make sure that the power supply is properly configured for polarity, voltage level, and current capability (~1A) and is connected to the board.

2. Check that the terminal and board are set for the same character format and baud.3. Press the RESET button to insure that the board has been initialized properly.

If a proper response does not occur after these steps, your board may have been damaged. Contact Freescale Semiconductor for further instructions. Please see the end of this manual for contact details.

3.4 Using The BDM PortThe MCF5235 microprocessor has a built in debug module referred to as BDM (background debug module). To use BDM, simply connect the 26-pin debug connector on the board, J1, to the P&E BDM wiggler cable provided in the kit. No special setting is needed. Refer to the MCF5235 Reference Manual for additional instructions.

NOTEBDM functionality and use is supported by third party developer software tools. Details may be found on the CD-ROM included in this kit.

4 Using the Monitor/Debug FirmwareThe M523xEVB single board computer has a resident firmware package that provides a self-contained programming and operating environment. The firmware, named dBUG, provides you with a monitor/debug interface, inline assembler and disassembly, program download, register and memory manipulation, and I/O control functions. This section is a how-to-use description of the dBUG package, including the user interface and command structure.

4.1 What is dBUG?dBUG is a traditional ROM monitor/debugger that offers a comfortable and intuitive command line interface to download and execute code. It contains all the primary features needed in a debugger to create a useful debugging environment.

The firmware provides a self-contained programming and operating environment. dBUG interacts with you through pre-defined commands that are entered via the terminal. These commands are defined in Section 4.4, “Commands”.

An additional function called the system call allows your program to use various routines within dBUG. The system call is discussed at the end of this section.



The operational mode of dBUG is demonstrated in Figure 10. After the system initialization, the board waits for a command-line input from the user terminal. When a proper command is entered, the operation continues in one of the two basic modes. If the command causes execution of your program, the dBUG firmware may or may not be re-entered, at the discretion of your program. For the alternate case, the command is executed under control of the dBUG firmware, and after command completion, the system returns to command entry mode.

During command execution, additional user input may be required depending on the command function.

For commands that accept an optional <width> to modify the memory access size, the valid values are:• B 8-bit (byte) access• W 16-bit (word) access• L 32-bit (long) access

When no <width> option is provided, the default width is W, 16-bit.

The ColdFire core register set is maintained by dBUG. These are listed below:• A0-A7• D0-D7• PC• SR

All control registers on ColdFire are not readable by the supervisor-programming model, and thus not accessible via dBUG. Your code may change these registers, but caution must be exercised as changes may render dBUG inoperable.

A reference to SP (stack pointer) actually refers to general purpose address register seven, A7.

4.2 Operational ProcedureSystem power-up and initial operation are described in detail in Section 3, “Initialization and Setup”. This information is repeated here for convenience and to prevent possible damage.

4.2.1 System Power-up• Be sure the power supply is connected properly prior to power-up.• Make sure the terminal is connected to the TERMINAL (P4) connector.• Turn power on to the board.



Figure 10 shows the dBUG operational mode.

Figure 10. Flow Diagram of dBUG Operational Mode

4.2.2 System Initialization

After the EVB is powered-up and initialized, the terminal displays:Hard ResetDRAM Size: 16M

ColdFire MCF5235 on the M523xEVB Firmware v3b.1a.xx (Built on xxx xx xxxx xx:xx:xx)Copyright 1995-2004 Freescale Semiconductor, Inc.

Enter 'help' for help.dBUG>

Other means can be used to re-initialize the M523xEVB firmware, as discussed in the following paragraphs.

4.2.2.1 External RESET Button

External RESET (SW6) is the red button. Depressing this button causes all processes to terminate, resets the MCF5235 processor and board logic, and restarts the dBUG firmware. Pressing the RESET button would be the appropriate action if all else fails.

Command lineinput from terminal

Does

cause user programexecution?

No

Yes

Yes

Execute commandfunction

Initialize

No

Jump to userprogram and

begin execution

command line



4.2.2.2 ABORT Button

ABORT (SW5) is the button located next to the RESET button. The abort function causes an interrupt of the present processing (a level 7 interrupt on MCF5235) and gives control to the dBUG firmware. This action differs from RESET in that no processor register or memory contents are changed, the processor and peripherals are not reset, and dBUG is not restarted. Also, in response to depressing the ABORT button, the contents of the MCF5235 core internal registers are displayed.

The abort function is most appropriate when software is being debugged. You can interrupt the processor without destroying the present state of the system. This is accomplished by forcing a non-maskable interrupt that calls a dBUG routine that saves the current state of the registers to shadow registers in the monitor for display. You are returned to the ROM monitor prompt after exception handling.

4.2.2.3 Software Reset Command

dBUG does have a command that causes the dBUG to restart as if a hardware reset was invoked. The command is RESET.

4.3 Command Line UsageThe user interface to dBUG is the command line. A number of features have been implemented to achieve an easy and intuitive command line interface.

dBUG assumes that an 80x24 ASCII character dumb-terminal is used to connect to the debugger. For serial communications, dBUG requires eight data bits, no parity, and one stop bit (8-N-1). The baud rate default is 19200 bps — a speed commonly available from workstations, personal computers and dedicated terminals.

The command line prompt is: dBUG>

Any dBUG command may be entered from this prompt. dBUG does not allow command lines to exceed 80 characters. Wherever possible, dBUG displays data in 80 columns or less. dBUG echoes each character as it is typed, eliminating the need for any local echo on the terminal side.

The <Backspace> and <Delete> keys are recognized as rub-out keys for correcting typographical mistakes.

Command lines may be recalled using the <Control> U, <Control> D and <Control> R key sequences. <Control> U and <Control> D cycle up and down through previous command lines. <Control> R recalls and executes the last command line.

In general, dBUG is not case-sensitive. Commands may be entered in uppercase or lowercase, depending upon your equipment and preference. Only symbol names require that the exact case be used.

Most commands can be recognized by using an abbreviated name. For instance, entering h is the same as entering help. Thus it is not necessary to type the entire command name.

The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging. dBUG recognizes this and allows for repeated execution of these commands with minimal typing. After a command is



entered, press the <Return> or <Enter> key to invoke the command again. The command is executed as if no command line parameters were provided.

4.4 CommandsThis section lists the commands that are available with all versions of dBUG. Some board or CPU combinations may use additional commands not listed below.

Table 27. dBUG Command Summary

Mnemonic Syntax Description

ASM asm <<addr> stmt> Assemble

BC bc addr1 addr2 length Block Compare

BF bf <width> begin end data <inc> Block Fill

BM bm begin end dest Block Move

BR br addr <-r> <-c count> <-t trigger> Breakpoint

BS bs <width> begin end data Block Search

DC dc value Data Convert

DI di<addr> Disassemble

DL dl <offset> Download Serial

DLDBUG dldbug Download dBUG

DN dn <-c> <-e> <-i> <-s <-o offset>> <filename> Download Network

FL fl erase addr bytesfl write dest src bytes

Flash Utilities

GO go <addr> Execute

GT gt addr Execute To

HELP help <command> Help

IRD ird <module.register> Internal Register Display

IRM irm module.register data Internal Register Modify

LR lr<width> addr Loop Read

LW lw<width> addr data Loop Write

MD md<width> <begin> <end> Memory Display

MM mm<width> addr <data> Memory Modify

MMAP mmap Memory Map Display

RD rd <reg> Register Display

RM rm reg data Register Modify

RESET reset Reset

SD sd Stack Dump



SET set <option value> Set Configurations

SHOW show <option> Show Configurations

STEP step Step (Over)

SYMBOL symbol <symb> <-a symb value> <-r symb> -C|l|s> Symbol Management

TRACE trace <num> Trace (Into)

UP up begin end filename Upload Memory to File

VERSION version Show Version

Table 27. dBUG Command Summary (continued)

Mnemonic Syntax Description

ASM asm <<addr> stmt> Assemble

BC bc addr1 addr2 length Block Compare

BF bf <width> begin end data <inc> Block Fill



ASM AssemblerUsage: ASM <<addr> stmt>

The ASM command is a primitive assembler. The <stmt> is assembled and the resulting code placed at <addr>. This command has an interactive and non-interactive mode of operation.

The value for address <addr> may be an absolute address specified as a hexadecimal value, or a symbol name. The value for stmt must be valid assembler mnemonics for the CPU.

For interactive mode, enter the command and the optional <addr>. If the address is not specified, then the last address is used. The memory contents at the address are disassembled, and you are prompted for the new assembly. If valid, the new assembly is placed into memory, and the address incremented accordingly. If the assembly is not valid, then memory is not modified, and an error message produced. In either case, memory is disassembled and the process repeats.

You may press the <Enter> or <Return> key to accept the current memory contents and skip to the next instruction, or enter a period to quit the interactive mode.

In the non-interactive mode, specify the address and the assembly statement on the command line. The statement is then assembled, and if valid, placed into memory. Otherwise, an error message is produced.

Examples:

To place a NOP instruction at address 0x0001_0000, the command is:asm 10000 nop

To interactively assemble memory at address 0x0040_0000, the command is:asm 400000



BC Block CompareUsage: BC addr1 addr2 length

The BC command compares two contiguous blocks of memory on a byte-by-byte basis. The first block starts at address addr1 and the second starts at address addr2, both of length bytes.

If the blocks are not identical, the address of the first mismatch is displayed. The value for addresses addr1 and addr2 may be an absolute address specified as a hexadecimal value or a symbol name. The value for length may be a symbol name or a number converted according to the user-defined radix (hexadecimal by default).

Example:

To verify that the data starting at 0x2_0000 and ending at 0x3_0000 is identical to the data starting at 0x8_0000, the command is:

bc 20000 80000 10000



BF Block FillUsage: BF<width> begin end data <inc>

The BF command fills a contiguous block of memory starting at address begin, stopping at address end, with the value data. <Width> modifies the size of the data that is written. If no <width> is specified, the default of word-sized data is used.

The value for addresses begin and end may be an absolute address specified as a hexadecimal value, or a symbol name. The value for data may be a symbol name, or a number converted according to the user-defined radix, normally hexadecimal.

The optional value <inc> can be used to increment (or decrement) the data value during the fill.

This command first aligns the starting address for the data access size, and then increments the address accordingly during the operation. Thus, for the duration of the operation, this command performs properly-aligned memory accesses.

Examples:

To fill a memory block starting at 0x0002_0000 and ending at 0x0004_0000 with the value 0x1234, the command is:

bf 20000 40000 1234

To fill a block of memory starting at 0x0002_0000 and ending at 0x0004_0000 with a byte value of 0xAB, the command is:

bf.b 20000 40000 AB

To zero out the BSS section of the target code (defined by the symbols bss_start and bss_end), the command is:

bf bss_start bss_end 0

To fill a block of memory starting at 0x0002_0000 and ending at 0x0004_0000 with data that increments by 2 for each <width>, the command is:

bf 20000 40000 0 2



BM Block MoveUsage: BM begin end dest

The BM command moves a contiguous block of memory starting at address begin and stopping at address end to the new address dest. The command copies memory as a series of bytes, and does not alter the original block.

The values for addresses begin, end, and dest may be absolute addresses specified as hexadecimal values, or symbol names. If the destination address overlaps the block defined by begin and end, an error message is produced and the command exits.

Examples:

To copy a block of memory starting at 0x0004_0000 and ending at 0x0008_0000 to the location 0x0020_0000, the command is:

bm 40000 80000 200000

To copy the target code’s data section (defined by the symbols data_start and data_end) to 0x0020_0000, the command is:

bm data_start data_end 200000

NOTERefer to the upuser command for copying code/data into flash memory.



BR BreakpointsUsage: BR addr <-r> <-c count> <-t trigger>

The BR command inserts or removes breakpoints at address addr. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name. Count and trigger are numbers converted according to the user-defined radix, normally hexadecimal.

If no argument is provided to the BR command, a listing of all defined breakpoints is displayed.

The -r option to the BR command removes a breakpoint defined at address addr. If no address is specified in conjunction with the -r option, then all breakpoints are removed.

Each time a breakpoint is encountered during the execution of target code, its count value is incremented by one. By default, the initial count value for a breakpoint is zero, but the -c option allows setting the initial count for the breakpoint.

Each time a breakpoint is encountered during the execution of target code, the count value is compared against the trigger value. If the count value is equal to or greater than the trigger value, a breakpoint is encountered and control returned to dBUG. By default, the initial trigger value for a breakpoint is one, but the -t option allows setting the initial trigger for the breakpoint.

If no address is specified in conjunction with the -c or -t options, then all breakpoints are initialized to the values specified by the -c or -t option.

Examples:

To set a breakpoint at the C function main() (symbol _main; see symbol command), the command is:br _main

When the target code is executed and the processor reaches main(), control is returned to dBUG.

To set a breakpoint at the C function bench() and set its trigger value to 3, the command is:br _bench -t 3

When the target code is executed, the processor must attempt to execute the function bench() a third time before returning control back to dBUG.

To remove all breakpoints, the command is:br -r



BS Block SearchUsage: BS<width> begin end data

The BS command searches a contiguous block of memory starting at address begin, stopping at address end, for the value data. <Width> modifies the size of the data that is compared during the search. If no <width> is specified, the default of word sized data is used.

The values for addresses begin and end may be absolute addresses specified as hexadecimal values, or symbol names. The value for data may be a symbol name or a number converted according to the user-defined radix, normally hexadecimal.


Examples:

To search for the 16-bit value 0x1234 in the memory block starting at 0x0004_0000 and ending at 0x0008_0000:

bs 40000 80000 1234

This reads the 16-bit word located at 0x0004_0000 and compares it against the 16-bit value 0x1234. If no match is found, then the address is incremented to 0x0004_0002 and the next 16-bit value is read and compared.

To search for the 32-bit value 0xABCD in the memory block starting at 0x0004_0000 and ending at 0x0008_0000:

bs.l 40000 80000 ABCD

This reads the 32-bit word located at 0x0004_0000 and compares it against the 32-bit value 0x0000_ABCD. If no match is found, then the address is incremented to 0x0004_0004 and the next 32-bit value is read and compared.



DC Data ConversionUsage: DC data

The DC command displays the hexadecimal or decimal value data in hexadecimal, binary, and decimal notation.

The value for data may be a symbol name or an absolute value. If an absolute value passed into the DC command is prefixed by 0x, data is interpreted as a hexadecimal value. Otherwise data is interpreted as a decimal value.

All values are treated as 32-bit quantities.

Examples:

To display the decimal and binary equivalent of 0x1234, the command is:dc 0x1234

To display the hexadecimal and binary equivalent of 1234, the command is:dc 1234



DI DisassembleUsage: DI <addr>

The DI command disassembles target code pointed to by addr. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name.

Wherever possible, the disassembler uses information from the symbol table to produce a more meaningful disassembly. This is especially useful for branch target addresses and subroutine calls.

The DI command attempts to track the address of the last disassembled opcode. If no address is provided to the DI command, then the DI command uses the address of the last opcode that was disassembled.

The DI command is repeatable.

Examples:

To disassemble code that starts at 0x0004_0000, the command is:di 40000

To disassemble code of the C function main(), the command is:di _main



DL Download ConsoleUsage: DL <offset>

The DL command performs an S-record download of data obtained from the console, typically a serial port. The value for offset is converted according to the user-defined radix, normally hexadecimal. Please reference the ColdFire Microprocessor Family Programmer’s Reference Manual for details on the S-Record format.

If offset is provided, then the destination address of each S-record is adjusted by offset.

The DL command checks the destination download address for validity. If the destination is an address outside the defined user space, then an error message is displayed and downloading aborted.

If the S-record file contains the entry point address, then the program counter is set to reflect this address.

Examples:

To download an S-record file through the serial port, the command is:dl

To download an S-record file through the serial port, and add an offset to the destination address of 0x40, the command is:

dl 0x40



DLDBUG Download dBUGUsage: DL <offset>

The DLDBUG command is used to update the dBUG image in flash. It erases the flash sectors containing the dBUG image, downloads a new dBUG image in S-record format obtained from the console, and programs the new dBUG image into flash.

When the DLDBUG command is issued, dBUG prompts you for verification before any actions are taken. If the command is affirmed, the flash is erased and you are prompted to begin sending the new dBUG S-record file. The file should be sent as a text file with no special transfer protocol.

CAUTIONUse this command with extreme caution, as any error can render dBUG useless!



DN Download NetworkUsage: DN <-c> <-e> <-i> <-s> <-o offset> <filename>

The DN command downloads code from the network. The DN command manages files that are S-record, COFF, ELF or image formats. The DN command uses trivial file transfer protocol (TFTP) to transfer files from a network host.

In general, the type of file to be downloaded and the name of the file must be specified to the DN command.

• -c option indicates a COFF download• -e option indicates an ELF download• -i option indicates an image download• -s indicates an S-record download• -o option works only in conjunction with the -s option to indicate an optional offset for S-record

download.

The filename is passed directly to the TFTP server and therefore must be a valid filename on the server.

If neither of the -c, -e, -i, -s or filename options are specified, then a default filename and filetype is used. Default filename and filetype parameters are manipulated using the SET and SHOW commands.

The DN command checks the destination download address for validity. If the destination is an address outside the defined user space, then an error message is displayed and downloading aborted.

For ELF and COFF files that contain symbolic debug information, the symbol tables are extracted from the file during download and used by dBUG. Only global symbols are kept in dBUG. The dBUG symbol table is not cleared prior to downloading. So, it is your responsibility to clear the symbol table as necessary prior to downloading.

If an entry point address is specified in the S-record, COFF or ELF file, the program counter is set accordingly.

Examples:

To download an S-record file with the name srec.out, the command is:dn -s srec.out

To download a COFF file with the name coff.out, the command is:dn -c coff.out

To download a file using the default filetype with the name bench.out, the command is:dn bench.out

To download a file using the default filename and filetype, the command is:dn



FL Flash UtilitiesInfo Usage: FLErase Usage: FL erase addr bytesWrite Usage: FL write dest src bytes

The FL command provides a set of flash utilities that displays information about the flash devices on the EVB, erases a specified range of flash, or erases and programs a specified range of flash.

When issued with no parameters, the FL command displays usage information, as well as device specific information for the flash devices available. This information includes size, address range, protected range, access size, and sector boundaries.

When the erase command is given, the FL command attempts to erase the number of bytes specified on the command line beginning at addr. If this range doesn’t start and end on flash sector boundaries, the range is adjusted automatically and you are prompted for verification before proceeding.

When the write command is given, the FL command programs the number of bytes specified from src to dest. An erase of this region is first attempted. As with the erase command, if the flash range to be programmed does not start and end on flash sector boundaries, the range is adjusted and you are prompted for verification before the erase is performed. The specified range is also checked to insure that the entire destination range is valid within the same flash device and that the src and dest are not within the same device.



GO ExecuteUsage: GO <addr>

The GO command executes target code starting at address addr. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name.

If no argument is provided, the GO command begins executing instructions at the current program counter.

When the GO command is executed, all user-defined breakpoints are inserted into the target code, and the context is switched to the target program. Control is only regained when the target code encounters a breakpoint, illegal instruction, trap #15 exception, or other exception that causes control to be handed back to dBUG.

The GO command is repeatable.

Examples:

To execute code at the current program counter, the command is:go

To execute code at the C function main(), the command is:go _main

To execute code at the address 0x0004_0000, the command is:go 40000



GT Execute ToUsage: GT addr

The GT command inserts a temporary breakpoint at addr and then executes target code starting at the current program counter. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name.

When the GT command is executed, all breakpoints are inserted into the target code, and the context is switched to the target program. Control is only regained when the target code encounters a breakpoint, illegal instruction, or other exception that causes control to be handed back to dBUG.

Examples:

To execute code up to the C function bench(), the command is:gt _bench



HELP HelpUsage: HELP <command>

The HELP command displays a brief syntax of the commands available within dBUG. In addition, the address of where your code may start is given. If command is provided, then a brief listing of the syntax of the specified command is displayed.

Examples:

To obtain a listing of all the commands available within dBUG, the command is:help

To obtain help on the breakpoint command, the command is:help br



IRD Internal Register DisplayUsage: IRD <module.register>

This command displays the internal registers of different modules inside the MCF5235. In the command line, module refers to the module name where the register is located and register refers to the specific register to display.

The registers are organized according to the module to which they belong. Use the IRD command without any parameters to get a list of all the valid modules. Refer to the MCF5235 Reference Manual for more information on these modules and the registers they contain.

Example:ird sim.rsr



IRM Internal Register ModifyUsage: IRM module.register data

This command modifies the contents of the internal registers of different modules inside the MCF5235. In the command line, module refers to the module name where the register is located and register refers to the specific register to modify. The data parameter specifies the new value to be written into the register.

Example:

To modify the TMR register of the first timer module to the value 0x0021, the command is:irm timer1.tmr 0021



LR Loop ReadUsage: LR<width> addr

The LR command continually reads the data at addr until a key is pressed. The optional <width> specifies the size of the data to be read. If no <width> is specified, the command defaults to reading word-sized data.

Example:

To continually read the longword data from address 0x2_0000, the command is:lr.l 20000



LW Loop WriteUsage: LW<width> addr data

The LW command continually writes data to addr. The optional width specifies the size of the access to memory. The default access size is word.

Examples:

To continually write the longword data 0x1234_5678 to address 0x2_0000, the command is:lw.l 20000 12345678

The following command writes 0x78 into memory:lw.b 20000 12345678



MD Memory DisplayUsage: MD<width> <begin> <end>

The MD command displays a contiguous block of memory starting at address begin and stopping at address end. The values for addresses begin and end may be absolute addresses specified as hexadecimal values, or symbol names. Width modifies the size of the data that is displayed. If no <width> is specified, the default of word-sized data is used.

Memory display starts at the address begin. If no beginning address is provided, the MD command uses the last address that was displayed. If no ending address is provided, then MD displays memory up to an address that is 128 beyond the starting address.


Examples:

To display memory at address 0x0040_0000, the command is:md 400000

To display memory in the data section (defined by the symbols data_start and data_end), the command is:md data_start

To display a range of bytes from 0x0004_0000 to 0x0005_0000, the command is:md.b 40000 50000

To display a range of 32-bit values starting at 0x0004_0000 and ending at 0x0005_0000:md.l 40000 50000



MM Memory ModifyUsage: MM<width> addr <data>

The MM command modifies memory at the address addr. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name. Width specifies the size of the data that is modified. If no <width> is specified, the default of word sized data is used. The value for data may be a symbol name, or a number converted according to the user-defined radix, normally hexadecimal.

If a value for data is provided, then the MM command immediately sets the contents of addr to data. If no value for data is provided, then the MM command enters into a loop. The loop obtains a value for data, sets the contents of the current address to data, increments the address according to the data size, and repeats. The loop terminates when an invalid entry for the data value is entered, i.e., a period.


Examples:

To set the byte at location 0x0001_0000 to be 0xFF, the command is:mm.b 10000 FF

To interactively modify memory beginning at 0x0001_0000, the command is:mm 10000



MMAP Memory Map DisplayUsage: mmap

This command displays the memory map information for the M523xEVB evaluation board. The information displayed includes the type of memory, the start and end address of the memory, and the port size of the memory. The display also includes information on how the chip selects are used on the board and which regions of memory are reserved (protected) for dBUG use.

Here is an example of the output from this command:Type Start End Port Size

-----------------------------------------------------------------SDRAM 0x00000000 0x00FFFFFF 32-bitSRAM (Int) 0x20000000 0x2000FFFF 32-bitMRAM (Ext) 0x30000000 0x3007FFFF 32-bitIPSBAR 0x40000000 0x7FFFFFFF 32-bitFlash (Ext) 0xFFE00000 0xFFFFFFFF 16-bit

Protected Start End----------------------------------------dBUG Code 0xFFE00000 0xFFE3FFFFdBUG Data 0x00000000 0x0000FFFF

Chip Selects----------------CS0 Ext FlashCS1 Ext MRAM



RD Register DisplayUsage: RD <reg>

The RD command displays the register set of the target. If no argument for reg is provided, then all registers are displayed. Otherwise, the value for reg is displayed.

dBUG preserves the registers by storing a copy of the register set in a buffer. The RD command displays register values from the register buffer.

Examples:

To display all the registers and their values, the command is:rd

To display only the program counter:rd pc

Here is an example of the output from this command:PC: 00000000 SR: 2000 [t.Sm.000...xnzvc]An: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000Dn: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000



RM Register ModifyUsage: RM reg data

The RM command modifies the contents of the register reg to data. The value for reg is the name of the register, and the value for data may be a symbol name, or it is converted according to the user-defined radix, normally hexadecimal.

dBUG preserves the registers by storing a copy of the register set in a buffer. The RM command updates the copy of the register in the buffer. The actual value is not written to the register until target code is executed.

Examples:

To change register D0 to contain the value 0x1234, the command is:rm D0 1234



RESET Reset the Board and dBUGUsage: RESET

The RESET command resets the board and dBUG to their initial power-on states.

The RESET command executes the same sequence of code that occurs at power-on. If the RESET command fails to reset the board adequately, cycle the power or press the reset button.

Examples:

To reset the board and clear the dBUG data structures, the command is:reset



SD Stack DumpUsage: SD

The SD command displays a back trace of stack frames. This command is useful after some user code has executed that creates stack frames (i.e,. nested function calls). After control is returned to dBUG, the SD command decodes the stack frames and display a trace of the function calls.



SET Set ConfigurationsUsage: SET <option value>

The SET command allows the setting of user-configurable options within dBUG. With no arguments, SET displays the options and values available. The SHOW command displays the settings in the appropriate format. The standard set of options is listed below.

• baud—This is the baud rate for the first serial port on the board. All communications between you and dBUG occur using 9600 or 19200 bps, eight data bits, no parity, and one stop bit (8-N-1) with no flow control.

• base—This is the default radix for use in converting a number from its ASCII text representation to the internal quantity used by dBUG. The default is hexadecimal (base 16), and other choices are binary (base 2), octal (base 8), and decimal (base 10).

• client—This is the network Internet Protocol (IP) address of the board. For network communications, the client IP is required to be set to a unique value, usually assigned by your local network administrator.

• server—This is the network IP address of the machine that contains files accessible via TFTP. Your local network administrator has this information and can assist in properly configuring a TFTP server if one does not exist.

• gateway—This is the network IP address of the gateway for your local subnetwork. If the client IP address and server IP address are not on the same subnetwork, then this option must be properly set. Your local network administrator has this information.

• netmask—This is the network address mask to determine if use of a gateway is required. This field must be properly set. Your local network administrator has this information.

• filename—This is the default filename to be used for network download if no name is provided to the DN command.

• filetype—This is the default filetype to be used for network download if no type is provided to the DN command. Valid values are: srecord, coff, and elf.

• mac—This is the ethernet Media Access Control (MAC) address (hardware address) for the evaluation board. This should be set to a unique value, and the most significant nibble should always be even.

Examples: To set the baud rate of the board to be 19200, the command is:set baud 19200

NOTESee the SHOW command for a display containing the correct formatting of these options.



SHOW Show ConfigurationsUsage: SHOW <option>

The SHOW command displays the settings of the user-configurable options within dBUG. When no option is provided, SHOW displays all options and values.

Examples:

To display all options and settings, the command is:show

To display the current baud rate of the board, the command is:show baud

Here is an example of the output from a show command:dBUG> show

base: 16baud: 19200server: 0.0.0.0client: 0.0.0.0gateway: 0.0.0.0netmask: 255.255.255.0filename: test.s19filetype: S-Recordethaddr: 00:CF:52:82:CF:01



STEP Step OverUsage: STEP

The STEP command steps over a subroutine call, rather than tracing every instruction in the subroutine. The command sets a temporary breakpoint one instruction beyond the current program counter and then executes the target code.

The STEP command steps over BSR and JSR instructions. The command works for other instructions as well, but if STEP is used with an instruction that does not return (i.e. BRA) then the temporary breakpoint may never be encountered and dBUG may never regain control.

Examples:

To pass over a subroutine call, the command is:step



SYMBOL Symbol Name ManagementUsage: SYMBOL <symb> <-a symb value> <-r symb> <-c|l|s>

The SYMBOL command adds or removes symbol names from the symbol table. If only a symbol name is provided to the SYMBOL command, then the symbol table is searched for a match on the symbol name and its information displayed.

• -a option adds a symbol name and its value into the symbol table• -r option removes a symbol name from the table• -c option clears the entire symbol table• -l option lists the contents of the symbol table• -s option displays usage information for the symbol table

Symbol names contained in the symbol table are truncated to 31 characters. Any symbol table lookups, by the SYMBOL command or by the disassembler, only use the first 31 characters. Symbol names are case-sensitive.

Symbols can also be added to the symbol table via inline assembly labels and ethernet downloads of ELF formatted files.

Examples:

To define the symbol main to have the value 0x0004_0000, the command is:symbol -a main 40000

To remove the symbol junk from the table, the command is:symbol -r junk

To see how full the symbol table is, the command is:symbol -s

To display the symbol table, the command is:symbol -l



TRACE Trace IntoUsage: TRACE <num>

The TRACE command allows single-instruction execution. If num is provided, then num instructions are executed before control is handed back to dBUG. The value for num is a decimal number.

The TRACE command sets bits in the processors’ supervisor registers to achieve single-instruction execution, and the target code executed. Control returns to dBUG after a single-instruction execution of the target code.

This command is repeatable.

Examples:

To trace one instruction at the program counter, the command is:tr

To trace 20 instructions from the program counter, the command is:tr 20



UP Upload DataUsage: UP begin end filename

The UP command uploads the data from a memory region (specified by begin and end) to a file (specified by filename) over the network. The file created contains the raw binary data from the specified memory region. The UP command uses the trivial file transfer protocol (TFTP) to transfer files to a network host.

Example:

To upload a portion of SDRAM to a file sdram.bin, the command is:up 40000 50000 sdram.bin



VERSION Display dBUG VersionUsage: VERSION

The VERSION command displays the version information for dBUG. The dBUG version, build number and build date are all given.

The version number is separated by a decimal, for example, v 2b.1c.1a:

The version date is the day and time the entire dBUG monitor was compiled and built.

Examples:

To display the version of the dBUG monitor, the command is:version

4.5 TRAP #15 FunctionsAn additional utility within the dBUG firmware is a function called the TRAP 15 handler. This function can be called by your program to use various routines within the dBUG, to perform a special task, and to return control to the dBUG. This section describes the TRAP 15 handler and how it is used.

There are four TRAP #15 functions. These are: OUT_CHAR, IN_CHAR, CHAR_PRESENT, and EXIT_TO_dBUG.

4.5.1 OUT_CHAR

This function (function code 0x0013) sends a character, which is in the lower eight bits of D1, to the terminal.

Assembly example:/* assume d1 contains the character */move.l #$0013,d0 Selects the functionTRAP #15 The character in d1 is sent to terminal

C example:void board_out_char (int ch){

/* If your C compiler produces a LINK/UNLK pair for this routine, * then use the following code that takes this into account*/

#if l/* LINK a6,#0 -- produced by C compiler */asm (“ move.l8(a6),d1”); /* put ‘ch’into d1 */

In this example, v 2b . 1c . 1a{ { {

dBUG commonmajor and minor revision

CPU major and minor revision

board majorand minor revision



asm (“ move.l#0x0013,d0”); /* select the function */asm (“ trap#15”); /* make the call *//* UNLK a6 -- produced by C compiler */

#else/* If C compiler does not produce a LINK/UNLK pair, the use * the following code.*/ asm (“ move.l4(sp),d1”); /* put ‘ch’into d1 */asm (“ move.l#0x0013,d0”); /* select the function */asm (“ trap#15”); /* make the call */

#endif}

4.5.2 IN_CHAR

This function (function code 0x0010) returns an input character (from terminal) to the caller. The returned character is in D1.

Assembly example:move.l #$0010,d0 Select the functiontrap #15 Make the call, the input character is in d1.

C example:int board_in_char (void){

asm (“ move.l#0x0010,d0”); /* select the function */asm (“ trap#15”); /* make the call */asm (“ move.ld1,d0”); /* put the character in d0 */

}

4.5.3 CHAR_PRESENT

This function (function code 0x0014) checks if an input character is present to receive. A value of zero is returned in D0 when no character is present. A non-zero value in D0 means a character is present.

Assembly example:move.l #$0014,d0 Select the functiontrap #15 Make the call, d0 contains the response (yes/no).

C example:int board_char_present (void){

asm (“ move.l#0x0014,d0”); /* select the function */asm (“ trap#15”); /* make the call */

}

4.5.4 EXIT_TO_dBUG

This function (function code 0x0000) transfers the control back to the dBUG, by terminating your code. The register context are preserved.



Assembly example:move.l #$0000,d0 Select the functiontrap #15 Make the call, exit to dBUG.

C example:void board_exit_to_dbug (void){

asm (“ move.l#0x0000,d0”); /* select the function */asm (“ trap#15”); /* exit and transfer to dBUG */

}

5 Configuring dBUG for Network DownloadsThe dBUG module has the ability to perform downloads over an Ethernet network using the trivial file transfer protocol, TFTP.

NOTEThis requires a TFTP server to be running on the host attached to the board.

Prior to using this feature, several parameters are required for network downloads to occur. The information that is required and the steps for configuring dBUG are described below.

5.1 Required Network ParametersFor performing network downloads, dBUG needs six parameters; four are network-related, and two are download-related. The parameters are listed below, with the dBUG designation following in parenthesis.

All computers connected to an Ethernet network running the IP protocol need three network-specific parameters. These parameters are:

• Internet Protocol (IP( address for the computer (client IP)• IP address of the gateway for non-local traffic (gateway IP)• Network netmask for flagging traffic as local or non-local (netmask)

In addition, the dBUG network download command requires the following three parameters:• IP address of the TFTP server (server IP),• Name of the file to download (filename),• Type of the file to download (filetype of S-record, COFF, ELF, or Image).

Your local system administrator can assign a unique IP address for the board, and also provide you the IP addresses of the gateway, netmask, and TFTP server. Fill out the lines below with this information.

Client IP: ___.___.___.___ (IP address of the board)Server IP: ___.___.___.___ (IP address of the TFTP server)Gateway: ___.___.___.___ (IP address of the gateway)Netmask: ___.___.___.___ (Network netmask)



5.2 Configuring dBUG Network ParametersAfter the network parameters have been obtained, the dBUG ROM monitor must be configured. The following commands are used to configure the network parameters.

set client <client IP>set server <server IP>set gateway <gateway IP>set netmask <netmask>set mac <addr>

For example, the TFTP server is named santafe and has IP address 123.45.67.1. The board is assigned the IP address of 123.45.68.15. The gateway IP address is 123.45.68.250, and the netmask is 255.255.255.0. The MAC address is chosen arbitrarily and is unique. The commands to dBUG are:

set client 123.45.68.15set server 123.45.67.1set gateway 123.45.68.250set netmask 255.255.255.0set mac 00:CF:52:82:EB:01

The last step is to inform dBUG of the name and type of the file to download. Prior to giving the name of the file, keep in mind the following.

Most, if not all, TFTP servers only allow access to files starting at a particular sub-directory. (This is a security feature that prevents reading of arbitrary files by unknown persons.) For example, SunOS uses the directory /tftp_boot as the default TFTP directory. When specifying a filename to a SunOS TFTP server, all filenames are relative to /tftp_boot. As a result, you normally are required to copy the file to download into the directory used by the TFTP server.

A default filename for network downloads is maintained by dBUG. To change the default filename, use the command:

set filename <filename>

When using the Ethernet network for download, S-record, COFF, ELF, or image files may be downloaded. A default filetype for network downloads is maintained by dBUG as well. To change the default filetype, use the command:

set filetype <srecord|coff|elf|image>

Continuing with the above example, the compiler produces an executable COFF file, a.out. This file is copied to the /tftp_boot directory on the server with the command:

rcp a.out santafe:/tftp_boot/a.out

Change the default filename and filetype with the commands:set filename a.outset filetype coff

Finally, perform the network download with the DN command. The network download process uses the configured IP addresses and the default filename and filetype for initiating a TFTP download from the TFTP server.



5.3 Troubleshooting Network ProblemsMost problems related to network downloads are a direct result of improper configuration. Verify that all IP addresses configured into dBUG are correct. This is accomplished via the SHOW command.

• Using an IP address already assigned to another machine causes dBUG network download to fail, and probably other severe network problems. Make certain the client IP address is unique for the board.

• Check for proper insertion or connection of the network cable. Is the status LED lit indicating that network traffic is present?

• Check for proper configuration and operation of the TFTP server. Most Unix workstations can execute a command named tftp that can be used to connect to the TFTP server as well. Is the default TFTP root directory present and readable?

• If ICMP_DESTINATION_UNREACHABLE or similar ICMP message appears, then a serious error has occurred. Reset the board, and wait one minute for the TFTP server to time out and terminate any open connections. Verify that the IP addresses for the server and gateway are correct. Also, verify that a TFTP server is running on the server.



6 Schematics

5 5

4 4

3 3

2 2

1 1

D C B A

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Gen

eral

Not

es a

nd In

form

atio

nC

M52

3xE

VB

B

116

Mon

day,

Aug

ust 1

3, 2

007

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Gen

eral

Not

es a

nd In

form

atio

nC

M52

3xE

VB

B

116

Mon

day,

Aug

ust 1

3, 2

007

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Gen

eral

Not

es a

nd In

form

atio

nC

M52

3xE

VB

B

116

Mon

day,

Aug

ust 1

3, 2

007

SHEE

T 12

SHEE

T 11

SHEE

T 9

HIERARCHICAL INTERCONNECTS

MRAM MEMORY

ETHERNET INTERFACE

POWER SUPPLY UNIT

EXPANSION CONNECTORS

SHEE

T 8

M523X CPU

- All connectors are denoted Jx

Tabl

e O

f Con

tent

s:

SERIAL I/O INTERFACE

SHEE

T 6

- All decoupling caps less than 0.1uF are COG SMD 0805 unless otherwise stated

Dat

e

SHEE

T 13

FLASH MEMORY

Rev

SHEE

T 14

ETPU INTERFACE

Revi

sion

Info

rmat

ion

SHEE

T 7

SHEE

T 5

SHEE

T 15

Des

igne

rSH

EET

2

CAN INTERFACE

Notes:

- All test points are denoted TPx

0.0

SHEE

T 4

02 F

eb 0

4

RESET CONFIGURATION AND CLOCKING CIRCUITRY

SHEE

T 10

ADDRESS AND DATA BUS BUFFERS

- All decoupling caps greater than 0.1uF are X7R SMD 0805 unless otherwise stated

L. A

nder

son

Prov

ision

al re

leas

e

M52

3X E

valu

atio

n B

oard

- All Switches are denoted SWx

- All jumpers are denoted JPx

Com

men

tsSH

EET

3

DEBUG

SDRAM MEMORY

SHEE

T 16

USB INTERFACE

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

A05

Mar

04

P. H

ight

onA

dded

Met

row

erks

sche

mat

ic p

art n

umbe

r and

revi

sion

lette

r.B

30 A

pr 0

4L.

And

erso

nRe

mov

ed al

tern

ativ

e foo

tprin

t for

90-

pin

SSO

P 32

-bit

Flas

h an

dre

plac

ed w

ith 1

6-bi

t Fla

sh, c

orre

cted

RJ4

5 pi

nout

and

adde

d18

Koh

m p

ull-d

own

resis

tors

to U

11 (e

ther

net t

rans

ceiv

er).

C23

Jun

04L.

And

erso

n &

Pete

Hig

hton

Fina

l upd

ate i

nclu

ding

silk

scre

en m

odifi

catio

ns o

f the

rese

tco

nfig

urat

ion

tabl

es. C

orre

ctio

n of

sign

als o

n th

e RJ-

45 co

nnec

tor

and

addi

tion

of p

ull-d

own

resis

tors

on

the e

ther

net s

igna

ls.

D A27

Jul 0

5L.

And

erso

nU

pdat

ed U

SB p

age.

Jum

pers

59

to 6

2 re

num

bere

d.11

Nov

05

C. C

have

zU

pdat

ed R

evisi

on S

chem

atic

s Pag

e to

refle

ct R

oHS

conv

ersio

n of

EVB.

B03

Mar

07

C. C

have

zA

dded

term

inat

ion

resis

tors

R28

,R29

,R72

with

22

Ohm

resis

tors

inor

der t

o pa

ss F

CC.

Repl

aced

ASR

AM

with

MRA

M U

1 an

d U

2.C

06 A

ug 0

7C.

Cha

vez

Repl

aced

1M

Ohm

with

1K

Ohm

resis

tors

on

R1, R

3, R

67, R

68,

R69.



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ER

XD

2

ETX

D0

ER

XD

3

ETX

D1

EC

OL

ER

XD

V

ETX

D3

ER

XC

LKE

RX

D0

ER

XE

R

ETX

ER

ETX

CLK

ER

XD

1

ETX

D2

ETX

EN

EC

RS

EM

DC

U0T

XD

EX

TAL

/U1R

TS

/SD

_CA

S

/TE

A

XTA

L

U2R

XD

/TA

DD

ATA

[3:0

]

/SD

_CS

1

U1T

XD

/SD

_CS

0

PS

T[3:

0]

TDO

/DS

O

/U0C

TS

TDI/D

SI

EM

DIO

/RE

SE

T

/SD

_SC

KE

UTP

UO

DIS

U1R

XD

CA

N0T

X

/SD

_RA

S

TRS

T/D

SC

LK

TCLK

/PS

TCLK

TSIZ

1

/TIP

CA

N1R

X

I2C

_SC

L

CA

N0R

X

TMS

/BK

PT

/U0R

TS

QS

PI_

PC

S0

/U1C

TS

I2C

_SD

A

U2T

XD

/SD

_WE

CA

N1T

X

/U2R

TS/U

2CTS

CLK

OU

T

LTP

UO

DIS

/RC

ON

/BS

[3:0

]

/OE

CLK

MO

D[1

:0]

DTI

N0

DTO

UT1

DTI

N2

DTO

UT2

DTI

N3

TCR

CLK

TPU

CH

[15:

0]TP

UC

H[3

1:16

]

A[2

3:0]

B_D

[31:

0]B

_A[2

3:0]

/CS

[7:0

]

JTA

G_E

N

/TS

TSIZ

0

DTO

UT0

DTI

N1

DTO

UT3

R/W

ETP

U/E

TH

D[3

1:0]

QS

PI_

PC

S1

QS

PI_

DO

UT

QS

PI_

DIN

QS

PI_

SC

K

/IRQ

[7:1

]

/RS

TOU

T

U0R

XD

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Hie

rarc

hica

l Blo

ck D

iagr

amC

M52

3xE

VB

C

216

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Hie

rarc

hica

l Blo

ck D

iagr

amC

M52

3xE

VB

C

216

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Hie

rarc

hica

l Blo

ck D

iagr

amC

M52

3xE

VB

C

216

Frid

ay, A

ugus

t 10,

200

7

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

She

et 1

5S

eria

l I/O

U2TXD

U1TXD

U0RXD

/U1RTS

/U0CTSU0TXD

/U1CTS

/U0RTS

U2RXD

U1RXD

QSPI_DIN

QSPI_PCS1

QSPI_DOUTQSPI_PCS0

QSPI_SCK

I2C_SCLI2C_SDA

CANH1CANL1

/U2RTS/U2CTS

/RSTOUT/IRQ[7:1]

She

et 3

MR

AM

B_A[23:0]

/BS[3:0]

/OE

B_D[31:0]

R/W

/CS[7:0]

She

et 1

3R

eset

Con

fig &

Clo

cks

/RESET/BDM_RSTIN

/EXT_RSTIN

XTALEXTAL

ETH_CLK/IRQ[7:1]

D[31:0]

JTAG_EN/RCON

CLKMOD[1:0]/RSTOUT

CLKOUT

/CS[7:0]

/BS[3:0]

LTPUODISUTPUODIS

/OER/W/TS

/TIP/TA

/TEA

TSIZ0

TSIZ1

DTIN0DTOUT0

DTIN1

DTIN2

DTIN3

DTOUT1

DTOUT2

DTOUT3

TMS/BKPTTDI/DSI

TDO/DSOTRST/DSCLK

ETPU/ETH

She

et 5

CA

N

CAN0RXCAN0TX

CAN1TXCAN1RX

CANH1CANL1

She

et 7

Deb

ug

DDATA[3:0]

PST[3:0]

TCLK/PSTCLK

TDO/DSO

TMS/BKPT

TDI/DSI

TRST/DSCLK

/TA

BDM_/RSTIN

She

et 4

Buf

fers

A[23:0]

B_A[23:0]

D[31:0]

B_D[31:0]

R/W

/CS[7:0]

She

et 1

1Fl

ash

Mem

ory

B_A[23:0]B_D[31:0]/CS[7:0]

/OE

R/W

She

et 1

4S

DR

AM

/BS[3:0]

/SD_CS0

/SD_WESD_SCKE

D[31:0]

/SD_RAS

A[23:0]

CLKOUT

/SD_CAS

She

et16

US

B

B_D[31:0]

/RSTOUT

B_A[23:0]

/CS[7:0]

/OER/W

/IRQ[7:1]

DTIN1

DTIN2DTOUT1

DTOUT2

She

et 1

0

Exp

ansi

on C

onne

ctor

s

TPU

CH

[15:

0]TP

UC

H[3

1:16

]

TCR

CLK

/U0C

TS

U0R

XD

DTO

UT0

DTI

N0

U0T

XD

/U0R

TS

CLK

MO

D[1

:0]

D[3

1:0]

/EX

T_R

STI

N

/OE

DTO

UT1

DTI

N1

/IRQ

[7:1

]

TSIZ

0

TCLK

/PS

TCLK

DTO

UT2

DTI

N2

TDI/D

SI

TDO

/DS

O

TMS

/BK

PT

TRS

T/D

SC

LK

PS

T[3:

0]D

DA

TA[3

:0]

JTA

G_E

N/R

CO

N

/RS

TOU

T/R

ES

ET

EX

TAL

XTA

L

/SD

_CS

1

CLK

OU

T

/SD

_CA

S

/SD

_CS

0/S

D_R

AS

R/W

CA

N0T

XC

AN

0RX

/SD

_WE

/TS

/TIP /TA

/TE

A

DTO

UT3

DTI

N3

LTP

UO

DIS

UTP

UO

DIS

A[2

3:0]

/CS

[7:0

]

TSIZ

1

U1T

XD

U1R

XD

/U1R

TS

U2T

XD

/U1C

TS

CA

N1T

X

U2R

XD

CA

N1R

X

SD

_SC

KE

QS

PI_

PC

S1

/BS

[3:0

]

QS

PI_

PC

S0

QS

PI_

DO

UT

QS

PI_

DIN

I2C

_SD

A

QS

PI_

SC

K

I2C

_SC

L

EM

DC

EM

DIO

/U2C

TS/U

2RTS

She

et 6

CP

U A[2

3:0]

D[3

1:0]

/CS

[7:0

]

U1T

XD

/BS

[3:0

]

/OE

/IRQ

[7:1

]

TSIZ

0TS

IZ1

CLK

MO

D[1

:0]

DTO

UT1

DTI

N1

DTO

UT2

DTI

N2

TCLK

/PS

TCLK

PS

T[3:

0]D

DA

TA[3

:0]

XTA

LE

XTA

L

/SD

_CS

1/S

D_C

S0

JTA

G_E

N

CLK

OU

T

/SD

_RA

S/S

D_C

AS

R/W

CA

N0R

XC

AN

0TX

/SD

_WE

/TS

/TIP

/TA

/TE

A

DTO

UT3

DTI

N3

LTP

UO

DIS

UTP

UO

DIS

TPU

CH

[15:

0]

U0R

XD

QS

PI_

PC

S1

/U1C

TS

/RS

TOU

T

/RC

ON

DTO

UT0

TDO

/DS

O

/U0C

TS

SD

_SC

KE

/U1R

TS

TRS

T/D

SC

LK

QS

PI_

DO

UT

/U0R

TS

QS

PI_

PC

S0

U1R

XD

TMS

/BK

PT

U0T

XD

QS

PI_

DIN

U2R

XD

TDI/D

SI

QS

PI_

SC

K

U2T

XD

DTI

N0

TPU

CH

[31:

16]

EM

DIO

EM

DC

TCR

CLK

/RE

SE

T

CA

N1R

XC

AN

1TX

I2C

_SD

AI2

C_S

CL

ER

XE

R

ETX

D2

ETX

D1

ETX

EN

ETX

D3

ETX

ER

ER

XD

0E

RX

D1

ER

XD

2E

RX

D3

ER

XC

LK

ER

XD

V

ETX

CLK

ETX

D0

EC

OL

EC

RS

/U2R

TS/U

2CTS

ETP

U/E

TH

She

et 9

eTP

U

TCRCLKUTPUODISLTPUODISTPUCH[15:0]TPUCH[31:16]

QSPI_DINQSPI_SCK

QSPI_DOUTQSPI_PCS0

/TIP/TEATSIZ0TSIZ1

She

et 1

2P

SU

She

et 8

Eth

erne

t

/RSTOUT

ETH_CLK

EMDIOEMDC

/IRQ[7:1]

ECOLECRSERXDVERXERERXCLKERXD0ERXD1ERXD2ERXD3ETXENETXERETXCLKETXD0ETXD1ETXD2ETXD3



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

B_A

[23:

0]

/BS

2

B_D

20

B_A

[23:

0]

/BS

0/C

S1

B_A

[23:

0]

/BS

1

/BS

3

/BS[3:0]

/CS

1

B_D

10

B_D

18

B_D

11

B_D

24

B_D

16

B_D

13

B_D

5

B_D

0

B_D

8

B_D

19

B_D

25

B_D

17

B_D

7

B_D

12

B_D

1

B_D

28

B_D

31

B_D

23

B_D

26

B_D

[31:

0]

B_D

[31:

0]

B_D

15

B_D

22

B_D

29

B_D

21B

_D27

B_D

9

B_D

2B

_D3

B_D

6

B_D

4

B_D

14

B_D

30

B_A

5

B_A

3

B_A

18

B_A

18

B_A

9

B_A

7

B_A

4

B_A

10B

_A11

B_A

17

B_A

2

B_A

5

B_A

19

B_A

14

B_A

19

B_A

9B

_A15

B_A

15

B_A

12

B_A

4

B_A

2

B_A

10

B_A

7

B_A

16

B_A

3

B_A

6

B_A

13

B_A

12B

_A11

B_A

16B

_A8

B_A

13

B_A

17

B_A

6

B_A

8B

_A14

/CS

[7:0

]

B_A

[23:

0]

/BS

[3:0

]

/OE

B_D

[31:

0]

/CS

[7:0

]

R/W

+3.3

V+3

.3V

+3.3

V+3

.3V

+3.3

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

MR

AM

C

M52

3xE

VB

B

316

Tues

day,

Aug

ust 1

4, 2

007

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

MR

AM

C

M52

3xE

VB

B

316

Tues

day,

Aug

ust 1

4, 2

007

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

MR

AM

C

M52

3xE

VB

B

316

Tues

day,

Aug

ust 1

4, 2

007

MR

AM

Upp

er 1

6-bi

t wor

d

NO

TE: /

BS

3 se

lect

s th

e m

ost

sign

ifica

nt b

yte

lane

acc

ess

and

/BS

0 th

e le

ast s

igni

fican

t.

MR

AM

Low

er 1

6-bi

t wor

d

TSO

P II

TSO

P II

Eac

h M

RA

M is

256

K x

16b

it (5

12K

B)

Tota

l MR

AM

ava

ilabl

e =

1MB

NO

TE: A

SR

AM

's w

ith th

e sa

me

PC

B fo

otpr

int

and

func

tiona

lity

are

:- R

enes

as H

M62

W16

255H

CJP

-12,

Cyp

ress

CY

7C10

41C

V33

10ZC

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

C8

0.1u

FC

80.

1uF

C2

1nF

C2

1nF

C3

1nF

C3

1nF

C7

0.1u

FC

70.

1uF

U1

MR

2A16

ATS

35C

U1

MR

2A16

ATS

35C

A0

1A

12

A2

3A

34

A4

5/C

E6

I/00

7I/0

18

I/02

9I/0

310

VC

C11

VS

S12

I/04

13I/0

514

I/06

15I/0

716

/WE

17A

518

A6

19A

720

A8

21A

922

A10

23A

1124

A12

25A

1326

A14

27N

C28

I/O8

29I/O

930

I/O10

31I/O

1132

VC

C33

VS

S34

I/O12

35I/O

1336

I/O14

37I/O

1538

/BLE

39/B

HE

40/O

E41

A15

42A

1643

A17

44

C4

1nF

C4

1nF

C6

0.1u

FC

60.

1uF

U2

MR

2A16

ATS

35C

U2

MR

2A16

ATS

35C

A0

1A

12

A2

3A

34

A4

5/C

E6

I/00

7I/0

18

I/02

9I/0

310

VC

C11

VS

S12

I/04

13I/0

514

I/06

15I/0

716

/WE

17A

518

A6

19A

720

A8

21A

922

A10

23A

1124

A12

25A

1326

A14

27N

C28

I/O8

29I/O

930

I/O10

31I/O

1132

VC

C33

VS

S34

I/O12

35I/O

1336

I/O14

37I/O

1538

/BLE

39/B

HE

40/O

E41

A15

42A

1643

A17

44

C5

0.1u

FC

50.

1uF

C1

1nF

C1

1nF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

B_A

18

B_A

15

B_D

17

D7

A0

B_D

8

D18

D28

D[3

1:0]

B_A

17

A18

B_D

16

A11

A7

B_D

30

D10

D23

B_D

21

B_D

10

D30

B_D

1D

2

B_A

19

B_A

4

B_D

18

D20

B_D

[31:

0]

A1

D8

B_D

9

D16

A19

B_D

13

B_D

2

D6

B_D

26

A12

A8

D17

B_D

31

B_D

11

B_D

22

B_A

20

B_A

5

B_D

19

A2

B_D

27

B_D

3

A13

A9

D11

B_D

12

D0

B_A

21

B_A

6

A20

A3

B_A

10

A15

D9

B_D

28

A14

B_A

22

B_A

7

B_D

0

B_D

23

D19

D22

D21

D24

A4

D25

B_A

0

B_A

11

B_D

4

B_A

16

B_A

8

D5

A[2

3:0]

B_D

24

D3

A21

D26

B_A

12

B_A

1

B_D

5

D14

B_A

[23:

0]

B_A

9

D12

B_D

25

B_A

2

B_A

13

B_D

6

D13

D15

A22

A16

B_D

14

A5

B_A

14

B_A

3

D4

B_D

7

D1

D27

A17

B_D

15

A10

A6

B_D

29

B_D

20

D31

D29

B_A

23A

23

/CS

2

/CS

0

/CS

1

D[3

1:0]

B_D

[31:

0]

R/W

A[2

3:0]

B_A

[23:

0]

/CS

[7:0

]

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Buf

fers

C

M52

3xE

VB

B

416

Tues

day,

Aug

ust 1

4, 2

007

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Buf

fers

C

M52

3xE

VB

B

416

Tues

day,

Aug

ust 1

4, 2

007

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Buf

fers

C

M52

3xE

VB

B

416

Tues

day,

Aug

ust 1

4, 2

007

AD

DR

ES

S B

US

BU

FFE

RS

Add

ress

and

Dat

a B

us b

uffe

rs/tr

ansc

eive

rs u

sed

to b

uffe

rth

e si

gnal

s fo

r the

MR

AM

and

Fla

sh m

emor

ies

and

the

US

B c

ontro

ller.

DA

TA B

US

TR

AN

SC

EIV

ER

S

AN

D G

ate

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

C14

1nF

C14

1nF

U4

MC

74LC

X16

245D

T

U4

MC

74LC

X16

245D

T

1B1

21B

23

1B3

51B

46

1B5

81B

69

1B7

111B

812

2B1

132B

214

2B3

162B

417

2B5

192B

620

2B7

222B

823

1DIR

11O

E48

2OE

252D

IR24

GN

D4

GN

D10

GN

D15

GN

D21

GN

D28

GN

D34

GN

D39

GN

D45

1A1

471A

246

1A3

441A

443

1A5

411A

640

1A7

381A

837

2A1

362A

235

2A3

332A

432

2A5

302A

629

2A7

272A

826

VC

C7

VC

C18

VC

C31

VC

C42

RP

2

4x 4

.7K

RP

2

4x 4

.7K

11

22

33

44

55

66

77

88

U7

MC

74LC

X24

5DT

U7

MC

74LC

X24

5DT

T/R

1A

02

A1

3A

24

A3

5A

46

A5

7A

68

A7

9G

ND

10

VC

C20

OE

19B

018

B1

17B

216

B3

15B

414

B5

13B

612

B7

11

C11

0.1u

FC

110.

1uF

U3

MC

74LC

X16

245D

T

U3

MC

74LC

X16

245D

T

1B1

21B

23

1B3

51B

46

1B5

81B

69

1B7

111B

812

2B1

132B

214

2B3

162B

417

2B5

192B

620

2B7

222B

823

1DIR

11O

E48

2OE

252D

IR24

GN

D4

GN

D10

GN

D15

GN

D21

GN

D28

GN

D34

GN

D39

GN

D45

1A1

471A

246

1A3

441A

443

1A5

411A

640

1A7

381A

837

2A1

362A

235

2A3

332A

432

2A5

302A

629

2A7

272A

826

VC

C7

VC

C18

VC

C31

VC

C42

C9

0.1u

FC

90.

1uF

C15

1nF

C15

1nF

RP

1

4x 4

.7K

RP

1

4x 4

.7K

11

22

33

44

55

66

77

88

U6

MC

74LC

X16

245D

T

U6

MC

74LC

X16

245D

T

1B1

21B

23

1B3

51B

46

1B5

81B

69

1B7

111B

812

2B1

132B

214

2B3

162B

417

2B5

192B

620

2B7

222B

823

1DIR

11O

E48

2OE

252D

IR24

GN

D4

GN

D10

GN

D15

GN

D21

GN

D28

GN

D34

GN

D39

GN

D45

1A1

471A

246

1A3

441A

443

1A5

411A

640

1A7

381A

837

2A1

362A

235

2A3

332A

432

2A5

302A

629

2A7

272A

826

VC

C7

VC

C18

VC

C31

VC

C42

C12

1nF

C12

1nF

U5 SN

74LV

C1G

11

U5 SN

74LV

C1G

11

A GN

DB

CV

CC Y

C10

0.1u

FC

100.

1uF

C13

1nF

C13

1nF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CA

NL1

CA

NH

1

CA

N1R

X

CA

N1T

X

CA

N0R

X

CA

N0T

X

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

CA

N T

rans

ceiv

ers

C

M52

3xE

VB

B

516

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

CA

N T

rans

ceiv

ers

C

M52

3xE

VB

B

516

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

CA

N T

rans

ceiv

ers

C

M52

3xE

VB

B

516

Frid

ay, A

ugus

t 10,

200

7

Def

ault

setti

ng fo

r JP

2 is

fitte

d.

Def

ault

setti

ng fo

r JP

4 is

fitte

d.

Def

ault

setti

ng fo

r JP

1 is

NO

T fit

ted.

CA

N B

us C

onne

ctor

- 9

way

D-ty

pe(F

emal

e)

CA

N1

and

UA

RT2

sha

re th

e sa

me

DB

9 co

nnec

tor o

n S

heet

15

Def

ault

setti

ng fo

r JP

3 is

NO

T fit

ted.

CAN

Cha

nnel

0

CAN

Cha

nnel

1

Tran

scei

ver M

ode

CA

N T

erm

inat

ion

CA

N T

erm

inat

ion

Tran

scei

ver M

ode

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

JP1

JP1

12

C17

0.1u

FC

170.

1uF

U8

SN

65H

VD

230D

U8

SN

65H

VD

230D

D1

GN

D2

VC

C3

R4

VR

EF

5C

AN

L6

CA

NH

7R

S8

JP3

JP3

12

R4

62R4

62C

181n

FC

181n

F

U9

SN

65H

VD

230D

U9

SN

65H

VD

230D

D1

GN

D2

VC

C3

R4

VR

EF

5C

AN

L6

CA

NH

7R

S8

JP2

JP2

12

R1

1KR1

1K

R2

62R2

62

C19

1nF

C19

1nF

JP4

JP4

12

R3

1KR3

1K

P1

P1

5 9 4 8 3 7 2 6 1

C16

0.1u

FC

160.

1uF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CLK

MO

D[1

:0]

A[2

3:0]

PST0

/IRQ3

D31

TPU

CH

11

TPU

CH

10

/CS

[7:0

]

/CS7

A10

A5

A1

A3

/IRQ1

D3

D17

CLK

MO

D1

/BS0

A16

D21

D29

A23

/CS3

DDATA0

D5

CLK

MO

D0

TPU

CH

14

D[31:0]

A[23:0]

D27

TPU

CH

8

D14

/BS3/BS2

A14

/IRQ7

D18

D23

A20

A15

A0

D0

D1

D6

A8

D8

D15

D13

D20

TPU

CH

13

/BS

[3:0

]

A19

A12

A13

A7

DD

ATA

[3:0

]

PST1

D11

D9

/CS6

/CS4

A17

D19

D26

D30

TPU

CH

12

PS

T[3:

0]

/BS1

A6

/IRQ5/IRQ4

D10

D16

D12

D28

/IRQ

[7:1

]

D[3

1:0]

A21

A18

PST2

D2

A11

A9

A2

D22

D24

TPU

CH

15

TPU

CH

7

PST3/CS0

/CS1/CS5

TPU

CH

4

TPU

CH

0

TPU

CH

3

TPU

CH

1

TPU

CH

5TP

UC

H6

TPU

CH

2

TPUCH[15:0]

DDATA3

TPU

CH

19

TPU

CH

29

TPU

CH

28

TPU

CH

31

TPUCH[31:16]

TPU

CH

16

TPU

CH

23

TPU

CH

22

TPU

CH

27

TPU

CH

26

TPU

CH

17

TPU

CH

18

TPU

CH

21

TPU

CH

20

TPU

CH

25

TPU

CH

24

TPU

CH

30

A4

DDATA1

D7

/IRQ2

D4

D25

A22

DDATA2

/IRQ6

/CS2

TPU

CH

9

A[2

3:0]

D[3

1:0]

/CS

[7:0

]

U1TXD

/BS

[3:0

]

/OE

/IRQ

[7:1

]

TSIZ0TSIZ1

CLK

MO

D[1

:0]

DTOUT1DTIN1

DTOUT2DTIN2

TCLK/PSTCLK

PS

T[3:

0]

DD

ATA

[3:0

]

XTA

L

EX

TAL

/SD

_CS

1

/SD

_CS

0

JTA

G_E

N

CLK

OU

T

/SD

_RA

S/S

D_C

AS

R/W

CA

N0R

XC

AN

0TX

/SD

_WE

/TS

/TIP

/TA

/TE

AD

TOU

T3

DTI

N3

LTP

UO

DIS

UTP

UO

DIS

TPU

CH

[15:

0]

U0R

XD

QSPI_PCS1

/U1CTS

/RSTOUT

/RCON

DTO

UT0

TDO/DSO

/U0C

TS

SD_SCKE

/U1RTS

TRST/DSCLK

QSPI_DOUT

/U0R

TS

QSPI_PCS0

U1RXD

TMS/BKPT

U0T

XD

QS

PI_

DIN

TDI/DSI

QS

PI_

SC

K

DTI

N0

EMDIOEMDC

TCR

CLK

/RESET

U2R

XD

CA

N1R

X

U2T

XD

CA

N1T

X

ETX

CLK

ETX

D1

ER

XE

R

ETX

EN

ETX

D2

ETX

ER

ETX

D3

ETX

D0

ER

XD

0

ER

XD

1

ER

XD

2

ER

XD

3

ER

XC

LK

ER

XD

V

EC

OL

EC

RS

TPU

CH

[31:

16]

I2C

_SD

AI2

C_S

CL

/U2C

TS

/U2R

TS

ETP

U/E

TH

+1.5

VP

+3.3

VP

+3.3

VP

VS

SP

LLV

SS

PLL

VS

SP

LL

+3.3

VP

+3.3

VP

+1.5

VP

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

CP

UC

M52

3xE

VB

C

616

Tues

day,

Aug

ust 1

4, 2

007

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

CP

UC

M52

3xE

VB

C

616

Tues

day,

Aug

ust 1

4, 2

007

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

CP

UC

M52

3xE

VB

C

616

Tues

day,

Aug

ust 1

4, 2

007

NO

TE: P

lace

C33

, C34

& L

1 as

clo

seto

pin

s P

15 &

R15

as

poss

ible

usi

ng a

sepa

rate

gro

und

plan

e.

Pla

ce R

5 as

clos

e to

pin

C10

as p

ossi

ble.

Pla

ce R

6 as

clos

e to

pin

N15

as p

ossi

ble.

Pla

ce R

P3

as c

lose

to p

ins,

L13,

M13

, M14

& M

15 a

spo

ssib

le.

PLL

Filt

er C

ircu

it

eTP

U/E

ther

net E

nabl

e- s

ee p

age

13

256M

apB

GA

Def

ault

setti

ng fo

r JP

5, J

P9,

JP

10,

JP11

, JP

13-2

4 is

2 &

3 c

onne

cted

Def

ault

setti

ng fo

rJP

6 &

JP

8 is

pin

s 1&

2D

efau

lt se

tting

for J

P7

& J

P11

is p

ins

2&3

Def

ault

setti

ng fo

r JP

25 &

JP26

is b

ewte

en p

ins

1&2

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

Mot

orol

a C

oldF

ire

Mic

ropr

oces

sor M

CF5

235

TM

JP5

JP5

12

3

C18

50.

1uF

C18

50.

1uF

R28

22R

2822

C29

0.1u

FC

290.

1uF

JP10

JP10

12

3

JP13

JP13

12

3

C18

70.

1uF

C18

70.

1uF

C21

100p

FC

2110

0pF

JP15

JP15

12

3

JP6

JP6

12

3

JP16

JP16

12

3

C25

1nF

C25

1nF

C31

0.1u

FC

310.

1uF

C18

31n

FC

183

1nF

U10

MC

F523

5

U10

MC

F523

5

VS

SA

1

TPU

CH

8B

1TP

UC

H7

B2

TPU

CH

10C

1TP

UC

H9

C2

TPU

CH

25/E

RX

D1

C3

TPU

CH

12D

1TP

UC

H11

D2

TPU

CH

27/E

RX

D3

D3

TPU

CH

26/E

RX

D2

D4

TPU

CH

14E

1TP

UC

H13

E2

TPU

CH

29/E

RX

CLK

E3

TPU

CH

28/E

RX

DV

E4

TCR

CLK

F1TP

UC

H15

F2TP

UC

H31

/EC

OL

F3TP

UC

H30

/EC

RS

F4

U0C

TSG

1U

0RX

DG

2

DTO

UT0

G3

DTI

N0

G4

Cor

e V

DD

H1

U0T

XD

H2

U0R

TSH

3

NC

H4

VS

SJ1

CLK

MO

D0

J2C

LKM

OD

1J3

D28

K1

D29

K2

D30

K3

D31

K4

D24

L1D

25L2

D26

L3D

27L4

D21

M1

D22

M2

D23

M3

D19

N1

D20

N2

D13

N3

D9 N4

D17

P1

D18

P2

D12 P3

D16

R1

D15 R2

VSS T1

D14 T2

D10 T3D11 R3

D6 T4D7 R4D8 P4

Core VDD T5

D4 R5D5 P5

VSS T6

D1 R6D2 P6D3 N6

OE T7

DTOUT1 R7DTIN1 P7

D0 N7

IRQ6 T8IRQ7 R8

TES

TJ4

eTP

U/E

thE

NB

M4

NC N5

TSIZ0 P8TSIZ1 N8

IRQ2 T9IRQ3 R9IRQ4 P9IRQ5 N9

TCLK/PSTCLK T10DTOUT2 R10DTIN2 P10

IRQ1 N10

TDI/DSI T11TDO/DSO R11TMS/BKPT P11TRST/DSCLK N11

PST3 T12PST2 R12PST1 P12PST0 N12

DDATA1 T13DDATA0 R13

RCON P13

RSTOUT T14

PLL_TEST R14

RESET T15VS

ST1

6

XTA

LR

16

VS

SP

LLR

15

EX

TAL

P16

VD

DP

LLP

15

DD

ATA

2P

14

VS

SN

16

SD

_CS

1N

15

DD

ATA

3N

14

JTA

G_E

NN

13

CLK

OU

TM

16

SD

_CA

SM

15S

D_R

AS

M14

SD

_CS

0M

13

R/W

L16

I2C

_SD

A/C

AN

0RX

L15

I2C

_SC

L/C

AN

0TX

L14

SD

_WE

L13

TSK

16TI

PK

15TA

K14

TEA

K13

DTO

UT3

/U2R

TSJ1

6D

TIN

3/U

2CTS

J15

LTP

UO

DIS

J14

UTP

UO

DIS

J13

A3

H16

A2

H15

A1

H14

A0

H13

Cor

e V

DD

G16

A6

G15

A5

G14

A4

G13

VS

SF1

6

A9

F15

A8

F14

A7

F13

A13

E16

A12

E15

A11

E14

A10

E13

A16

D16

A15

D15

A14

D14

CS0D13

A17

C16

A18

C15

A22C14

A19

B16

A20B15

VSSA16

A21A15

CS4A14

A23B14

CS6A13 CS1B13 CS5C13

U1TXDA12

CS3B12 CS7C12 CS2D12

U1RXDA11 U1RTSB11 U1CTSC11 U2TXD/CAN1TXD11

BS0A10

QSPI_PCS1B10

SD_SCKEC10

U2RXD/CAN1RXD10

BS1A9 BS2B9 BS3C9

QSPI_PCS0D9

Core VDDA8

QSPI_SCK/I2C_SCLB8 QSPI_DIN/I2C_SDAC8 QSPI_DOUTD8

TPUCH0A7 TPUCH16/ETXD0B7

EMDIOC7 EMDCD7

TPUCH1A6 TPUCH19/ETXD3B6 TPUCH20/ETXERC6 TPUCH21/ETXEND6

TPUCH17/ETXD1A5 TPUCH18/ETXD2B5 TPUCH22/ETXCLKC5 TPUCH23/ERXERD5 TPUCH2A4 TPUCH3B4 TPUCH24/ERXD0C4 TPUCH4A3 TPUCH5B3 TPUCH6A2

VS

SE

5

VD

DF5

VS

SF6

VD

DG

5V

DD

G6

VS

SG

7

VD

DH

5V

DD

H6

VS

SH

7V

SS

H8

VD

DJ5

VD

DJ6

VS

SJ7

VD

DK

5V

DD

K6

VD

DL5

VSS M5

VDD M6VSS L6

VDD M7VDD L7VSS K7

VDD M8VDD L8VSS K8VSS J8

VDD M9VDD L9VSS K9

VDD M10VDD L10

VDD M11

VS

SM

12

VD

DL1

2V

SS

L11

VD

DK

12V

DD

K11

VS

SK

10

VD

DJ1

2V

DD

J11

VS

SJ1

0V

SS

J9

VD

DH

12V

DD

H11

VS

SH

10

VD

DG

12V

DD

G11

VD

DF1

2

VSSE12

VDDE11 VSSF11

VDDE10 VDDF10 VSSG10

VDDE9 VDDF9 VSSG9 VSSH9

VDDE8 VDDF8 VSSG8

VDDE7 VDDF7

VDDE6

JP19

JP19

12

3

C18

40.

1uF

C18

40.

1uF

C22

100p

FC

2210

0pF

VIA

2V

IA21

JP21

JP21

12

3

C18

110

0pF

C18

110

0pF

JP26

JP26

12

3

JP23

JP23

12

3

C32

10uF

TA

NT.

C32

10uF

TA

NT.

C34

1000

pFC

3410

00pF

L1 10uH

L1 10uH

C23

100p

FC

2310

0pF

C18

60.

1uF

C18

60.

1uF

C18

21n

FC

182

1nF

JP9

JP9

12

3

RP

3

4x 2

2

RP

3

4x 2

211

22

33

44

55

66

77

88

JP11

JP11

12

3R

522

R5

22

C33

0.1u

FC

330.

1uF

JP12

JP12

12

3

C28

0.1u

FC

280.

1uF

JP14

JP14

12

3

C27

1nF

C27

1nF

JP17

JP17

12

3

JP8

JP8

12

3

JP7

JP7

12

3

JP18

JP18

12

3

JP20

JP20

12

3

C26

1nF

C26

1nF

C30

0.1u

FC

300.

1uF

VIA

1V

IA1

1

C18

010

0pF

C18

010

0pF

C20

100p

FC

2010

0pF JP

25JP

25

12

3

JP22

JP22

12

3

R6

22R6

22

R29

22R29

22

TP1 PLL Test Point

TP1 PLL Test Point1

JP24

JP24

12

3

C24

1nF

C24

1nF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DD

ATA

2D

DA

TA1

DD

ATA

0

DD

ATA

[3:0

]

PS

T0

DD

ATA

[3:0

]

PS

T3P

ST2

DD

ATA

3P

ST1

PS

T[3:

0]P

ST[

3:0]

DD

ATA

[3:0

]

PS

T[3:

0]

TDO

/DS

O

TMS

/BK

PT

TDI/D

SI

TRS

T/D

SC

LK

BD

M_/

RS

TIN

/TA

TCLK

/PS

TCLK

+1.5

V+3

.3V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

BD

M/J

TAG

Deb

ug P

ort

C

M52

3xE

VB

A

716

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

BD

M/J

TAG

Deb

ug P

ort

C

M52

3xE

VB

A

716

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

BD

M/J

TAG

Deb

ug P

ort

C

M52

3xE

VB

A

716

Frid

ay, A

ugus

t 10,

200

7

Def

ault

setti

ng fo

rJP

27 is

fitte

d.

NO

TE: J

P27

is re

quire

d fo

r som

e of

the

lega

cy B

DM

cabl

es th

at c

onne

ct p

ins

9 &

25

of th

e B

DM

inte

rface

inte

rnal

ly. M

ore

rece

nt c

able

s su

ppor

t bot

h co

re &

I/O

volta

ges.

Ple

ase

chec

k w

ith y

our B

DM

cab

le s

uppl

ier.

Cor

e V

olta

ge

IMP

OR

TAN

T N

OTE

: ON

LY 3

.3V

BD

M d

ebug

ging

cab

les

can

be u

sed

with

the

MC

F523

x pr

oces

sors

.

I/O V

olta

ge

NO

TE: 4

.7K

pul

l up

resi

stor

s ar

e us

ed o

n si

gnal

s /B

KP

T, D

SC

LK, D

SI,

DS

O&

/RE

SE

T. A

1K

pul

l up

is u

sed

for /

TA. S

ee p

age

13 o

f the

sch

emat

ics.

Def

ault

setti

ng -

FITT

ED

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

JP28

JP28

12

R7

10K

R7

10K

J1J1 1 3 5 7 9 11 13 15 17 19 21 23 25

2 4 6 8 10 12 14 16 18 20 22 24 26

JP27

JP27

12



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

/IRQ

[7:1

]/IR

Q2

/RS

TOU

T

ETH

_CLK

EM

DIO

EM

DC

/IRQ

[7:1

]

ER

XD

3E

RX

D2

ER

XD

1E

RX

D0

ER

XD

VE

RX

CLK

ER

XE

RE

TXC

LK

ETX

ER

ETX

EN

ETX

D0

ETX

D1

ETX

D2

ETX

D3

EC

OL

EC

RS

+3.3

V

+3.3

V

+2.5

VP

LL+2

.5V

A

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+2.5

VA

+2.5

VA

+2.5

VA

+2.5

VA

+2.5

VA

+2.5

VA

+2.5

VP

LL

+2.5

V

+2.5

V

+2.5

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

10/

100B

aseT

Eth

erne

t Tra

nsce

iver

C

M52

3xE

VB

B

816

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

10/

100B

aseT

Eth

erne

t Tra

nsce

iver

C

M52

3xE

VB

B

816

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

10/

100B

aseT

Eth

erne

t Tra

nsce

iver

C

M52

3xE

VB

B

816

Frid

ay, A

ugus

t 10,

200

7

Pla

ce s

ilk s

cree

n LE

D la

bels

next

to D

1 th

ru' D

4.

Sep

arat

e R

J45

conn

ecto

rch

assi

s gr

ound

.

NO

TE: E

ther

net C

h. p

hysi

cal a

ddr.

defa

ult s

ettin

g is

add

r. =

1 se

lect

ed v

ia in

tern

al re

sist

or b

iasi

ng d

urin

g re

set.

Pla

ce R

P4

& R

P5

as c

lose

to U

11 a

s po

ssib

le.

Pla

ce R

P6

& R

P7

as c

lose

to th

eM

CF5

23x

(CP

U) a

s po

ssib

le.

Link

LE

D

Col

lisio

nLE

D

100B

T LE

D

Full

Dup

lex

LED

Ana

log

Eth

erne

t Pla

ne

GR

EE

N

GR

EE

N

GR

EE

N

GR

EE

N

Pla

ce th

e ca

paci

tors

abo

vecl

ose

to p

ins

7 an

d 24

on

U11

.

Pla

ce R

8, R

9, R

10 &

R11

clo

se to

U11

.

NO

TE: U

11 K

S87

21B

L ha

s an

on-

chip

LD

O th

atde

rives

the

+2.5

V s

uppl

y fro

m th

e +3

.3V

sup

ply.

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

NO

TE: R

P27

is p

rese

nt to

ens

ure

the

corr

ect c

onfig

urat

ion

of U

11ou

t of r

eset

.

C44

0.1u

FC

440.

1uF

D3

D3

R8

49.9

1%

R8

49.9

1%

C45

47uF

C45

47uF

R12

4.7K

R12

4.7K

C46

0.1u

FC

460.

1uF

C48

0.1u

FC

480.

1uF

U11

KS

8721

BL

U11

KS

8721

BL

MD

IO1

MD

C2

RX

D3/

PH

YA

D1

3R

XD

2/P

HY

AD

24

RX

D1/

PH

YA

D3

5R

XD

0/P

HY

AD

46

VD

DIO

7G

ND

8R

XD

V/P

CS

_LP

BK

9R

XC

10R

XE

R/IS

O11

GN

D12

VDDC 13TXER 14TXC/REFCLK 15TXEN 16TXD0 17TXD1 18TXD2 19TXD3 20COL/RMII 21CRS/RMII_LPBK 22GND 23VDDIO 24IN

T#/P

HY

AD

025

LED

0/TE

ST

26LE

D1/

SP

D10

027

LED

2/D

UP

LEX

28LE

D3/

NW

AY

EN

29P

D#

30V

DD

RX

31R

X-

32R

X+

33FX

SD

/FX

EN

34G

ND

35G

ND

36

REXT37 VDDRCV38 GND39 TX-40 TX+41 VDDTX42 GND43 GND44 XO45 XI46 VDDPLL47 RST#48

RP

6

4x 5

1

RP

6

4x 5

1

1 1223 3445 5667 788

C42

0.1u

FC

420.

1uF

R17

220

R17

220

R15

220

R15

220

C40

0.1u

FC

400.

1uF

C38

0.1u

FC

380.

1uF

C50

10nF

C50

10nF

J2 Hal

o H

FJ11

-245

0E

J2 Hal

o H

FJ11

-245

0E

TX+

1TX

-2

RX

+3

CT_

TX4

CT_

RX

5R

X-

6N

C7

GN

D8

D2

D2

C36

0.1u

FC

360.

1uF

C35

0.1u

FC

350.

1uF

FB2

STE

WA

RD

HI1

206T

500R

-00

FB2

STE

WA

RD

HI1

206T

500R

-00

12

RP

27

4x 1

8K

RP

27

4x 1

8K

1 1223 3445 5667 788

R10

49.9

1%

R10

49.9

1%

C51

10uF

C51

10uF

R18

220

R18

220

C43

0.1u

FC

430.

1uF

C39

1nF

C39

1nF

RP

54x

51

RP

54x

51

11

22

33

44

55

66

77

88

C47

0.1u

FC

470.

1uF

R13

6.49

K 1

%

R13

6.49

K 1

%

D4

D4

R11

49.9

1%

R11

49.9

1%

RP

44x

51

RP

44x

51

11

22

33

44

55

66

77

88

RP

7

4x 5

1

RP

7

4x 5

1

1 1223 3445 5667 788

R16

220

R16

220

D1

D1

R9

49.9

1%

R9

49.9

1%

C41

47uF

C41

47uF

FB1

STE

WA

RD

HI1

206T

500R

-00

FB1

STE

WA

RD

HI1

206T

500R

-00

12

C49

0.1u

F

C49

0.1u

FC

371n

FC

371n

F

R14

10K

R14

10K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AN

6

TPU

CH

1

TPU

CH

2

TPU

CH

3

TPU

CH

4

TCR

CLK

AN

7

TPU

CH

29

TPU

CH

13

TPU

CH

7

LTP

UO

DIS

TPU

CH

22

TPU

CH

30

TPU

CH

4

TPU

CH

16

TPU

CH

19

TPU

CH

10

TPU

CH

5

TPU

CH

12

TPU

CH

31

TPU

CH

7

TPU

CH

9

TPU

CH

5

TPU

CH

23

TPU

CH

20

TPU

CH

26

TPU

CH

8

TPU

CH

2

TPU

CH

11

TPU

CH

24

TPU

CH

12

TPU

CH

11

TPU

CH

10

TPU

CH

27

TPU

CH

8

TPU

CH

17

TPU

CH

6

TPU

CH

1

TPU

CH

3

TPU

CH

25

TPU

CH

9

TPU

CH

21

TPU

CH

28

TPU

CH

0

TPU

CH

15

TPU

CH

10

TPU

CH

13

TPU

CH

6

TPU

CH

18

TPU

CH

14

TPU

CH

[15:

0]

TPU

CH

8

TPU

CH

9

TPU

CH

11

TPU

CH

12

TPU

CH

13TP

UC

H4

TPU

CH

3TP

UC

H2

TPU

CH

1

AN

5

AN

0A

N1

TPU

CH

14

TPU

CH

[15:

0]

AN

4A

N3

AN

2

TPU

CH

15

TSIZ

1

/TE

A

TSIZ

0

/TIP

QS

PI_

DIN

QS

PI_

SC

K

QS

PI_

DO

UT

TCR

CLK

UTP

UO

DIS

TPU

CH

[31:

16]

LTP

UO

DIS

TPU

CH

[15:

0]

QS

PI_

PC

S0

VS

SA

+3.3

V

+5V

+3.3

V+5

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

VS

SA

VS

SA

+3.3

V+5

VA

+5V

A

VS

SA

+3.3

V

+3.3

V

+3.3

V

VS

SA

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+5V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+5V

+3.3

V

VS

SA

VS

SA

+3.3

V

+3.3

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

eTP

U c

onne

ctor

s an

d A

DC

C

M52

3xE

VB

C

916

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

eTP

U c

onne

ctor

s an

d A

DC

C

M52

3xE

VB

C

916

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

eTP

U c

onne

ctor

s an

d A

DC

C

M52

3xE

VB

C

916

Frid

ay, A

ugus

t 10,

200

7

Zero

_cro

ss_B

She

ildin

g

I_se

nse_

DC

B

PW

M_B

T

Zero

_cro

ss_A

PW

M_A

B

BE

MF_

sens

e_C

I_se

nse_

A

UN

I3 c

onne

ctio

n

BE

MF_

sens

e_B

I_se

nse_

BI_

sens

e_C

BE

MF_

sens

e_A

PW

M_C

B

PW

M_A

T

She

ildin

g

She

ildin

g

She

ildin

g

She

ildin

g

Zero

_cro

ss_C

PW

M_C

TS

heild

ing

She

ildin

g

V_s

ense

_DC

B_3

.3

PW

M_B

B

Ove

rcur

rent

com

para

tor

Hal

l sen

sors

/Enc

oder

con

nect

or

But

tons

& s

witc

h

Yel

low

led:

PW

M_A

B, P

WM

_BB

, PW

M_C

BG

reen

led:

PW

M_A

T, P

WM

_BT,

PW

M_C

T, L

ED

_STA

TUS

Red

led:

I_D

CB

_FA

ULT

Ple

ase

ensu

re th

ere

is th

icke

r gau

ge c

oppe

r be

twee

n V

out o

n U

13 a

nd R

EFI

N o

n U

12.

Ple

ase

ensu

re V

SS

A h

as a

pla

ne o

f cop

per u

nder

J4,

U11

& U

12.

Pla

ce C

87 a

ndC

88 a

s cl

ose

as p

ossi

ble

topi

ns 1

& 2

on

J6

Usi

ng G

PIO

(sec

onda

ryfu

nctio

n on

the

/TE

A p

in)

Usi

ng G

PIO

(sec

onda

ryfu

nctio

n on

the

TSIZ

0 pi

n)

Usi

ng G

PIO

(sec

onda

ryfu

nctio

n on

the

TSIZ

1 pi

n)

Usi

ng G

PIO

(sec

onda

ry fu

nctio

non

the

/TIP

pin

)

EX

OR

Log

ic G

ate

Inve

rterIn

verte

r

Pla

ce C

86 a

scl

ose

to U

17 a

spo

ssib

le

Pla

ce C

69 a

scl

ose

to U

16as

pos

sibl

e

AN

D G

ate

Logi

c

Pla

ce C

65as

clo

se to

U14

as

poss

ible

Pla

ce C

89as

clo

se to

U18

as

poss

ible

PW

M_A

T

PW

M_A

B

PW

M_B

T

PW

M_C

B

PW

M_C

T

PW

M_B

B

LED

_STA

TUS

I_D

CB

_FA

ULT

Plac

e th

ese

resi

stor

s at

an

acce

sibl

epo

int t

o al

low

rem

oval

if re

quire

d.

Pla

ce th

ese

zero

ohm

resi

stor

s as

clo

se to

the

junc

tion

with

the

eTP

U s

igna

ls a

s po

ssib

le a

nd a

t an

acce

ssib

lepo

int t

o al

low

rem

oval

if re

quire

d.

Pla

ce C

67 a

scl

ose

to U

15as

pos

sibl

e

Pla

ce th

e ca

paci

tors

& re

sist

ors

imm

edia

tely

bel

ow a

s cl

ose

aspo

ssib

le to

the

Vin

X p

ins

on U

12, a

s th

ey re

pres

ent a

n R

C fi

lter

for t

he A

DC

inpu

ts.

Ple

ase

plac

e H

S/E

NC

0 on

the

silk

scre

en c

lose

to J

6

Ple

ase

plac

e U

NI3

on

the

silk

scre

en c

lose

to J

4

AD

C H

eade

r

eTP

U H

eade

r

HS

/EN

CO

Hea

der

-UP

-DO

WN

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

QS

PI c

hip

sele

ctju

mpe

r, de

faul

t FIT

TED

defa

ult F

ITTE

D

R44

270

R44

270

C61

2.2n

F

C61

2.2n

F

C68

100n

FC

6810

0nF

C93

470p

FC

9347

0pF

R25

0R

250

U12 AD

7928

BR

U

U12 AD

7928

BR

U

SC

LK1

DIN

2C

S3

AG

ND

4A

VD

D5

AV

DD

6R

EFI

N7

AG

ND

8V

in7

9V

in6

10V

in5

11V

in4

12V

in3

13V

in2

14V

in1

15V

in0

16A

GN

D17

DO

UT

18V

driv

e19

AG

ND

20

C66

10nF

C66

10nF

R57

24R

5724

D12

D12

C65

100n

FC

6510

0nF

D11

D11

C85

0.1u

FC

850.

1uF

R34

120

R34

120

R46

270

R46

270

SW

2

KS

11R

22C

QD

SW

2

KS

11R

22C

QD

13

24

C77

1nF

C77

1nF

C55

0.1u

F

C55

0.1u

F

C71

1nF

C71

1nF

R36

120

R36

120

J5J5

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

U18 NL2

7WZ8

6

U18 NL2

7WZ8

6

A1

B1

Y2

GN

D

VC

C Y1

B2

A2

D10

D10

C62

2.2n

F

C62

2.2n

F

R52

1kR52

1k

C17

9

2.2n

F

C17

9

2.2n

F

R59

1kR59

1k

R51

1k8

R51

1k8

C57

0.1u

F

C57

0.1u

F

C69

100n

FC

6910

0nF

C80

0.1u

FC

800.

1uF

J4

Mol

ex/3

9-26

-740

5

J4

Mol

ex/3

9-26

-740

5

12345678910111213141516171819202122232425262728293031323334353637383940

R61

24R

6124

J3J3

1 2 3 4 5 6 7 8 9 10 11 12

C86

100n

FC

8610

0nF

C92

470p

FC

9247

0pF

U13

AD

780B

R

U13

AD

780B

R

NC

1+V

in2

TEM

P3

GN

D4

TRIM

5V

out

6N

C7

2.5/

3.0V

8

R48

270

R48

270

R60

4K7

R60

4K7

R41

10K

R41

10K

13

2

J6J6

1 2 3 4 5 6

R38

22K

R38

22K

U15

LM39

3M

U15

LM39

3M

Out

putA

1In

putA

2In

putA

3G

ND

4In

putB

5In

putB

6O

utpu

tB7

V+

8

C63

2.2n

F

C63

2.2n

F

C72

1nF

C72

1nF

C90

470p

FC

9047

0pF

R40

150

R40

150

C76

1nF

C76

1nF

R33

120

R33

120

R56

1kR56

1k

D6

D6

R35

120

R35

120

R22

0R

220

R39

100

R39

100

C56

10uF

C56

10uF

R24

0R

240

D9

D9

U16

NL2

7WZ0

4

U16

NL2

7WZ0

4

A1

GN

D

A2

Y1

VC

C Y2

C58

2.2n

F

C58

2.2n

F

C64

2.2n

F

C64

2.2n

F

C81

0.1u

FC

810.

1uF

D8

D8

C53

0.1u

F

C53

0.1u

F

R23

0R

230

R64

24R

6424

C91

470p

FC

9147

0pF

SW

1

RU

N/S

TOP

SW

1

RU

N/S

TOP

21 3

C73

1nF

C73

1nF

C83

0.1u

FC

830.

1uF

C79

0.1u

FC

790.

1uF

R43

270

R43

270

C75

1nF

C75

1nF

R63

1kR63

1k

C84

0.1u

FC

840.

1uF

C89

100n

FC

8910

0nF

JP30

JP30

12

C59

2.2n

F

C59

2.2n

F

R62

1K8

R62

1K8

JP29

JP29

12

R30

120

R30

120

R55

4k7

R55

4k7

R27

120

R27

120

R45

270

R45

270

U14

NL1

7SZ0

8

U14

NL1

7SZ0

8

B A GN

D

VC

C Y

R58

1K8

R58

1K8

R42

270

R42

270

R26

120

R26

120

D5

D5

R54

1K8

R54

1K8

R53

24R

5324

U17

SN

74H

C04

D

U17

SN

74H

C04

D

1A1

1Y2

2A3

2Y4

3A5

3Y6

GN

D7

4Y8

4A9

5Y10

5A11

6Y12

6A13

VC

C14

R37

1MR

371M

C88

100n

FC

8810

0nF

R65

1K8

R65

1K8

R19

0R

190

R49

4K7

R49

4K7

C67

100n

FC

6710

0nF

+C

872.

2uF

+C

872.

2uF

C60

2.2n

F

C60

2.2n

F

R31

120

R31

120

C74

1nF

C74

1nF

C70

1nF

C70

1nF

C54

10uF

C54

10uF

R21

0R

210

C78

0.1u

FC

780.

1uF

D7

D7

R32

0R

320

R50

270

R50

270

R47

270

R47

270

C82

0.1u

FC

820.

1uF

R20

0R

200

C52

0.1u

F

C52

0.1u

F

SW

3

KS

11R

22C

QD

SW

3

KS

11R

22C

QD

13

24



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TPU

CH

7TP

UC

H8

TPU

CH

12TP

UC

H11

D28

D24

D25

D19

D16

TPU

CH

26TP

UC

H29

TPU

CH

28TP

UC

H31

TPU

CH

30

CLK

MO

D1

D31

D26

D27

D13

A9

A7

A20

A19

A3

DD

ATA

3

A0

A5

A16

A22

A17

A14

A4

A8

/CS2

/CS6

TPUCH20TPUCH21

TPUCH1

TPUCH2

TPUCH24

TPUCH5

TPUCH6

TPUCH16

/BS1

TPUCH23

D7D11

PST1 PST2

/IRQ2

D3

DDATA1

D1

/IRQ1

/IRQ6

DDATA2

D8

DDATA0

D4

D0

D5

TPU

CH

[15:

0]

TPU

CH

[15:

0]TP

UC

H[1

5:0]

TPU

CH

10TP

UC

H9

TPU

CH

[31:

16]

TPU

CH

[31:

16]

TPU

CH

25TP

UC

H27

TPU

CH

14TP

UC

H13

TPU

CH

15

CLK

MO

D0

D[3

1:0]

D[3

1:0]

D[3

1:0]

D29

D30

D23

D21

D22

D20

D17

D18

D9

D12

D15

D[3

1:0]

D14 D10D6

D2

/IRQ

[7:1

]

/IRQ

[7:1

]

/IRQ7

/IRQ3 /IRQ4/IRQ5

/IRQ

[7:1

]

PS

T[3:

0]

PS

T[3:

0]

PS

T[3:

0]

PST0

PST3

DD

ATA

[3:0

]D

DA

TA[3

:0]

DD

ATA

[3:0

]

A[2

3:0]

A[2

3:0]

A[2

3:0]

A2

A1

A12

A6

A10

A11

A13

A15

A18

A21

/CS

[7:0

]

/CS4

/CS

[7:0

]

/CS1

/CS3

A23/CS0/CS5/CS7

/CS

[7:0

]

/BS

[3:0

]

/BS0

/BS2/BS3

TPUCH0TPUCH19

TPUCH22TPUCH18TPUCH17

TPUCH3

TPUCH4

TPU

CH

[15:

0]

TPU

CH

[31:

16]

TCR

CLK

/U0C

TSU

0RX

DD

TOU

T0D

TIN

0U

0TX

D/U

0RTS

CLK

MO

D[1

:0]

D[3

1:0]

/OEDTOUT1

DTIN1

/IRQ

[7:1

]

TSIZ0

TCLK/PSTCLKDTOUT2 DTIN2

TDI/DSITDO/DSO TMS/BKPT

TRST/DSCLKP

ST[

3:0]

DD

ATA

[3:0

]

JTAG_EN /RCON/RSTOUT

/RESET

EX

TAL

XTA

L/S

D_C

S1

CLK

OU

T/S

D_C

AS

/SD

_CS

0/S

D_R

AS

R/W

CA

N0T

XC

AN

0RX

/SD

_WE

/TS

/TIP

/TA

/TE

AD

TOU

T3D

TIN

3LT

PU

OD

ISU

TPU

OD

IS

A[2

3:0]

/CS

[7:0

]

TSIZ1

U1TXDU1RXD/U1RTS

U2TXD

/U1CTSU2RXD

CAN1RXSD_SCKE

QSPI_PCS1/U2RTS

/BS

[3:0

]

QSPI_PCS0QSPI_DOUT

QSPI_DINI2C_SDA

QSPI_SCKI2C_SCL

EMDCEMDIO

/EX

T_R

STI

N

CAN1TX

/U2CTS

+3.3

V+1

.5V

+3.3

V+5

V+3

.3V

+1.5

V+3

.3V

+5V

+3.3

V

+1.5

V

+3.3

V

+5V

+3.3

V

+5V

+1.5

V

+3.3

V

+5V

+3.3

V

+1.5

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Exp

ansi

on C

onne

ctor

sC

M52

3xE

VB

C

1016

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Exp

ansi

on C

onne

ctor

sC

M52

3xE

VB

C

1016

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Exp

ansi

on C

onne

ctor

sC

M52

3xE

VB

C

1016

Frid

ay, A

ugus

t 10,

200

7

NO

TE: i

f des

igni

ng a

dau

ghte

r car

d to

fit t

hese

exp

ansi

on c

onne

ctor

spl

ease

ens

ure

all s

igna

ls a

re b

uffe

red

on th

e da

ught

er c

ard. M

otor

ola

SP

S T

SP

G -

TEC

D C

oldF

ire G

roup

C99

1nF

C99

1nF

C10

210

nFC

102

10nF

C96

470p

FC

9647

0pF

C10

510

nFC

105

10nF

C10

947

0pF

C10

947

0pF

C10

00.

1uF

C10

00.

1uF

C10

310

nFC

103

10nF

J10 AM

P 1

7798

3-2

J10 AM

P 1

7798

3-2

2468

1012141618202224262830323436384042444648505254565860

1357911131517192123252729313335373941434547495153555759

C10

410

nFC

104

10nF

C10

847

0pF

C10

847

0pF

J7 AM

P 1

7798

3-2

J7 AM

P 1

7798

3-2

2468

1012141618202224262830323436384042444648505254565860

1357911131517192123252729313335373941434547495153555759

C94

10nF

C94

10nF

C10

747

0pF

C10

747

0pF

C97

470p

FC

9747

0pF

J9 AM

P 1

7798

3-2

J9 AM

P 1

7798

3-2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

J8 AM

P 1

7798

3-2

J8 AM

P 1

7798

3-2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

C98

1nF

C98

1nF

C95

10nF

C95

10nF

C10

10.

1uF

C10

10.

1uF

C10

647

0pF

C10

647

0pF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

B_D

[31:

0]

B_A

14B

_A2

B_A

21

B_A

8

B_A

19

B_A

9

B_A

20

B_A

17

B_A

6

B_A

4

B_A

7

B_A

5B

_A11

B_A

10

B_A

18

B_A

16

B_A

12

B_A

15

B_A

3

B_A

13

B_A

[23:

0]B

_A[2

3:0]

B_A

[23:

0]

B_D

31B

_D23

B_D

22B

_D29

B_D

21B

_D28

B_D

16B

_D24

B_D

17B

_D25

B_D

18B

_D26

B_D

19B

_D27

B_D

20

B_D3

B_D4

B_D16

B_D26

B_D27

B_D

[31:

0]

B_D10

B_D18

B_D20

B_D11

B_D13

B_D14

B_D24

B_D25

B_D12

B_D

[31:

0]

B_D2

B_D5

B_D15 B_D0

B_D6

B_D22

B_D28

B_D31

B_D21

B_D1

B_D19

B_D7B_D8

B_D9

B_D30

B_D23

B_D29

B_D17

B_D

[31:

0]

B_D

[31:

0]

B_A

1B

_A2

B_A

3B

_A4

B_A

5B

_A6

B_A

7B

_A8

B_A

18B

_A19

/CS

0

B_A

[23:

0]

B_D

30

B_A

9B

_A10

B_A

11B

_A12

B_A

13B

_A14

B_A

15B

_A16

B_A

17

B_A

20

/OE

R/W

B_A

[23:

0]

B_D

[31:

0]/C

S[7

:0]

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Fla

sh M

emor

y (F

ujits

u S

SO

P O

R A

MD

BG

A)

C

M52

3xE

VB

C

1116

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Fla

sh M

emor

y (F

ujits

u S

SO

P O

R A

MD

BG

A)

C

M52

3xE

VB

C

1116

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Fla

sh M

emor

y (F

ujits

u S

SO

P O

R A

MD

BG

A)

C

M52

3xE

VB

C

1116

Frid

ay, A

ugus

t 10,

200

7

NO

TE: T

he w

rite

prot

ect p

in (C

5)sh

ould

not

be

left

float

ing

asin

cons

ista

nt b

ehav

iour

of t

heFl

ash

devi

ce c

ould

resu

lt.To

use

har

dwar

e pr

otec

t on

the

top/

botto

m b

oot s

ecto

r set

JP

32be

twee

n pi

ns 2

& 3

. To

disa

ble

hard

war

e pr

otec

t set

bet

wee

npi

ns 1

& 2

(def

ault)

.

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

32M

Bit

Flas

hB

oot

Def

ault

setti

ng -

JP31

fitte

dac

ross

pin

s 1

& 2

Onl

y on

e or

the

othe

r foo

tprin

tsw

ill b

e po

pula

ted

- BG

A (U

35)

OR

SS

OP

(U19

)

16 M

Bit

Flas

h B

oot

Def

ault

setti

ng -

JP64

fitte

d ac

ross

pin

s 1

& 2

Mem

ory

Siz

e: 1

M x

16-

bit =

2M

BM

emor

y S

ize:

1M

x 3

2-bi

t = 4

MB

C11

90.

1uF

C11

90.

1uF

C11

70.

1uF

C11

70.

1uF

C11

11n

FC

111

1nF

C11

81n

FC

118

1nF

R68

4.7K

R68

4.7K

R66

4.7K

R66

4.7K

U35

Am

29P

L320

D

U35

Am

29P

L320

D

CE

A8

VS

SB

8N

CA

7W

OR

DB

7O

EC

7W

EA

6N

CB

6N

CC

6N

CA

5A

CC

B5

WP

C5

NC

D5

NC

E5

A1

A4

A2

B4

A3

C4

A0

D4

A4

A3

A5

B3

VC

CB

2

DQ30B9VCCC9

DQ15C8DQ13D9DQ29D8DQ14D7

DQ31/A-1D6DQ12E9DQ28E8

VSSE7NCE6

DQ27F9DQ11F8DQ10F7

NCF6DQ26G9

VSSG8DQ25G7DQ8G6VCCH9

DQ24H8DQ9J9

A19

K8

VC

CJ8

A16

K7

A17

J7A

18H

7A

13K

6A

14J6

A15

H6

NC

K5

NC

J5N

CH

5N

CG

5N

CF5

A10

K4

A9

J4A

11H

4A

12G

4A

7K

3A

6J3

A8

H3

VS

SK

2

DQ17 C1DQ1 C2

VCC D1VSS D2DQ16 D3

DQ0 C3

DQ3 E1DQ19 E2DQ18 E3DQ2 E4DQ20 F1DQ4 F2DQ5 F3NC F4VSS G1DQ6 G2DQ21 G3VCC H1

DQ22 J1DQ23 J2

DQ7 H2

JP31

JP31

1

2

3

C11

21n

FC

112

1nF

C11

60.

1uF

C11

60.

1uF

C12

00.

1uF

C12

00.

1uF

JP32

JP32

1

2

3

C11

31n

FC

113

1nF

JP64

JP64

1

2

3

C11

50.

1uF

C11

50.

1uF

R67

4.7KR67

4.7K

R69

4.7K

R69

4.7K

U19

AM

D A

m29

PL1

60C

B-6

5RS

U19

AM

D A

m29

PL1

60C

B-6

5RS

WE

#1

A18

2A

173

A7

4A

65

A5

6A

47

A3

8A

29

A1

10A

011

CE

#12

Vss

13O

E#

14D

Q0

15D

Q8

16D

Q1

17D

Q9

18D

Q2

19D

Q10

20D

Q3

21D

Q11

22V

cc23

DQ

424

DQ

1225

DQ

526

DQ

1327

DQ

628

DQ

1429

DQ

730

DQ

15/A

-131

Vss

32B

YTE

#33

A16

34A

1535

A14

36A

1337

A12

38A

1139

A10

40A

941

A8

42A

1943

NC

44

C11

40.

1uF

C11

40.

1uF

C11

01n

FC

110

1nF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+3.3

VP

+5V+3

.3V

+3.3

V

+3.3

V+1

.5V

+1.5

V+1

.5V

P

+5V

+1.5

V

VS

SP

LL

VS

SA+5

V+5

VA

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Pow

er S

uppl

yC

M52

3xE

VB

B

1216

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Pow

er S

uppl

yC

M52

3xE

VB

B

1216

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Pow

er S

uppl

yC

M52

3xE

VB

B

1216

Frid

ay, A

ugus

t 10,

200

7

Aug

at 2

5V-0

2

+

NO

TE: t

he p

ositi

ve te

rmin

al o

f eac

hpo

wer

con

nect

or m

ust b

e sh

own

on th

esi

lksc

reen

of t

he P

CB

-

2-w

ay B

are

Wire

Pow

er C

onne

ctor

JP33

SH

OU

LD B

EIN

STA

LLE

D D

UR

ING

AS

SE

MB

LY

DC

vol

tage

inpu

t ran

ge +

7 to

+14

V

5.0V

Reg

ulat

or

-

3.3V

Reg

ulat

or

+

Pow

er J

ack

Con

nect

or -

2.1m

m d

iam

eter

NO

TE: D

iode

s pr

even

t exc

essi

vedi

ffere

nce

betw

een

3.3V

& 1

.5V

rails

, at p

ower

up

NO

TE: S

chot

tky

Dio

de p

reve

nts

exce

ssiv

edi

ffere

nce

betw

een

3.3V

& 1

.5V

rails

, at p

ower

dow

n

JP34

SH

OU

LD B

EIN

STA

LLE

D D

UR

ING

AS

SE

MB

LY

1.5V

Reg

ulat

or

VS

SA

- an

alog

gro

und

for e

TPU

cha

nnel

s

VS

SP

LL -

filte

red

grou

nd fo

r CP

U P

LL m

odul

e

Filte

red

grou

nd fo

r pla

ne fo

r eth

erne

t RJ4

5 co

nnec

tor

+5V

A -

filte

red

pow

er fo

r eTP

U A

DC

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

D15

MB

RS

340T

3

D15

MB

RS

340T

3

21

L3

25uH

L3

25uH

U20

LM25

96S

-3.3

U20

LM25

96S

-3.3

VIN

1V

OU

T2

~ON

/OFF

5

GND 3

FB4

TAB 6

C12

3

0.1u

F

C12

3

0.1u

F

D18

MR

A40

03T3

D18

MR

A40

03T3

FB3

FB3

12

FB4

FB4

12

L2 25uH

L2 25uH

C13

0

0.1u

F

C13

0

0.1u

F

D17

+5V

GR

EE

N P

OW

ER

LE

D

D17

+5V

GR

EE

N P

OW

ER

LE

D

C12

133

0uF

C12

133

0uF

SW

4

PO

WE

R S

W S

LID

E-S

PS

T(B

oard

Edg

e)

SW

4

PO

WE

R S

W S

LID

E-S

PS

T(B

oard

Edg

e)

54 6

21 3

F1

5A F

ast b

low

.

F1

5A F

ast b

low

.

C12

510

00uF

C12

510

00uF

C12

20.

1uF

C12

20.

1uF

C12

633

0uF

C12

633

0uF

D16

MB

RS

340T

3D

16M

BR

S34

0T3

21

D14 +3

.3V

GR

EE

N P

OW

ER

LE

D

D14 +3

.3V

GR

EE

N P

OW

ER

LE

D

U22

LT10

86C

MU

22LT

1086

CM

VIN

3

ADJ 1

VO

UT

2

R71 56

0

R71 56

0

FB6

FB6

12

FB5

FB5

12

U21

LM25

96S

-5U

21LM

2596

S-5

VIN

1V

OU

T2

~ON

/OFF

5

GND 3

FB4

TAB 6

D22

MB

RS

340T

3

D22

MB

RS

340T

3

21

C12

4

1nF

C12

4

1nF

P2

Sw

itchc

raft

RA

PC

712

P2

Sw

itchc

raft

RA

PC

712123

JP33

JP33

12

JP34

JP34

12

R70

270

R70

270

R73

120

R73

120

C12

810

uF T

AN

T.C

128

10uF

TA

NT.

P3

P3

1 2

D20

MB

RS

340T

3

D20

MB

RS

340T

3

21

C12

70.

1uF

C12

70.

1uF

D19 M

RA

4003

T3

D19 M

RA

4003

T3

D13

MB

RS

340T

3D

13M

BR

S34

0T3

21

C12

933

0uF

C12

933

0uF

R74

22R

7422



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

/IRQ

7/IR

Q[7

:1]

D16

D20

D[3

1:0]

D19

D25

D24

D21

CLK

MO

D[1

:0]

CLK

MO

D1

CLK

MO

D0

/IRQ

2

/CS

6/C

S5

/IRQ

7/C

S7

/IRQ

6

/IRQ

[7:1

]

/CS

4/IR

Q5

/CS

3/IR

Q3

/IRQ

1

/CS

2

/IRQ

4

/CS

0

/CS

[7:0

]

/CS

0/C

S1

/BS

[3:0

]

/BS

0/B

S1

/BS

2/B

S3

/RE

SE

T/B

DM

_RS

TIN

/EX

T_R

STI

N

ETH

_CLK

XTA

L

/IRQ

[7:1

]

JTA

G_E

N

/RS

TOU

T

D[3

1:0]

/RC

ON

CLK

MO

D[1

:0]

/RS

TOU

T

/CS

[7:0

]

R/W

/BS

[3:0

]

TDI/D

SI

/OE

TDO

/DS

O

/IRQ

[7:1

]

/TA

TRS

T/D

SC

LK

TSIZ

0

TMS

/BK

PT

TSIZ

1

CLK

OU

T

/TS

/TA

/CS

[7:0

]

R/W

/OE

/TE

A

/TIP

/TS

EX

TAL

UTP

UO

DIS

LTP

UO

DIS

DTO

UT2

DTO

UT3

DTO

UT1

DTO

UT0

DTI

N2

DTI

N1

DTI

N0

DTI

N3

ETP

U/E

TH

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V+3

.3V

VS

SP

LL

VS

SP

LL

VS

SP

LL

+3.3

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Res

et C

onfig

urat

ion

& C

lock

sel

ectio

nC

M52

3xE

VB

C

1316

Tues

day,

Aug

ust 1

4, 2

007

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Res

et C

onfig

urat

ion

& C

lock

sel

ectio

nC

M52

3xE

VB

C

1316

Tues

day,

Aug

ust 1

4, 2

007

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Res

et C

onfig

urat

ion

& C

lock

sel

ectio

nC

M52

3xE

VB

C

1316

Tues

day,

Aug

ust 1

4, 2

007

AB

OR

T/-IN

T7

DE

BO

UN

CE

D /I

RQ

7S

IGN

AL

HA

RD

RE

SE

T &

VO

LTA

GE

SE

NS

E C

ON

TRO

LLE

R

Buf

fere

d an

d "O

R'd

" /R

STI

sig

nal t

o th

e C

PU

from

the

BD

M p

ort,

expa

nsio

n co

nnec

tors

or r

eset

sw

itch.

NO

TE: s

igna

l tra

ck le

ngth

s be

twee

n th

ese

cloc

kci

rcui

ts a

nd th

e M

CF5

23x

shou

ld b

e m

inim

ised

.

OS

CIL

LATO

R -

dual

layo

ut fo

otpr

int

for 8

AN

D 1

4 pi

n so

cket

ed D

IL o

sc.'s

D24

D21

D20

D19

D16

CLK

MO

D0

CLK

MO

D1

JTA

G_E

NR

CO

N

IMP

OR

TAN

T N

OTE

: TH

E /R

STO

UT

SIG

NA

L M

US

T B

E U

SE

D T

O D

RIV

E T

HE

OU

TPU

T E

NA

BLE

PIN

S O

F U

7 T

O A

LLO

W T

HE

D16

, D17

, D18

, D19

, D21

, D24

, D25

& D

26 S

IGN

ALS

TO

BE

LA

TCH

ED

CO

RR

EC

TLY

BY

THE

MC

F523

x FO

R C

ON

FIG

UR

ATI

ON

AT

RE

SE

T.

Clo

sed/

On

Ope

n/O

ff

D25

Enc

oded

Add

ress

/Chi

p S

elec

t Mod

eS

W7-

9

S

W7-

10

Mod

e--

----

----

-

----

----

---

----

----

----

----

----

----

-- O

FF

OFF

PF[

7:5]

= /C

S[6

:4]

OFF

O

N

P

F7 =

/CS

6, P

F[6:

5] =

A[2

2:21

] O

N

OFF

PF[

7:6]

= /C

S[6

:5],

PF[

5] =

A21

ON

O

N

P

F[7:

5] =

A[2

3:21

]

NO

TE: P

leas

e pl

ace

thes

e ta

bles

on

the

silk

scre

en o

n th

e to

psid

e of

the

PC

B c

lose

to S

W7.

Enc

oded

Boo

t Dev

ice

(Por

t Siz

e)S

W7-

6

S

W7-

7

Mod

e--

----

----

-

----

----

---

----

----

----

----

----

----

-- O

FF

OFF

Ext

erna

l (32

-bit)

OFF

O

N

E

xter

nal (

8-bi

t) O

N

OFF

Ext

erna

l (16

-bit)

ON

ON

Ext

erna

l (32

-bit)

Enc

oded

Ope

ratin

g M

ode

SW

7-5

Mod

e--

----

----

-

----

----

---

OFF

R

eser

ved

ON

M

aste

r

Enc

oded

Clo

ck M

ode

SW

7-3

S

W7-

4

Mod

e--

----

----

- -

----

----

--

---

----

----

----

----

----

----

----

----

----

----

----

---

OFF

O

FF

Ext

erna

l Clo

ck -

(No

PLL

) O

FF

ON

1

:1 P

LL O

N

OFF

N

orm

al P

LL o

pera

tion

(Ext

. Clo

ck)

ON

O

N

Nor

mal

PLL

ope

ratio

n (E

xt. C

ryst

al)

----

----

----

----

----

----

O

FF -

SW

7 - O

N

----

----

----

----

----

----

Chi

p C

onfig

. Off

1

Chi

p C

onfig

. On

JTA

G In

terfa

ce E

nabl

ed

2

BD

M In

terfa

ce E

nabl

edE

ncod

ed C

lock

Mod

e

3

E

ncod

ed C

lock

Mod

eE

ncod

ed C

lock

Mod

e

4

E

ncod

ed C

lock

Mod

eE

ncod

ed O

per.

Mod

e

5

E

ncod

ed O

per.

Mod

eE

ncod

ed B

oot D

evic

e

6

E

ncod

ed B

oot D

evic

eE

ncod

ed B

oot D

evic

e

7

E

ncod

ed B

oot D

evic

eP

artia

l Bus

Driv

e

8

Fu

ll B

us D

rive

Enc

oded

Add

ress

Mod

e

9

Enc

oded

Add

ress

Mod

eE

ncod

ed A

ddre

ss M

ode

1

0

Enc

oded

Add

ress

Mod

eeT

PU

Ena

bled

11

Eth

erne

t Ena

bled

Not

e: d

efau

lt se

tting

for S

W7

is a

ll sw

itche

s cl

osed

/on.

Impo

rtant

Not

e - a

ll un

conn

ecte

d pu

ll-up

and

pul

l-dow

nre

sist

or p

ack

conn

ectio

ns, o

n al

l sch

emat

ics

page

s, n

eed

to b

e co

nnec

ted

to a

n un

mas

ked

via.

NO

TE: P

lace

TP

9, T

P10

, TP

11 &

TP

12 a

t the

cor

ners

of t

he P

CB

to a

llow

eas

y co

nnec

tion

of 's

cope

pro

be g

roun

d le

ads.

NO

TE: P

leas

e pl

ace

D25

thro

ugh

D32

toge

ther

in a

line

.

DTI

N0

LED

DTI

N1

LED

DTI

N2

LED

DTI

N3

LED

DTO

UT0

LE

D

DTO

UT1

LE

D

DTO

UT2

LE

D

DTO

UT3

LE

D

Cry

stal

Ena

ble

Def

ault

setti

ng fo

r JP3

8 th

roug

h JP

45 is

fitte

d.

Ext

erna

l Clo

ck In

put (

SM

A c

onne

ctor

)

Pla

ce T

P6

ascl

ose

to E

XTA

Las

pos

sibl

e

Eth

erne

t/eTP

U M

ode

(eTP

U c

hann

els

16 to

31)

SW

7-11

Mod

e--

----

----

-

----

----

---

OFF

eT

PU

ena

bled

ON

E

ther

net e

nabl

ed

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

TP5

CH

IP S

ELE

CT

0

TP5

CH

IP S

ELE

CT

01

SW

6

KS

11R

23C

QD

RE

SE

T

SW

6

KS

11R

23C

QD

RE

SE

T

RP

15

4x 4

.7K

RP

15

4x 4

.7K

11

22

33

44

55

66

77

88

RP

17

4x 4

.7K

RP

17

4x 4

.7K

11

22

33

44

55

66

77

88

RP

18

4x 1

0

RP

18

4x 1

0

1 1223 3445 5667 788

TP9

GR

OU

ND

TP9

GR

OU

ND

1

SW

7

Con

figur

atio

n D

IP s

witc

h - G

rayh

ill 7

8RB

12

SW

7

Con

figur

atio

n D

IP s

witc

h - G

rayh

ill 7

8RB

12

JP38

JP38

12

R77

100

R77

100

C13

110

pFC

131

10pF

D30

D30

R80

1KR80

1K

TP4

RE

AD

NO

T W

RIT

E

TP4

RE

AD

NO

T W

RIT

E1

JP37

JP37

12

RP

13

4x 1

0K

RP

13

4x 1

0K

1 1223 3445 5667 788

SW

5

KS

11R

22C

QD

SW

5

KS

11R

22C

QD

U25

AD

M70

8SA

R

U25

AD

M70

8SA

R

MR

1V

CC

2G

ND

3P

FI4

PFO

5N

.C.

6R

ES

ET

7R

ES

ET

8

TP7

TRA

NS

FER

AC

KN

OW

LED

GE

TP7

TRA

NS

FER

AC

KN

OW

LED

GE

1

RP

10

4x 4

.7K

RP

10

4x 4

.7K

11

22

33

44

55

66

77

88

D28

D28

U26 SN

74LV

C1G

11

U26 SN

74LV

C1G

11

A GN

DB

CV

CC Y

R76

10K

R76

10K

JP42

JP42

12

TP3

OU

TPU

T E

NA

BLE

TP3

OU

TPU

T E

NA

BLE

1

D31

D31

D24

RE

D R

ES

ET

LE

DD

24R

ED

RE

SE

T L

ED

JP35

JP35

1

2

3

U24

AD

M70

8SA

R

U24

AD

M70

8SA

R

MR

1V

CC

2G

ND

3P

FI4

PFO

5N

.C.

6R

ES

ET

7R

ES

ET

8

RP

14

4x 4

.7K

RP

14

4x 4

.7K

11

22

33

44

55

66

77

88

D23

RE

D -I

NT7

LE

DD

23R

ED

-IN

T7 L

ED

JP39

JP39

12

TP6

CP

U C

LOC

K I/

P

TP6

CP

U C

LOC

K I/

P1

J11

J11

1

2345

RP

21

4x 4

.7K

RP

21

4x 4

.7K

11

22

33

44

55

66

77

88

R79

100

R79

100

D26

D26

RP

11

4x 4

.7K

RP

11

4x 4

.7K

11

22

33

44

55

66

77

88

R78

270

R78

270

D29

D29

JP41

JP41

12

RP

20

4x 4

.7K

RP

20

4x 4

.7K

11

22

33

44

55

66

77

88

RP

12

4x 4

.7K

RP

12

4x 4

.7K

11

22

33

44

55

66

77

88

R75

270

R75

270

RP

19

4x 1

0

RP

19

4x 1

0

1 1223 3445 5667 788

Y1 25

MH

z

Y1 25

MH

z

JP43

JP43

12

TP8

CP

U C

LOC

K O

/P

TP8

CP

U C

LOC

K O

/P1

RP

16

4x 4

.7K

RP

16

4x 4

.7K

11

22

33

44

55

66

77

88

D25

D25

TP12

GR

OU

ND

TP12

GR

OU

ND

1

RP

22

4x 4

.7K

RP

22

4x 4

.7K

11

22

33

44

55

66

77

88

D27

D27

JP44

JP44

12

JP45

JP45

12

RP

8

4x 4

.7K

RP

8

4x 4

.7K

11

22

33

44

55

66

77

88

TP11

GR

OU

ND

TP11

GR

OU

ND

1

U23

25M

Hz

U23

25M

Hz

OE

1

GN

D7

CLK

8

VD

D14

OE

4V

DD

11

JP40

JP40

12

C13

210

pFC

132

10pF

R72

22R72

22

U27

MC

74LC

X54

1DT

U27

MC

74LC

X54

1DT

OE

11

D0

2D

13

D2

4D

35

D4

6D

57

D6

8D

79

GN

D10

O7

11O

612

O5

13O

414

O3

15O

216

O1

17O

018

OE

219

VC

C20

TP10

GR

OU

ND

TP10

GR

OU

ND

1

D32

D32

RP

9

4x 4

.7K

RP

9

4x 4

.7K

11

22

33

44

55

66

77

88

TP2

TRA

NS

FER

STA

RT

TP2

TRA

NS

FER

STA

RT

1

JP36

JP36

1

2

3



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

A13

D5 A

23

D27

D2

D13

D20

D[3

1:0]

A20

D4

A11

/BS

[3:0

]

A17

D23

A[2

3:0]

D24

D3 A

12A

11

A12

D6

D25

A21

A17

A9

/BS

3 /BS

1

D17

D28

D9

D11

D8

D19

A13

D21

D26

/BS

2

A14

D16

A22

/BS

0

D7

A10

D0A

20

D15

A19

D10

D31

A19

D14

A22

A10

D30

D12

A[2

3:0]

A15

A23

D29

D18 D

1

A18

D[3

1:0]

A9

A21

A14

A15

A18

D22

/BS

[3:0

]

/SD

_CS

0

/SD

_WE

SD

_SC

KE

D[3

1:0]

/SD

_RA

SC

LKO

UT

/SD

_CA

S

A[2

3:0]

A[2

3:0]

+3.3

V

+3.3

V

+3.3

V+3

.3V

+3.3

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

SD

RA

MC

M52

3xE

VB

B

1416

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

SD

RA

MC

M52

3xE

VB

B

1416

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

SD

RA

MC

M52

3xE

VB

B

1416

Frid

ay, A

ugus

t 10,

200

7

SDR

AM U

pper

16-

bit W

ord.

SD

RA

M L

ower

16-

bit W

ord.

NO

TE: M

emor

y si

ze: E

ach

SD

RA

Mm

emor

y is

con

figur

ed 4

M x

16b

it(8

MB

). To

tal a

vaila

ble

SD

RA

M is

16M

B.

NO

TE: A

ltern

ativ

e S

DR

AM

's w

ith th

e sa

me

PC

B fo

otpr

int a

re:

Sam

sung

K4S

6416

32E

Hyu

ndai

HY

57V

6416

20H

GTo

shib

a TC

59S

6416

CFT

Infin

eon

HY

B39

S64

160E

TW

inbo

nd W

9864

16D

H

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

C14

00.

1uF

C14

00.

1uF

C13

41n

FC

134

1nF

U29

MT4

8LC

4M16

A2T

G (T

SO

P II

400

mil)

U29

MT4

8LC

4M16

A2T

G (T

SO

P II

400

mil)

VD

D1

DQ

02

VD

DQ

3D

Q1

4D

Q2

5V

SS

Q6

DQ

37

DQ

48

VD

DQ

9D

Q5

10D

Q6

11V

SS

Q12

DQ

713

VD

D14

DQ

ML

15W

E#

16C

AS

#17

RA

S#

18C

S#

19B

A0

20B

A1

21A

1022

A0

23A

124

A2

25A

326

VD

D27

VS

S28

A4

29A

530

A6

31A

732

A8

33A

934

A11

35N

C36

CK

E37

CLK

38D

QM

H39

NC

40V

SS

41D

Q8

42V

DD

Q43

DQ

944

DQ

1045

VS

SQ

46D

Q11

47D

Q12

48V

DD

Q49

DQ

1350

DQ

1451

VS

SQ

52D

Q15

53V

SS

54

U28

MT4

8LC

4M16

A2T

G (T

SO

P II

400

mil)

U28

MT4

8LC

4M16

A2T

G (T

SO

P II

400

mil)

VD

D1

DQ

02

VD

DQ

3D

Q1

4D

Q2

5V

SS

Q6

DQ

37

DQ

48

VD

DQ

9D

Q5

10D

Q6

11V

SS

Q12

DQ

713

VD

D14

DQ

ML

15W

E#

16C

AS

#17

RA

S#

18C

S#

19B

A0

20B

A1

21A

1022

A0

23A

124

A2

25A

326

VD

D27

VS

S28

A4

29A

530

A6

31A

732

A8

33A

934

A11

35N

C36

CK

E37

CLK

38D

QM

H39

NC

40V

SS

41D

Q8

42V

DD

Q43

DQ

944

DQ

1045

VS

SQ

46D

Q11

47D

Q12

48V

DD

Q49

DQ

1350

DQ

1451

VS

SQ

52D

Q15

53V

SS

54C

135

1nF

C13

51n

FC

139

0.1u

FC

139

0.1u

FC

136

1nF

C13

61n

FC

138

0.1u

FC

138

0.1u

FC

137

0.1u

FC

137

0.1u

FC

133

1nF

C13

31n

F



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

/IRQ

[7:1

]/IR

Q1

QS

PI_

PC

S1

QS

PI_

PC

S0

U0R

XD

/U1R

TS

/U0C

TS

/U1C

TS

/U0R

TS

U2R

XD

U1R

XD

QS

PI_

DIN

QS

PI_

DO

UT

QS

PI_

SC

K

QS

PI_

PC

S0

I2C

_SC

L

I2C

_SD

A

CA

NH

1C

AN

L1

QS

PI_

PC

S1

U0T

XD

U1T

XD

U2T

XD

/U2C

TS

/U2R

TS

/IRQ

[7:1

]

/RS

TOU

T

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+5V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V+3

.3V

+3.3

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Ser

ial I

/OC

M52

3xE

VB

C

1516

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Ser

ial I

/OC

M52

3xE

VB

C

1516

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

Ser

ial I

/OC

M52

3xE

VB

C

1516

Frid

ay, A

ugus

t 10,

200

7

TER

MIN

AL

PO

RT

9-W

AY

D-T

YP

E(F

emal

e)

RS2

32 T

rans

ceiv

er.

Def

ault

setti

ng fo

r JP

46 to

JP

49 is

fitte

d.

RS2

32 T

rans

ceiv

er.

AU

XIL

IAR

Y P

OR

T 1

9-W

AY

D-T

YP

E(F

emal

e)

RS2

32 T

rans

ceiv

er.

AU

XIL

IAR

Y P

OR

T 2

9-W

AY

D-T

YP

E(F

emal

e)

NO

TE: t

he I2

C b

us o

n th

e M

CF5

23x

proc

esso

r is

3.3V

tole

rant

onl

y. If

con

nect

ion

to a

5V

sys

tem

is re

quire

d hi

gh fr

eque

ncy

volta

ge le

vel s

hifte

rs w

ill b

e re

quire

d be

twee

nth

e pe

riphe

ral a

nd p

roce

ssor

.

Def

ault

setti

ng fo

r JP

53 &

JP

54 is

NO

T fit

ted.

Def

ault

setti

ng fo

r JP

50 to

JP

52 is

fitte

d be

twee

n pi

ns 1

& 2

.

NO

TE: L

abel

as

"UA

RT0

"an

d "T

erm

inal

"

NO

TE: L

abel

as

"UA

RT1

"an

d "A

uxili

ary"

NO

TE: L

abel

as

"UA

RT2

"an

d "C

AN

1"

I2C

0.1

" pitc

h th

ru' b

oard

con

nect

or

QS

PI 0

.1" p

itch

thru

' boa

rd c

onne

ctor

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

U32

MA

X32

25C

AP

or I

CL3

225C

A

U32

MA

X32

25C

AP

or I

CL3

225C

A

RE

AD

Y1

C1+

2V

+3

C1-

4C

2+5

C2-

6V

-7

T2O

UT

8R

2IN

9R

2OU

T10

INV

ALI

D11

T2IN

12T1

IN13

FOR

CE

ON

14

GN

D18

R1O

UT

15R

1IN

16T1

OU

T17

VC

C19

FOR

CE

OFF

20

C14

60.

1uF

C14

60.

1uF

JP48

JP48

12

C15

51n

FC

155

1nF

JP49

JP49

12

JP53

JP53

12

C14

40.

1uF

C14

40.

1uF

J13

J13 1 2 3 4

C14

10.

1uF

C14

10.

1uF

JP54

JP54

12

JP51

JP51

12

3

C14

20.

1uF

C14

20.

1uF

P4

P4

5 9 4 8 3 7 2 6 1

C14

70.

1uF

C14

70.

1uF

C15

00.

1uF

C15

00.

1uF

C15

20.

1uF

C15

20.

1uF

C15

40.

1uF

C15

40.

1uF

U30

MA

X32

25C

AP

or I

CL3

225C

A

U30

MA

X32

25C

AP

or I

CL3

225C

A

RE

AD

Y1

C1+

2V

+3

C1-

4C

2+5

C2-

6V

-7

T2O

UT

8R

2IN

9R

2OU

T10

INV

ALI

D11

T2IN

12T1

IN13

FOR

CE

ON

14

GN

D18

R1O

UT

15R

1IN

16T1

OU

T17

VC

C19

FOR

CE

OFF

20

RP

26

4x 4

.7K

RP

26

4x 4

.7K

11

22

33

44

55

66

77

88

C15

60.

1uF

C15

60.

1uF

C15

10.

1uF

C15

10.

1uF

C14

50.

1uF

C14

50.

1uF

U31

MA

X32

25C

AP

or I

CL3

225C

A

U31

MA

X32

25C

AP

or I

CL3

225C

A

RE

AD

Y1

C1+

2V

+3

C1-

4C

2+5

C2-

6V

-7

T2O

UT

8R

2IN

9R

2OU

T10

INV

ALI

D11

T2IN

12T1

IN13

FOR

CE

ON

14

GN

D18

R1O

UT

15R

1IN

16T1

OU

T17

VC

C19

FOR

CE

OFF

20

RP

24

4x 4

.7K

RP

24

4x 4

.7K

11

22

33

44

55

66

77

88

RP

254x

4.7

KR

P25

4x 4

.7K

11

22

33

44

55

66

77

88

C14

90.

1uF

C14

90.

1uF

C14

30.

1uF

C14

30.

1uF

C15

31n

FC

153

1nF

C15

80.

1uF

C15

80.

1uF

JP46

JP46

12

P5

P5

5 9 4 8 3 7 2 6 1

J12

J12

1 2 3 4 5 6 7 8 9 10

P6

P6

5 9 4 8 3 7 2 6 1

C14

80.

1uF

C14

80.

1uF

JP50

JP50

12

3

RP

234x

4.7

KR

P23

4x 4

.7K

11

22

33

44

55

66

77

88

C15

71n

FC

157

1nF

JP47

JP47

12

JP52

JP52

12

3



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

B_A

[23:

0]

B_D

21

B_D

25B

_D24

B_D

[31:

0]

/CS

2

B_D

17

B_D

28B

_D27

B_D

26

B_D

18

B_D

31

B_D

23

B_D

19

B_D

30

B_D

16

/CS

[7:0

]

B_D

29

B_D

22

B_A

1

B_D

20

/IRQ

3

/IRQ

[7:1

]

/IRQ

4

B_A

0B

_D[3

1:0]

B_A

[23:

0]

/CS

[7:0

]

/OE

R/W

/IRQ

[7:1

]

DTI

N1

DTI

N2

DTO

UT1

DTO

UT2

/RS

TOU

T +3.3

V

+3.3

V+5

V

+3.3

V+3

.3V

+3.3

V+3

.3V

+3.3

V

+5V

+3.3

V+3.3

V

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

US

B C

ontro

ller

C

M52

3xE

VB

B

1616

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

US

B C

ontro

ller

C

M52

3xE

VB

B

1616

Frid

ay, A

ugus

t 10,

200

7

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SC

H-2

0380

US

B C

ontro

ller

C

M52

3xE

VB

B

1616

Frid

ay, A

ugus

t 10,

200

7

Dec

oupl

ing

capa

cito

rs

Hos

t

Dev

ice

500m

A p

er c

hann

el

HO

STE

NB

1 (J

P56

) - s

et b

etw

een

pins

2 &

3 if

usin

g P

ort 1

in H

OS

T m

ode.

Set

betw

een

pins

1 &

2 if

usi

ng P

ort 1

in O

TGor

DE

VIC

E m

ode

(def

ault)

.

OTG

Min

i-AB

Rec

epta

cle

Do

not p

opul

ate

OTG

Ena

ble

- NO

T FI

TTE

D b

y de

faul

t

The

ISP

1362

can

be

conf

igur

ed to

op

erat

e in

PIO

or D

MA

mod

e.Ju

mpe

r Set

tings

are

as

follo

ws:

D

MA

PIO

JP57

O

N

OFF

JP58

O

N

OFF

JP59

O

N

OFF

JP60

O

N

OFF

JP62

O

FF

O

NJP

63

OFF

ON

Def

ault

setti

ng is

DM

A e

nabl

ed

US

B S

erie

s "B

" CO

NN

US

B S

erie

s "A

" CO

NN

Def

ault

for J

P61

is F

ITTE

D

Mot

orol

a S

PS

TS

PG

- TE

CD

Col

dFire

Gro

up

Y2

12M

Hz

Y2

12M

Hz

C16

710

uF 1

6VC

167

10uF

16V

C17

20.

1uF

C17

20.

1uF

U34

MIC

2026

U34

MIC

2026

EN

A1

FLG

A2

FLG

B3

EN

B4

OU

TB5

GN

D6

IN7

OU

TA8

R91

10K

R91

10K

R93

1MR

931M

C16

81n

FC

168

1nF

J15

J15 1 2 3 4

C17

60.

1uF

C17

60.

1uF

R85

100K

R85

100K

C16

510

uF 1

6VC

165

10uF

16V

R84

22R

R84

22R

JP60

JP60

12

JP62

JP62

12

R88

22R

R88

22R

C16

047

pFC

160

47pF

C17

822

pFC

178

22pF

C16

60.

1uF

C16

60.

1uF

R86

100K

R86

100K

R92

100K

R92

100K

C17

31n

FC

173

1nF

R89

1KR

891K

R81

10K

R81

10K

JP57

JP57

12

J16

J16 1 2 3 4

JP59

JP59

12

JP61

JP61

12

C16

347

pFC

163

47pF

C17

010

nFC

170

10nF

C16

147

pFC

161

47pF

D33

D33

JP56

JP56

123

U33

ISP

1362

U33

ISP

1362

DG

ND

1

VC

C(5

.0)

56

AG

ND

51

VB

US

55

OTG

_DM

149

OTG

_DP

150

CP

_CA

P2

54C

P_C

AP

153

OTG

MO

DE

45

RE

SE

T32

DR

EQ

124

DR

EQ

225

DA

CK

128

DA

CK

229

INT2

31

H_P

SW

236

H_D

M2

46H

_DP

247

H_S

US

PD

/WU

P33

D_S

US

PD

/WU

P34

H_P

SW

135

GL

39

DG

ND

9

VC

C(3

.3)

4

CS

21R

D20

WR

22

INT1

30

ID48

A0

61A

162

VC

C(3

.3)

52V

CC

(3.3

)58

TES

T023

TES

T159

DG

ND

19

VC

C(3

.3)

14

TES

T260

CLK

OU

T38

D0

63D

164

DG

ND

27

VC

C(3

.3)

26

D2

2D

33

D4

5D

56

D6

7D

78

D8

10D

911

D10

12D

1113

D12

15D

1316

D14

17D

1518

VC

C(3

.3)

40

X2

44X

143

DG

ND

37

H_O

C1

42H

_OC

241

DG

ND

57

C17

40.

1uF

C17

40.

1uF

R87

22R

R87

22R

R82

10K

R82

10K

C17

722

pFC

177

22pF

JP63

JP63

12

R83

22R

R83

22R

C16

222

nFC

162

22nF

C16

447

pFC

164

47pF

JP58

JP58

12

C16

90.

1uF

C16

90.

1uF

C17

11n

FC

171

1nF

JP55

JP55

12

C17

51n

FC

175

1nF

J14

US

B M

ini-A

B C

ON

N

J14

US

B M

ini-A

B C

ON

N

1 2 3 4 5

C15

910

uF 1

6VC

159

10uF

16V

R90

10K

R90

10K

TP13

VB

US

1

TP13

VB

US

1

1



F

Part Number Notes

170-20380

AVX 08051C102KAT2A

AVX 08055C104KAT2A

TA016TCM106KBR

TPSC476K016R0350

C0805X7R250-103KNE

TPSD106K035R0300

AVX 08055C104KAT2A

T494A225K010AS

M5235E

VB

User’s M

anu

al, Rev. 2

reescale Sem

iconductor93

7 Evaluation Board BOMTable 28. M523xEVB Bill of Materials

Item Qty Reference Description Mfgr

1 1 N/A BARE PWB ; RE Rev X for M523XEVB RapidPCB

2 46 C1, C2, C3, C4, C12, C13, C14, C15, C18, C19, C24, C25, C26, C27, C37, C34, C39, C70, C71, C72, C73, C74, C75, C76, C77, C98, C99, C110, C111, C112, C113, C118, C124, C133, C134, C135, C136, C153, C155, C157, C168, C171, C173, C175, C182, C183

1nF 50V 0805, 5% COG Surface Mount Caps KOA

3 77 C5, C6, C7, C8, C9, C10, C11, C16, C17, C28, C29, C30, C31, C33, C35, C36, C38, C40, C42, C43, C44, C46, C47, C48, C49, C52, C53, C55, C57, C78, C79, C80, C81, C82, C83, C84, C85, C100, C101, C114. C115, C116, C117. C119, C120, C122, C123, C127, C130, C137, C138, C139, C140, C141, C142, C143, C144, C145, C146, C147, C148, C149, C150, C151, C152, C154, C156, C158, C166, C169, C172, C174, C176, C184, C185, C186, C187

0.1uF 25V 0805, 10% X7R Surface Mount Caps KOA

4 6 C20, C21, C22, C23, C180, C181 100pF 50V 0805 NPO or COG Surface Mount Caps

Venkel

5 2 C32, C128 10uF 16V 10% B Case Tant. AVX

6 2 C41, C45 47uF 16V C Case Tant. AVX

7 9 C50, C66, C94, C95, C102, C103, C104, C105, C170

10nF 25V X7R 0805 Surface Mount Caps Venkel

8 3 C51, C54, C56 10uF D Case 7343. Tant. AVX

9 8 C58, C59, C60, C61, C62, C63, C64, C179 2.2nF 25V NPO Venkel

10 7 C65. C67, C68, C69, C86, C88, C89 0.1uF 25V X7R 0805, 10% AVX

11 1 C87 2.2uF 10V A Case Tant. AVX

12 10 C90, C91, C92, C93, C96, C97, C106, C107, C108, C109

470pF 50V NPO or COG 0805, 5% Venkel

9

TPSE337K010R0100

ECA-1VM102 or UVZ1H102MHH

TA016TCM106KBR

AA3528SGC

AA3528SRC

AA3528YC

MBRS340T3

MRA4003T3

AA3528MBC

HI1206T500R-00

4527K Fuse Holder by KEYSTONE +0216005.H: Fuse by Littlefuse, 5A, 250V, 5 x 20mm glass

Part Number Notes

M5235E

VB

User’s M

anu

al, Rev. 2

4Freescale S

emiconductor

14 3 C121, C126, C129 330uF 10V D Case Tant AVX

15 1 C125 1000uF 35V Panasonic

16 3 C159, C165, C167 10uF 16V 10% B Case Tant. Venkel

17 2 C131, C132 10pF SMD 50V 0805 5% KOA or Philips

18 4 C160, C161, C163, C164 47pF SMD 50V 0805 5% KOA or Philips

19 1 C162 22nF SMD 50V 0805 5% KOA or Philips

20 2 C178, C177 22pF SMD 50V 0805 5% KOA or Philips

21 12 D1, D2, D3, D4, D6, D7, D9, D11, D14, D17, D33

GREEN LED Kingbright

22 3 D5, D23, D24 RED LED Kingbright

23 3 D8, D10, D12 YELLOW LED Kingbright

24 5 D13, D15, D16, D20, D22 Shottky Power Diodes On-Semi

25 2 D18, D19 SMA On-Semi

26 8 D25, D26, D27, D28, D29, D30, D31, D32 BLUE LED Kingbright

27 6 FB1, FB2, FB3, FB4, FB5, FB6 Ferrite Beads STEWARD

28 1 F1 5A Fast Blow FUSE Keystone

Table 28. M523xEVB Bill of Materials (continued)


F

S2105-02 or M22-2510205

S2105-03 or M22-2510305

609-2627

HFJ11-2450E

22-10-7128

39-26-7405

10-89-6404

22-27-2061

177983-2

1053378-1

22-10-2101

22-10-2041

440479-1 A

787780-1

787616-1

Part Number Notes

M5235E

VB

User’s M

anu

al, Rev. 2

reescale Sem

iconductor95

29 33 JP1, JP2, JP3, JP4, JP27, JP28, JP29, JP30, JP33, JP34, JP37, JP38, JP39, JP40, JP41, JP42, JP43, JP44, JP45, JP46, JP47, JP48, JP49, JP53, JP54, JP55, JP57, JP58, JP59, JP60, JP61, JP62, JP63

2-way Jumper Sullins or Harwin

30 30 JP5, JP6, JP7, JP8, JP9, JP10, JP11, JP12, JP13, JP14, JP15, JP16, JP17, JP18, JP19, JP20, JP21, JP22, JP23, JP24, JP25, JP26, JP31, JP32, JP35, JP36, JP50, JP51, JP52, JP56

3-way Jumper Sullins or Harwin

31 1 J1 2 x 13 BDM Connector - Shrouded Headers Thomas &Betts

32 1 J2 RJ45 Connector Halo

33 1 J3 1 x 12 ADC Header 0.1 Male Molex

34 1 J4 2 x 20 shrd. UNI3 Connector Male Molex

35 1 J5 2 x 20 eTPU Header 0.1 Male Molex

36 1 J6 1 x 6 HS/ENCO Header Male Molex

37 4 J7, J8, J9, J10 60 way Fine Pitch Surface Mount Connector AMP

38 1 J11 External Clock Input SMA Connector AMP

39 1 J12 1 x 10 QSPI Header Male Molex

40 1 J13 1 x 4 I2C Header 0.1 Male Molex

41 1 J14 USB MiniAB Connector AMP

42 1 J15 USB "series B" Connector AMP

43 1 J16 USB "series A" Connector AMP



9

ies CT1210LSC-100_ or 1210-103J

B82111-B-C24

747844-3

t RAPC722

2SV-02

4 X 4.7K, 4 X 0603

4 X 22

4 X 51

4 X 10K

4 X 10

1K

62

22.1R, 1%

Bourns 3314J-1 or Spectral Vishay 4G-103

10K

Part Number Notes

M5235E

VB

User’s M

anu

al, Rev. 2

6Freescale S

emiconductor

44 1 L1 10uH Inductor Central Technologor Delaven

45 2 L2, L3 Power Inductor Thru Hole Siemens

46 4 P1, P4, P5, P6 DB9 RS232 Port Thru Hole AMP

47 1 P2 2.1mm Barrel Power Connector Switchcraf

48 2 P3 2-way Bare Wire Power Connector Augat

49 18 RP1, RP2, RP8, RP9, RP10, RP11, RP12, RP14, RP15, RP16, RP17, RP20, RP21, RP22, RP23, RP24, RP25, RP26

ARV241, 4 x 4.7K ohm resistor pack KOA or Philips

50 1 RP3 ARV241, 4 x 22 ohm resistor pack KOA or Philips

51 4 RP4, RP5, RP6, RP7 ARV241, 4 x 51 ohm resistor pack KOA or Philips

52 1 RP13 ARV241, 4 x 10 K ohm resistor pack KOA or Philips

53 2 RP18, RP19 ARV241, 4 x 10 ohm resistor pack KOA or Philips

54 8 R1, R3, R52, R56, R59, R63, R80, R89 1K ohm 0805 Surface Mount Resistor KOA or Philips

55 2 R2, R4 62 ohm 0805 Surface Mount Resistor KOA or Philips

56 8 R5, R6, R28, R29, R72, R74, R83, R84, R87, R88

22R ohm 0805 Surface Mount Resistor KOA or Philips

57 1 R41 SMT POT Bourns

58 7 R7, R14, R76, R81, R82, R90, R91 10K ohm 0805 Surface Mount Resistor KOA or Philips



F

49.9R, 1%

4.7K

6.49K

220R

330

120

1M

22.1K, 1%

150

270R

1.8K

24.9R, 1%

560R

100

100K

108-2MS1T1B1M2QE

Part Number Notes

M5235E

VB

User’s M

anu

al, Rev. 2

reescale Sem

iconductor97

59 4 R8, R9, R10, R11 49.9R ohm 0805 Surface Mount Resistor KOA or Philips

60 8 R12, R49, R55, R60, R66, R67, R68, R69 4.7K ohm 0805 Surface Mount resistor KOA or Philips

61 1 R13 6.49K ohm 0805 Surface Mount Resistor KOA or Philips

62 4 R15, R16, R17, R18 220R ohm 0805 Surface Mount Resistor KOA or Philips

63 8 R19, R20, R21, R22, R23, R24, R25, R32 0 ohm 0805 Surface Mount Resistor KOA or Philips

64 9 R26, R27, R30, R31, R33, R34, R35, R36, R73

120 ohm 0805 Surface Mount Resistor KOA or Philips

65 2 R37, R93 1M ohm 0805 Surface Mount Resistor KOA or Philips

66 1 R38 22.1K ohm Surface Mount Resistor KOA or Philips

67 2 R39 150 ohm 0805 Surface Mount Resistor KOA or Philips

68 11 R42, R43, R44, R45, R46, R47, R48, R50, R70, R75, R78

270R ohm 0805 Surface Mount Resistor KOA or Philips

69 5 R51, R54, R58, R62, R65 1.8K ohm 0805 Surface Mount Resistor KOA or Philips

70 4 R53, R57, R61, R64 24R ohm 0805 Surface Mount Resistor KOA or Philips

71 1 R71 560R ohm 0805 Surface Mount Resistor KOA or Philips

72 2 R40, R77, R79 100 ohm 0805 Surface Mount Resistor KOA or Philips

73 3 R85, R86. R92 100K ohm 0805 Surface Mount Resistor KOA or Philips

74 1 SW1 Toggle Switch Apem



9

KS11R22CQD

25546NA6 (silver preferred) or 25546NLD (gold plate)

KS11R23CQD

78RB12

5015K

MR2A16ATS35C A

MC74LCX16245DT

SN74LVC1G11DBVR

MC74LCX245DT

SN65HVD230D

MCF5235CVM150

KS8721BL

AD9728BRU

AD780BR

NL17SZ08DFT2

LM393M

NL27WZ04DFT2

SN74HC04D

NL27WZ86US

Am29PL160CB-65RS

LM2596S-3.3

LM2596S-5

Part Number Notes

M5235E

VB

User’s M

anu

al, Rev. 2

8Freescale S

emiconductor

75 3 SW2, SW3, SW5 Surface Mount Switch - Black C & K

76 1 SW4 Slide Switch Apem

77 1 SW6 Surface Mount Switch - Red C & K

78 1 SW7 Configuration DIP switch 10 position SPDT Grayhill

79 13 TP1, TP2, TP3. TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13

Surface Mount Test Points Keystone

80 2 U1, U2 MRAM Freescale

81 3 U3, U4, U6 Buffers On-Semi

82 2 U5, U26 AND Gate TI

83 1 U7 Buffers On-Semi

84 2 U8, U9 CAN Transceivers TI

85 1 U10 ColdFire MCF5235 microprocessor Freescale

86 1 U11 Ethernet Transceiver Micrel

87 1 U12 A to D Converter Analog Devices

88 1 U13 Voltage Regulator Analog Devices

89 1 U14 AND Gate On-Semi

90 1 U15 Comparator

91 1 U16 2 Gate Inverter On-Semi

92 1 U17 6 Gate Inverter

93 1 U18 EXOR Logic Gate On-Semi

94 1 U19 16-bit flash memory AMD

95 1 U20 3.3V Regulator National

96 1 U21 5V Regulator National



F

h. LT1086CM

H5C-2E3 or F5C-2E3 or P1100-HCV or P1145-HCV

ADM708SAR

MC74LCX541DT

MT48LC4M16A2TG75L

MAX3225CAP or ICL3225CA

ISP1362BD

MIC2026-2BM

Am29PL320DB60RWP or MBM29PL3200BE70PBT

A

FOXS/250F-20 A

FOXS/120-20

Part Number Notes

M5235E

VB

User’s M

anu

al, Rev. 2

reescale Sem

iconductor99

97 1 U22 1.5V Regulator Linear Tec

98 1 U23 OSC. 3.3V 25MHz 4-pin Thru Hole FOX or Pletronics

99 2 U24, U25 Voltage Monitoring uP Supervisory Circuit Analog Devices

100 1 U27 Buffer Freescale

101 2 U28, U29 SDRAM Micron

102 3 U30, U31, U32 RS232 Transceiver Maxim

103 1 U33 USB OTG controller Philips

104 1 U34 Power Distrubution Switch Micrel

105 1 U35 32-bit flash memory AMD or Fujitsu

106 2 VIA1, VIA2 SMTP

107 1 Y1 25MHz Crystal FOX

108 1 Y2 12MHz Crystal FOX

Note: A = not populated at assembly.



Document Number: M5235EVBUMRev. 208/2007

How to Reach Us:

Home Page:www.freescale.com

Web Support:http://www.freescale.com/support

USA/Europe or Locations Not Listed:Freescale Semiconductor, Inc.Technical Information Center, EL5162100 East Elliot RoadTempe, Arizona 85284+1-800-521-6274 or +1-480-768-2130www.freescale.com/support

Europe, Middle East, and Africa:Freescale Halbleiter Deutschland GmbHTechnical Information CenterSchatzbogen 781829 Muenchen, Germany+44 1296 380 456 (English)+46 8 52200080 (English)+49 89 92103 559 (German)+33 1 69 35 48 48 (French)www.freescale.com/support

Japan:Freescale Semiconductor Japan Ltd.HeadquartersARCO Tower 15F1-8-1, Shimo-Meguro, Meguro-ku,Tokyo 153-0064Japan0120 191014 or +81 3 5437 [email protected]

Asia/Pacific:Freescale Semiconductor Hong Kong Ltd.Technical Information Center2 Dai King StreetTai Po Industrial EstateTai Po, N.T., Hong Kong+800 2666 [email protected]

For Literature Requests Only:Freescale Semiconductor Literature Distribution CenterP.O. Box 5405Denver, Colorado 802171-800-441-2447 or 303-675-2140Fax: [email protected]

Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative.

For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2007. All rights reserved.

http://www.freescale.com

http://www.freescale.com/epp

m5235evb user’s manual - nxp · 2016. 11. 23. · m5235evb user’s manual, rev. 2 2 freescale...

Documents