PIXEL 2012 1

Monolithic Active pixel Matrix with Binary cOunters

(MAMBO)Farah Khalid, Gregory Deptuch, Alpana Shenai,

Scott Holm, Ron Lipton

Fermi National Accelerator Laboratory

PIXEL 2012 2

Presentation outline• Nested well structure• MAMBO pixel electronics• Test results• Conclusions

- Fermi National Accelerator Laboratory is operated by Fermi Research Alliance, LLC under Contract DE-AC02-07CH11359 with the U.S. Department of Energy.- ASIC submission was covered by US-Japan Collaboration funds in collaboration with KEK, Japan

3PIXEL 2012

Characteristics of Buried P well (BPW)

Si (n-type) (40keV @ 1e12cm-2) P

0 2 4 6 8 10 12 14 16 18 200.0E+00

5.0E-02

1.0E-01

1.5E-01

2.0E-01

Capacitance between interference metal and pwell contact vs. Width of BPW

C_P Vdp=0.5v

C_P Vdp=2v

BPW Width (μm)

Cap

acita

nce

betw

een

Inte

rfer

ence

and

Pw

ell c

on-

tact

(fF

/μm

)

0 5 10 15 200.0E+00

2.0E-01

4.0E-01

6.0E-01

Capacitance between pwell and substrate vs. width of BPW

C_B Vdp=.5v

C_B Vdp= 2v

C_B Vdp=10v

BPW Width (um)

Cap

acita

nce

betw

een

pw

ell a

nd

subs

trate

(fF/

um)

0 5 10 15 20

-2.50E-002

-2.00E-002

-1.50E-002

-1.00E-002

-5.00E-003

0.00E+000

5.00E-003

Charge at Pwell vs Width of BPWV_dp= .5 V_bias= 0,1,2

012

BPW Width (um)

Cha

rge

dens

ity a

t Pw

ella

1 (fC

/um

)

PIXEL 2012 4

Characteristics of Nested Well structure

0.00E+00 5.00E+12 1.00E+138.50E-02

9.00E-02

9.50E-02

Capacitance between interference metal and BNW contact vs. BNW Dose

Vbnw=.5 Vdp=2

220

300

380

BNW dose cm-2

Capa

citan

ce b

etw

een

Inte

rfer

ence

met

al

and

BNW

cont

act (

fF/u

m)

0.00E+00 5.00E+12 1.00E+131.00E-27

1.00E-25

1.00E-23

1.00E-21

1.00E-19

Capacitance between interference metal and Pwell contact vs. BNW Dose

Vbnw=.5 Vdp=2

220

300

380

BNW dose cm-2

Capa

citan

ce b

etw

een

Infe

renc

e m

etal

and

Pw

ell c

onta

ct (F

/um

)

• C_N: Capacitance between interference metal and n well contact increases with increasing BNW dose, but reduces by increasing BNW implantation energy.

• C_P: Capacitance between interference metal and p well contact decreases with increasing BNW dose and by increasing BNW implantation energy.

• C_P: lower for nested well compared to just BPW

Si (n-type) (40keV @ 1e12cm-2) P

n (30keV @ 5e15cm-2) P

BNW energy (keV)

BNW energy (keV)

PIXEL 2012 5

SOI technology for detectors

BPW Nested BNW/BPW

– electric potential under any circuitry may be kept constant or change very little only by voltage from integrated charge

– gives increased C-to-V node capacitance – works with charge integrating pixels (3T-like), gain

may be nonlinear, – charge injections due to electronics activity may

be cancel out by sequential readout with exactly repeated patterns for control signals and CDS

– full isolation of the electronics and the detector charge collection node,

– electric potential under any circuitry is kept constant (AC ground)

– allows designs with amplification stages and virtual ground (CSA)

– Removes parasitics feedbacks and instabilities, – Unfortunately increases input capacitance of CSA

BNW BPW

BPW

PIXEL 2012 6

Shielding:– Tripple role of shielding between the SOI electronics and detector layer:

• to avoid back-gating in transistors (DC potential underneath the BOX shifts threshold of transistors),

• to avoid injection of parasitic charges from the SOI electronics to detector,• to avoid strong electric field in BOX that results in accelerated radiation damage.

This well separates digital circuitsfrom sensor substrate and prevents back gating effects

This well collects the charge carriers

SILVACO process simulatiom

Purpose of the nested well structure

Developed at Fermilab with KEK and OKI/Lapis

PIXEL 2012 7

pixel design with window discriminator and per pixel counter

MAMBO = Monolithic Active Pixel Matrix with Binary CountersMAMBO IV & V

integrating CSA w/ p-z network, shaping filter CR-RC2 with tp=200ns; gain=~100 mV/e-,ripple counter reconfigurable into shift register,DACs for threshold adjustment,control logic for testability

SOI LAPIS/OKI Semiconductor 0.2μm process

SHAPER WINDOW COMPARATOR

4b DAC H

4b DAC L

DDL Logic

COUNTER/

SHIFT

REGISTER

12b

ANALOG BUFFER

DIGITAL BUFFER

VthH

VthL Baseline

PREVIOUS PIXEL

NEXT PIXEL

Test

Output

Configuration Register -DAC setup (8bits) -Test setup (3bits)

NEXT PIXEL

PREVIOUS PIXEL

BLR PREAMP

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• Single pixel under test

• Selectable modes for analysis & characterization of various blocks• Analogue test mode; analyses:

noise, linearity and Dynamic Range

• Counter test mode

• DAC trimming mode

• Pixel disable mode

• Normal Operation mode

MAMBO V 50×52 pixels- testability at pixel level

for statistics analyzes

MAMBO test modes

PIXEL 2012 9

Preamplifier

Cfs=14fF, Cc=140fFProtection diode at Input

•Regulated Cascode with extra current boosting to increase gm of input transistor• Leakage current compensation• 1.7fF I/P test capacitance

Regulated-Folded cascode

Leakage current compensation

Test Setup

Feedbackcapacitance

Shaper coupling capacitance

strobe1

strobe2

In_test1

In_test2

Input

Regulated cascode

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Shaper and Baseline Restorer• CR-RC2 shaper• Regulated cascode to match preamplifier • Shaping time =200ns

BASELINE RESTORER

Clamping diodes

Feedback capacitance

Feedback resistance

RegulatedCascodeWith gainboosting

baseline

shaperOut

In

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Comparator• Hysteresis Comparator

• Connected to in_Vref during normal operationOR• Connected to baseline for trimmingOR• Connected to gnd! when disabled

trimming DAC current

source followers

in_Vref

baseline

gnd!

in

trim trimB

ib2 ib1

Out

disconnect

CalibrateOff

Calibrate

PIXEL 2012 12

Double Discriminator Logic

• Output of the Lower Threshold comparator behaves as a clock

• Output of the Upper Threshold comparator behaves as a Reset

• When both comparators fire the hit is not counted

Hits counted

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Counter /Shift Register

• 12 bit ripple counter

• Count switch disconnects counter from comparator while shifting

• CK_READ is external clock used for shifting data

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105 mm

Pixel Layout

Nested well conceptual

view

PIXEL 2012 15

MAMBO: TEST RESULTS

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Test Setup

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MAMBO V nested BNW/BPW: C-V & 1/C2 – V plots: HR1 substrate 325µm

• Voltage breakdown around 130V• Leakage current is 3 times larger compared to previous wafer (FZ)

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MAMBO V nested BNW/BPW: C-V & 1/C2-V plots: HR1 substrate < 1kΩ area (5.3 x 5.3 mm2)

• Voltage breakdown occurs before full depletion is achieved• Doping levels of substrate is not adequate (higher resistivity is desired)

PIXEL 2012 19Japan-US Cooperative Research Program Workshop, Dec. 20, 2011

Example of MAMBO IV results: no shift of PMOS & NMOS transistor IDS/VGS in nested wells at back-gate biases ranging from 0 to 100V

• For an NMOS transistor of size 41x(0.64µm/ 0.8µm) and PMOS transistor of size 41x(2µm/0.5µm) the plots indicate that there is no threshold voltage shifts on increasing the voltage on the die pad (VDP) from 0-100V

• whereas on increasing the voltage of BNW (VBNW) from 1-5V threshold voltage shifts of approximately 100mV for PMOS and 150mV for NMOS transistors is observed.

DP = 5VDP = 10VDP = 50VDP = 100VDP = 5VDP = 10VDP = 50VDP = 100V

DP = 5VDP = 10VDP = 50VDP = 100VDP = 5VDP = 10VDP = 50VDP = 100V

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Trimming DAC threshold scansDetector bias at 2V Detector bias at 20V

• For DAC current settings of 8nA to 64nA, with average non-linear LSB of 12mV to 27mV,corresponds to a voltage spread of ±90mV to ± 200mV respectively

• Digital circuit response independent of detector bias

PIXEL 2012 21

DAC Scans: Count vs. Threshold (VthL)

Varying Counter voltage Varying DAC current

• Baseline set at 400mV• VthL scanned from 350mV to 475mV

PIXEL 2012 22

IMAGE with Cd109 source (22keV)

(1.9mm x 1.9mm) square mask without mask

IWoRID 2012 23

BNW resistance simulation

• Shallow and lower concentration of BNW produces higher resistance across the N well contacts

• The resistance is independent of the Die pad voltage0 1 2 3 4 5 6 7 8 9 10

10

30

50

70

90

110

130

150

170

R_N vs V_dp; V_bnw=.51E+12; 220keV

1E+12; 300keV

1E+12; 380keV

5E+12; 220keV

5E+12; 300keV

5E+12; 380keV

1E+13; 220keV

1E+13; 300keV

1E+13; 380keV

V_dp (v)

Resis

tivity

bet

wee

n P1

,P2

elec

trod

es(k

ohm

um

)

BNW dose, energy

200 220 240 260 280 300 320 340 360 380 4000

50

100

150

200

R_N vs BNW Energy of ImplanationV_BNW=0.5 V_dp = 10

1.00E+12

5.00E+12

1.00E+13

BNW Energy (keV)

Resis

tivity

bet

wee

n N

1 ,N

2 el

ectr

odes

(koh

ms u

m)

BNW dose

PIXEL 2012 24

IMAGE with Cd109 source (22keV) with DiePad at 9V

(1.9mm x 1.9mm) square mask - Analogue oscillations when

Diepad voltage is increased beyond 3V

- Hypothesis: highly resistive BNW, requires more contacts

- Preamplifier gain reduced by operating front-end below 1V

- Image obtained with detector biased at 9V

PIXEL 2012 25

• Extensions made to the process closer to obtain a fully functional

detector with all satisfactory parameters

• Good effective collaboration with Lapis semiconductor

• First counting pixel SOI ASIC operated successfully with shielding of sensor from electronics

• Include more BNW contacts in the pixel layout to compensate for BNW resistivity. •Confirm and stabilize access to HR / FZ Si material • Optimize nested wells BNW-BPW to decrease input capacitance or implement alternative shielding method

• Provide back processing (implantation and annealing); limit depth of implantation to allow entrance window for autoradiograpy at low energy of particle (w or w/o back Al)

• Optimize thickness of wafers for actual application 50-100mm for tracking 500 - 700mm or more for X-ray imaging

Conclusions and Future Work

IWoRID 2012 26

Questions?