M. Dahlström, Z. Griffith, M. Urteaga, M.J.W. Rodwell University of California, Santa Barbara, CA, USA

X.-M. Fang, D. Lubyshev, Y. Wu, J.M. Fastenau and W.K. LiuIQE Inc, Betlehem, PA, USAgriffith@ece.ucsb.edu, mattias@ece.ucsb.edu, 805-893-8044, 805-893-5705 fax

InGaAs / InP DHBT’s with > 370 GHz f and fmax

using a Graded Carbon-doped Base

Parameter InP/InGaAs Si/SiGe benefit (simplified) collector electron velocity 3E7 cm/s 1E7 cm/s lower c , higher Jbase electron diffusivity 40 cm2/s ~2-4 cm2/s lower b

base sheet resistivity 500 Ohm 5000 Ohm lower Rbb

comparable breakdown fields

Consequences, if comparable scaling & parasitic reduction: ~3:1 higher bandwidth at a given scaling generation~3:1 higher breakdown at a given bandwidth

Problem for InP: SiGe has much better scaling & parasitic reduction

Present efforts in InP research community Development of low-parasitic, highly-scaled, high-yield fabrication processes

Why mesa DHBT?Continue to advance the epitaxial material for improved speed

Motivation for InP HBTs

High speed HBT: some standard figures of merit

Small signal current gain cut-off frequency (from H21)…

Maximum power gain (from U)…

bccexbcjec

Bcb CRRCC

qI

Tnk

f

2

1

icbCR

ff

bb ,8max

VI

C

c

cb

Collector capacitance charging time when switching…

How do we make HBT’s faster…

key device parameter required change

collector depletion layer thickness decrease 2:1

base thickness decrease 0.707:1

emitter junction width decrease 4:1

collector junction width decrease 4:1

emitter resistance per unit emitter area decrease 4:1

current density increase 4:1

base contact resistivity (if contacts lie above collector junction)

decrease 4:1

base contact resistivity (if contacts do not lie above collector junction)

unchanged

Required transistor design changes required to double transistor bandwidth

…easily derived from geometry / resistivity / velocity relationships

(C ’s, ’s, C/I ’s all reduced 2:1)

How do we improve gate delay for digital IC’s ?

clock clock clock clock

inin

out

out

cexLOGIC

LOGIC

Ccb

becb

becbC

LOGIC

IRq

kTV

V

IR

CCR

CCI

V

6

leastat bemust swing logic The

resistance base the through

charge stored

collector base Supplying

resistance base the through

charging ecapacitancDepletion

swing logic the through

charging ecapacitancDepletion

:by DeterminedDelay Gate

bb

depletion,bb

depletion,

max

logic

emitter

collector

min,

depl,

& not speed,clock for design toneed

:SiGen faster thabarely logic InP

high at lowfor low very bemust

22

objective.design HBTkey a is /High

total.of 80%-60% is

. with correlated not wellDelay

ff

JVR

v

T

A

A

V

V

I

VC

CI

CCIV

f

eex

effective

C

CE

LOGIC

C

LOGICcb

cbC

becbCLOGIC

Scaling Laws, Collector Current Density, Ccb charging time

base

emitter

collector

subcollector

base

emitter

collector

subcollector

Collector Field Collapse (Kirk Effect)

Collector Depletion Layer Collapse

)2/)(/( 2 cdsatcb TqNvJV

)2/)(( 2min, cTqNV dcb

2min,max /)2(2 ccbcbsat TVVvJ

Collector capacitance charging time is reduced by thinning the collector while increasing current

sat

C

CECE

LOGICCLOGICcCLOGICcb v

T

A

A

VV

VIVTAIVC

2/

emitter

collector

min,collector

cecbbe VVV )( hence , that Note

Challenges with Scaling

Collector-base scaling Mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer length → sets minimum size for collector Solution: reduce base contact resistivity → narrower base contacts allowedUnavailable solution: decouple base & collector dimensions

Compromise: physically undercut the collector semiconductor

Emitter Ohmic Resistivity: must improve in proportion to square of speed improvements

Current Density: self-heating, current-induced dopant migration, dark-line defect formation

Loss of breakdownavalanche Vbr never less than collector bandgap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power

Yield !!submicron InP processes have progressively decreasing yield

Fast DHBTs: high current density high temperature

0

5

10

15

20

25

30

35

40

-0.2 0 0.2 0.4 0.6 0.8 1 1.2

centerEdge

Te

mp

era

ture

Ris

e (

K)

Distance from substrate (m)

SC ES C B E E Metal

Max Trise in Collector

• Thermal conductivity of InGaAs ~ 5 W/mK• Thermal conductivity of InP ~ 68 W/mK

• Average Tj (Base-Emitter) =26.20°C• Measured Tj=26°C—good agreement

Conclusion…

Minimize InGaAs thickness in subcollector

Caused by Low K

of InGaAs

Prof. Ian Harrison

InGaAs 3E19 Si 400 Å

InP 3E19 Si 800 Å

InP 8E17 Si 100 Å

InP 3E17 Si 300 Å

InGaAs 8E19 5E19 C 300 Å

Setback 3E16 Si 200 Å

InP 3E18 Si 30 Å

InP 3E16 Si 1030 Å

SI-InP substrate

Grade 3E16 Si 240 Å

InP 1.5E19 Si 500 Å

InGaAs 2E19 Si 125 Å

InP 3E19 Si 3000 Å

Compared to previous UCSB mesa HBT results:

• Thinner InP collector—decrease c

• Collector doping increased—increase JKirk

• Thinner InGaAs in subcollector—remove heat

• Thicker InP subcollector—decrease Rc,sheet

High f DHBT Layer Structure and Band Diagram

Vbe = 0.75 V, Vce = 1.3 VEmitter

CollectorBase

UCSB mesa HBT process flow

UCSB mesa HBT process flow

UCSB mesa HBT process flow

UCSB mesa HBT process flow

UCSB mesa HBT process flow

InP HBT limits to yield: non-planar process

Emitter contact

Etch to base

Liftoff base metal

Failuremodes

Yield quickly degrades as emitters arescaled to submicron dimensions

base contact

emittercontact

base contact

S.I. substrate

base

sub collector

S.I. substrate

base

sub collector

S.I. substrate

base

sub collector

emitter

S.I. substrate

base

sub collector

Emitter planarization, interconnects

base contact

liftoff failure:emitter-baseshort-circuit

S.I. substrate

base

sub collector

base contact

excessiveemitter undercut

S.I. substrate

base

sub collector

S.I. substrate

base

sub collector

planarization failure: interconnect breaks

SEM of device before polymide passivation

Profile of high frequency device…

-- 0.6 um wide emitter by optical lithography 1.0 um thick -- emitters as small as 0.4 um wide fabricated

-- self aligned base contact as small as 0.3 um on both sides of emitter

Front view…

Emitter contact width = 0.6 um, base mesa width = 1.2 um

Physical emitter width = 0.5 um, collector undercut = 0.2 um

Area collector / Area emitter = 1.0 / 0.5 = 2

10-9

10-7

10-5

0.001

0.1

0 0.2 0.4 0.6 0.8 1

I_cI_b

I b, I

c (mA

)

Vbe

(V)

Vcb

= 0.3 V

nc= 1.37

nb= 1.92

Device dimensions• device area = 4.2 m2 • emitter metal 0.7 x 8 mm• emitter junction 0.6 x 7 mm • base mesa width = 1.7 m

DC gain: 8-10nc/nb: 1.04/1.55

Vbr,CEO: 5 V

Jc = 8 mA/m2 @ Vce=2.5 V

Jmax = 12 mA/m2 @ Vce=1.5 V

Device results—DC and Gummel plots for 150 nm collector

0

2

4

6

8

10

0 0.5 1 1.5 2 2.5

J e (m

A/

m2 )

Vce

(V)

Ajbe

=0.6 x 7 m2 Vcb

= 0 V

Ib step

= 0.4 mA

Device results—DC and rf…

30 nm InGaAs base: 8*1019/cm3 → 5*1019/cm3 150 nm InP collector 0.6 x 7 m emitter 0.5 m base contacts

base sheet: 603 /squarebase contacts: 20 -m2

emitter contacts: 10-15 -m2

collector sheet: 12 /square collector contacts: 9 -m2

0

5

10

15

20

25

30

1010 1011 1012

Gai

ns (

dB)

Frequency (Hz)

ft= 370 GHz

fmax

=375 GHzU

H21

MAG/MSG

0

2

4

6

8

10

0 0.5 1 1.5 2 2.5

J e (mA

/m

2 )

Vce

(V)

Ajbe

=0.6 x 7 m2 Vcb

= 0 V

Ib step

= 0.4 mA

freq (5.000GHz to 40.00GHz)

devi

ce_s

imul

atio

n..S

11p

devi

ce_s

imul

atio

n..S

22p

freq (75.00GHz to 110.0GHz)

devi

ce_s

imul

atio

n_W

..S11

pde

vice

_sim

ulat

ion_

W..S

22p

S21

p/20

S12

p*5

devi

ce_s

imul

atio

n_W

..S21

p/20

devi

ce_s

imul

atio

n_W

..S12

p*5

S-parameters and delay terms

Smith chart Summary of delay terms

S21/20S12 x5

S11

S22

Delay at this current point RelativeTau_ec 430 fs

RexCcb 13 fs 3.1 %RexClay 9 fs 2.0 %tau_f 314 fs 72.6 %

kT/qI times Cje 71 fs 16.5 %kT/qI times Ccb 16 fs 3.6 %kT/qI times Clayout 10 fs 2.3 %

SUM 433 fs 100.0 %

ft_corr 368 GHzft_meas 370 GHzRex-related 5.1 %

Extraction : ex=10 Ω-m2

vc=4.5105 m/sDevice dimensions• device area = 4.2 m2 • emitter metal 0.7 x 8 m• emitter junction 0.6 x 7 m • base mesa width = 1.7 m

Base metal resistance for very narrow contacts

• Resistance of e-beam deposited metals higher than “book” values.

• Metal resistivity increases when tbase metal <1000 A

2.2

2.4

2.6

2.8

3

3.2

3.4

0 500 1000 1500 2000 2500 3000 3500

Au

cm

Gold thickness (Å)

…An important contributor to Rbb for the base contact (Pd/Ti/Pd/Au, 25/170/170/630)

• s,base metal = 0.5 Ω/sq 3-8 Ω added to Rbb for 0.3 m base contact width

• this will generate thermal instability if Rex is very low—(how low…?)

Base-collector capacitance variation with Je

0

2

4

6

8

10

0 2 4 6 8 10

Ccb

/Ae (

fF/u

m2 )

Je=I

c /A

e, current density (mA/um2)

0.0 V

-0.2 V

Vcb

= -0.3 V

+0.3 V

+0.5 V

Ccb/Ic 0.26 ps / V

Rf performance over time, under bias

m1freq=308.0GHzdB(baseline..S(2,1))=0.000

m1

m1freq=308.0GHzdB(baseline..S(2,1))=0.000

m1freq=308.0GHzdB(baseline..S(2,1))=0.000

m1

m1freq=308.0GHzdB(baseline..S(2,1))=0.000

time = 3 minutes, f and fmax 308 GHz time = 3 hours, f and fmax 308 GHz

DC bias conditions: Vcb = 0.35 V, Vce 1.3 V J = 8.5 mA/m2

UCSB static frequency divider designs w/ DRC 2003 model

Divider speed w/ base mesa width

2.1 um 1.7 um 1.3 um

Rex = 15 m2

Rbb = 25 m2

113 127 143

Rbb = 20 115 129 145

Rbb = 15 117 132 148

Rbb = 10 120 135 152

Rex = 10 Rbb = 25 119 133 149

Rbb = 20 121 135 151

Rbb = 15 123 138 154

Rbb = 10 125 141 158

550 m

530 m

UCSB/ONR: Z. Griffith

Conclusions…

• We have achieved record performance for f in a InP mesa DHBT—370GHz, along with maintaining simultaneously high fmax—375GHz

• Much of the gains attributed to the work on the process and the collector—

• physical undercut

• thinning active material—2000A to 1500A

• doping higher to push Jkirk,max higher

• thinning InGaAs subcollector contact—500A to 125A, remove heat

What are we concentrating on now in our mesa process…• Contact resistance: need to drop Rex for simultaneous increase in ft and fmax

• Find way to increase base metal thickness: high ft and without lowing fmax

• Alternative base grade scheme—dual grade doping and alloy

Acknowledgment—

This work is supported by the Office of Naval Research under contract N00014-01-1-0024

On wafer LRL calibration…

• LRL calibration using on wafer Open, Zero-length through line, and delay line

• OSLT used to check U in DC-50 GHz band

• Probe pads separated by 460 m to reduce p-p coupling

• RF environment not ideal, need: thinning, air bridges, vias for parasitic mode suppression

S-parameter measurement test structure

SEM of patterned passivation w/ interconnects

Patterned polyimide passivation plasma etch Coplanar waveguide interconnects