lv1.1 lauren all 0103 1930 -...

SI-2 BUILDRALPH1.1

671

12-12-20111310A24893-0 MTR

David Cheng

AX1

LV1.1_Lauren

Everest Main Board

2012.1.3

CSC

REVDATE CHANGE NO.

E

D

C

B

A

7 6 5 4 3 2 1

7 6 5 4 3

E

D

C

B

A

8

FF

P/N

VER:

DATEDATEEE

DESIGNDRAWER

CHECK

8

INVENTECTITLE

SIZE CODE

SHEET of

DOC.NUMBER REV

1

POWER

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTECCORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE ORIN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUTWRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.

HSF Property:ROHS or Halogen-Free(5L3?)

RESPONSIBLE

SIZE=FILE NAME:

2

56. GPU-3-GPIO & THERMAL

CR/B CONN & JOG DIAL CONN & AU-USB30 CONN

63. GPU-10-CHANNEL B MEMORY (GDDR5)

INDEX

17. PVPCIE16. PVDDCI

18. POWER PAD

30. PCH29. SO-DIMM128. SO-DIMM0

21. CPU-120. CPU

12. VRPVSA11. VRP1V8S

32. PCH-2-PCIE & CLOCKS & SMBUS

15. VRPVCORE_DGPU

27. FAN & LOCAL SHUTDOWN

22. CPU-2-POWER

19. P5V0S & P3V3S & P1V5S

10. VRP1V05S_VCCP09. VRP1V5 & P0V75S08. VRP5V0A & VRP3V3A

13. PVCORE & PVAXG14. PVCORE & PVAXG

07. BATTERY CONN

05. POWER SEQUENCE

02. INDEX

PAGE01. PROJECT NAME

64. CARD READER BOARD

53. GPU52. SCREWS

47. USB30 REDRIVER46. RJ45

44. LVDS CONN43. HDMI

38. PCH-8-POWER37. PCH-7-POWER36. PCH-6-GPIO & CPU/MISC35. PCH-5-USB30 & USB20 & PCI34. PCH-4-LVDS & CRT & DISPLAY INTERFACE

41. KEYBOARD CONN & DC-JACK LED & TOUCHPAD CONN42. DISPLAY PORT

40. KBC39. PCH-9-VSS

03. BLOCK DIAGRAM04. POWER PROCEDURE

06. DC & BATTERY CHARGER

45. LAN

48. USB30 CONN1 & REAR SPEAKER CONN

51. WLAN CONN & BLUETOOTH CONN & HARDDRIVE PROTECTION

33. PCH-3-DMI & FDI & POWER MANAGEMENT

31. PCH-1-RTC & IHDA & SPI & LPC & SATA & EEPROM

55. GPU-2-BACO

65. ODD/B & WIRELESS AUDIO/B & POWER BUTTON/B

67. EMI

57. GPU-4-MEMORY CHANNEL A

66. TPM

58. GPU-5-MEMORY CHANNEL B

61. GPU-8-POWER & GPU LVDS60. GPU-7-VSS59. GPU-6-POWER

62. GPU-9-CHANNEL A MEMORY (GDDR5)

26. CPU-6-VSS & STRAP PIN25. CPU-5-POWER-GRAPHICS

54. GPU-1-PCIE INTERFACE

23. CPU-3-PCIE-GRAPHICS & DMI & FDI & EDP24. CPU-4-MEMORY BUS

49. AU/B CONN & HDD CONN & HD CONN & PBN CONN & ODD REDRIVER50. WIRELESS AUDIO/B CONN & MUTE BUTTON & LDPS/B CONN

AX11310A24893-0 MTR

LV1.1_Lauren

David Cheng 12-12-2011 2 67

Block Diagram

CSA3

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

USB 2.0

SATA0

PCIE

37.5MM X 37.5MM

DEBUG ONLY

+USB P2

D/B

M/B

DMI

PORT

LPC

PORT

KBC

HDMI

AUDIO CODEC

KEYBOARD

HDMI

ODD

DGPUPEGX8

DDR3

FDI

DDR3 SO-DIMM 0

USB P10

BLUETOOTH+

RPGA988B (SOCKET-G2)

X32GDDR5

(1GB)64MX32

V-RAMX4

P62~P63

LVDS

P44

P42

M2 29MM X 29MM

P43

P53~P61

LVDSX2

SATA2

P49

P49

SATA0SATA2

P20~P26

HDD

P49

THERMAL SENSORTI TMP302 P27

INT DMICP44 P50

HDA

P40

P41 P41

P50 P51

P51

RJ45P46

10/100/1000MHZ

AR8151

P45

USB 3.0 P3P50P50D/B

+USB P1

USB 3.0 P1

USB P4

P48 P44

WEBCAM

USB P5

P51

P29

1066/1333/1600 MHZ . 16GB MAXIMUM MEMORYIVY BRIDGE

P28

DDR3

DDR3 SO-DIMM 11066/1333/1600 MHZ . 16GB MAXIMUM MEMORY

USB P0

MAIN BATT

PANEL

AMD CHELSEA PRO 128BIT

CARD READER

DISPLAY

FCBGA PACKAGE P47

WLAN/WIMAX

ALS PROXIMITY

SENSOR CM3633

IDT 92HD91

SYSTEM CHARGER

P07

MINICARDP64

RTS5229SPI ROM

SPI

27 MM X 27 MM

ST MICRE HP302DLT8-MBD

ITE IT8572E/AX

P31BIOS

SPI

TOUCHPAD

USB 3.0

ACCELEROMETER

USB 2.0PANTHER POINTDPX2

MIC JACK

HP JACK X2

SUB WOOFER

REAR SPKR

FRONT SPKR

WIRELESS AUDIOP50

USB 3.0 REDRIVER

P30~P39

DC / DC SYSTEM POWERP06

TPMP66

SLB 9656

USB 3.0 P2

673

AX11310A24893-0 MTR

LV1.1_Lauren

12-12-2011David Cheng

Block Diagram

CSA3

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

P1V0S_VCCPP1V0S_VCCP

DGPU_PWR_EN

SCL

SDA

VO

PVAXG

ISL95836

VR_SVID_CLK

EN_CORE

VR_SVID_DATA

VR_SVID_ALERT#

EN_VPCIE EN

SDA

DDR3L_SEL

VRP3V3A

S5EN_P1V5

BATT_CLK

VO

BATT_DAT

PGOODGSCLK

PGOOD

VR_ON

VO

PVBAT

PG

PVPACK

ALERT#

VOUT

5/3.3V

AC_OK

BQ24728

ACDET

EN_P0V75 S3

FDMC7696

VOVREF

AON7410

P1V5_PG

TPS51219

VRP5V0A

AXG_PG

CORE_PG

PG

VO

RT8208

EN_DEM

VO

G9330TBPVCORE

P3V3SAO6402AL

TPS51123

ADAPTERP5V0S

P1V5S

EN_3V_5V

CHARGER

EN

VO

VID0

VCCSA_VID1

VCCSA_VID0

DGPU_PWROK

VID1

EN_PVCCSA

EN_P1V8

EN

VO

G9330TB

AT1530F11U

CORE_PWEN#

TPS51461

EN_P1V0_VCCP PG P5V0A

VO

PVDDCI

VRP1V8S

PVPCIE

VRPVCORE_DGPU

VCCIO_PG

VRP1V05S_VCCP

P3V3A

CORE_PWEN#

CORE_PWEN#

P0V75M_VREF

AO6402AL

AON7410

EN

VRPVSA

VRP1V5

P0V75S

TPS51216

EN

DGPU_PWROK

674

AX11310A24893-0 MTR

LV1.1_Lauren


POWER PROCEDURE

CSA3

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

Power sequence

675

AX11310A24893-0 MTR

LV1.1_Lauren


Block Diagram

CSA3

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

ACDET>3.15V = AC_OVP

ACDET>2.4V = AC_OK TO CHARGE

ACDET>1.8V = ADP_PRES HI

ACDET>0.6V = SMBUS OK

AX1

67

LV1.1_Lauren

1310A24893-0 MTR


21

R60

17

21

C60

20321

4 5678

Q6010

321

4 5678

Q6011

321

4 5678

Q6012

21

R60

46

21

D60

19

21R6020

21R6025

21

R60

48

9876

5 4 3

21

20

2

19181716

1514131211

10

1

U6000

21

C60

18

21

C60

16

21 L6016

21L6015

98765432

10

1JACK6015

2 1

D6018

21

R76

00

21

C60

24

21

D6015

3

21

D6017

21

R60

472

1

C60

02

4321

R6001

21

C60

12

21

C60

11

21

C60

10

21

C60

21

21

C6023

21

C60

48

21

PA

D60

15

21

C60

01

21

C60

00

21

L6000

3 2 145 6 7 8

Q6000

21

R60

27

3

21

D5049

2 1

C6027

21

R6026

21

C6026

21

C76

00

3 2 145 6 7 8

Q6001

2 1

D6016

21

C60

15

21

C60

17

21

R60

15

21

C60

33

2 1

C6031

4321

R6000

21

C6028

21

C60

30

21

C60

29

2 1

C6032

21

R60

18

21

R60

24

21

C60

25

21

R6043

21

R60

23

21

C60

47

21

C60

46

21

R60

28

21

C60

19

21

R60

21

21

R60

49

21

C60

22

21

R60

29

21

R60

30

40

6

740

40

35 40

41

41

6

740

PROF_HPW20008_10M100R_10P

1K_1%_2

12K_1%_2

0.0015UF_50V_2

1SS355VMTE_17

SEM_SM24_SOT23_3P_DY

CSC0805_DY

10UF_25V_5

10UF_25V_5

4.7UF_25V_5

0.01_1%_6

B0530W_7

0.1UF_25V_2

0.1UF_16V_2

CSC0402_DY

POWERPAD_2_0610

10UF_25V_5

CSC0805_DY

ETQP3W4R7WFN

RSC_0603_DY

AON7410

BAT54CW

0.047UF_16V_2

20_5%_5

2.2_5%_2

0.047UF_25V_3

TI_BQ24728_QFN_20P

CSC0402_DY

AON7410BAT54WS

1UF_10V_2

0_5%_2

0_5%_2

1000PF_50V_2

100pF_50V_2

AON7406

KC_FBMA_11_321611_121A60TKC_FBMA_11_321611_121A60T

1000PF_50V_2

100pF_50V_2

FDMC7696

1UF_25V_3

2_5%_6

2200PF_50V_2

RSC_0402_DY

0.1UF_25V_2

0.047UF_25V_2

0.1UF_16V_2

0.01_1%_6

CSC0402_DY

1UF_25V_3

AON7406

0.01UF_50V_2

4.3K_5%_2

10K_5%_2

4.3K_5%_2

36.5K_1%_2

100K_1%_2

CSC0402_DY

100PF_50V_2

4.3K_5%_2

300K_1%_2

1SS355VMTE_17

47K_1%_2

RSC_0402_DY

CSC0402_DY

RSC_0402_DY

A3 CS

Block Diagram

PVADPTR

P1V5S PVADPTR

P3V3A

P3V3AL

PVPACK

PVADPTR

PVADPTR PVBAT

PVBAT

PVPACK

P3V3AL

ADP_ID

PVBAT_CHG

VRPVPACK_PH

ACDRV

PVBAT_R

ACDRV

BATDRV

BATT_CLK

I_ADP

ADP_PRES

AC_OK

WHITE#

AMBER#

VRPVPACK_HG

VRPVPACK_CSP

VRPVPACK_CSN

VRPVPACK_LG

BATDRV

VADPBL

VRPVADPTR_CSN

VRPVADPTR_CSP

BATT_DAT

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

IN

12

NM

OS

_4D3S

D

G S

C

A2A1

OUT

NM

OS

_4D3S

D

G S

OUT

OUT

IN

OUT

OUT

OUT

BI

BI

IN

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

NMOS_4D3S

D

G

S

OUT

AC

NA

CP

CM

SR

CA

CD

RV

AC

PR

ES

LOD

RV

GN

DS

RP

SR

NB

AT

DR

V

ILIM

SCL

SDA

IOUT

ACDET

REGN

BTST

HIDRV

PHASE

VCC

TML

9

8

7

6

5

4

3

2

10

1

2 1

OUT

ININ

21

3

1 2

677

AX11310A24893-0 MTR

LV1.1_Lauren


G2G1

654321

CN6050

21

R6051

21

R6053

21

D75

06

21

C75

01

21

D75

04

21

C75

00

21

C60

50

21

R60

50

21

R60

52

640

640

BP0206C_B7200B3_9H

0.1UF_25V_2

PHP_PESD5V0S1BB_SOD523_2P

PHP_PESD5V0S1BB_SOD523_2P

100PF_50V_2

100_5%_2

100_5%_2

100PF_50V_2

2.2K_5%_2

2.2K_5%_2

A3 CS

Block Diagram

P3V3ALPVPACK

BATT_DATBATT_CLK

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

G

G

6

5

4

3

2

1

BI

12

12

BI

OCP=7AMP

OCP=8AMP OCP=8AMP

5.08V=((R6050/R6151)+1)*23.36V=((R6100/R6101)+1)*2

OCP=7AMP

SKIP:OOA=3.3V; PWM=2VREF; AUTO=GND

TON=3.3V:300KHZ/375KHZ

678

AX11310A24893-0 MTR

LV1.1_Lauren


21

C61

50

21

R61

6017

8

3

7 24

16

5 2

9 22

1425

14

23

11 20

15

6

1813

12 19

10 21

U610021

C61

10

21

C61

60

3

21

D6999

2 1PAD6100

2 1PAD6150

2 1PAD6121

21

C61

00

321 45678

Q6101

3 2 145 6 7 8

Q6151

21

C61

11

21

C61

23

21

R6155

21

C61

20

21

C61

21

21

R6114

21

R61

50

21

R61

51

21L6150

21

C61

61

3 2 145 6 7 8

Q6150

21

R76

15

21

C76

15

21

C6155

21

C61

22

21

R61

10

21

PA

D61

10

21

C6115

321 45678

Q6100

21

R61

13

21

R76

10

21

C76

10

21L6100

21

R61

00

21

R61

01

8 18

8 19

8

41

819

8

8

8

8 18

818

18

18

19

8

8

8

BAV70W_7_F

71.5K_1%_2

15.4K_1%_2

10UF_25V_5

220UF_6.3V

ETQP3W3R3WFN

10K_1%_2

POWERPAD_2_0610

4.7UF_25V_5_DY

AON7410

0.1UF_16V_2

RSC_0603_DY

AON7702A

CSC0402_DY

0.22UF_6.3V_2

2.2_5%_3

TI_TPS51123RGER_QFN_24P

10UF_6.3V_3

1UF_25V_3

73.2K_1%_2

POWERPAD_2_0610

2.2_5%_30.1UF_16V_2

AON7410

AON7702A

330K_5%_2_DY

1UF_6.3V_2

10UF_25V_5

4.7UF_25V_5_DY

RSC_0603_DY

CSC0402_DY

ETQP3W3R3WFN

220UF_6.3V

6.8K_1%_2

POWERPAD_2_0610

POWERPAD1X1M

10K_1%_2

A3 CS

Block Diagram

P3V3A

P3V3AL

PVBAT

P5V0A

EN_5V

VRP5V0A

VBATP

VRP5V0A_PH

VRP5V0A_LDO

EN_3V

VBATP

VRP3V3A_LDO

VRP3V3A_PH

VRP3V3A

PVBAT

VRP5V0A_VIN

PVADPTR

2VREF

VRP5V0A

VRP5V0A_PH5V_PG

VRP5V0A_HG

VRP5V0A_LG

VRP3V3A_HG

VRP3V3A_LG

SKIP_3V_5V

EN_3V_5V

VRP5V0A_VIN

VRP3V3A_LDO

VRP3V3A

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

OUT

ININ

12 IN

IN12

IN12

+

S G

D

SG

D

OUT

ININ

OUT

OUT

IN

NM

OS

_4D3S

D

G S

OUT

OUT

IN

12

IN

OUT

OUT

NM

OS

_4D

3S

D

GS

IN

IN

IN

+

VF

B1

VF

B2

GN

DS

KIP

SE

L

VR

EG

5E

NC

TM

L

TO

NS

EL

VIN

TR

IP2

TR

IP1

EN

0

VR

EF

DRVL2

VBST2

VREG3

VO2 VO1

PGOOD

VBST1

DRVH1

LL1

DRVL1

LL2

DRVH2

OCP=16AMP

OCP=12AMPMODE=100KOHM:TRACKING DISCHARGE1.511V=REFIN=1.8*(R6201/(R6200+R6201))

679

AX11310A24893-0 MTR

LV1.1_Lauren


21

R62

02

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14

U6200

4321

L6200

2 1PAD6200

21

C62

00

3 2 145 6 7 8

Q6201

3 2 145 6 7 8

Q6200

21

PA

D62

10

21

PA

D62

20

21

C62

16

21

C62

10

21

C62

11

21

R76

20

21

C76

20

21

C6215

21

R6215

21

C62

21

21

C62

20

21

R62

03

21R6200

21

C62

18

21

R62

01

21

C62

17

9

9

19

19

19

POWERPAD_2_0610

10UF_25V_5

4.7UF_25V_5

330UF_2V_9MR_PANA_-35%

POWERPAD1X1M

PCMC104T_1R0MN

POWERPAD_2_0610

FDMC8884

RSC_0603_DY

CSC0402_DY

FDMS0310AS

0.1UF_16V_2

0.22UF_6.3V_2

2.2UF_6.3V_3

2.2_5%_3

TI_TPS51216RUKR_QFN_20P

10UF_6.3V_5

100K_5%_2

66.5K_1%_2

10K_1%_2

0.1UF_16V_2

0.01UF_50V_2

52.3K_1%_2

A3 CS

Block Diagram

P5V0A

P0V75S

P0V75M_VREF

P1V5

PVBAT

VRP1V5

VRP1V5_PH

DDR3L_SEL

VRP1V5

P1V5_PG

VRP1V5_HG

VRP1V5_LG

EN_P1V5

EN_P0V75

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

VTTSNS

VTTREF

VTTGND

VTT

VREF

VLDOIN

VDDQSNS

VBSTV5IN

TRIP

TML

SW

S5

S3

REFIN

PGOOD

PGND

MODE

GND

DRVL

DRVH

12 IN

+

SG

D

NM

OS

_4D3S

D

G S

12

12IN

OUT

OUT

IN

IN

modify on 09/19

MODE=200KHZ:400KHZ

OCP=8AMP

OCP=12AMP

OCP=25AMP

VOUT=2*11.3/(10+11.3)=1.06V

6710

AX11310A24893-0 MTR

LV1.1_Lauren


21

R63

02

21

C63

20

21

R63

082

1R

6306

4321

L6300

3 2 145 6 7 8

Q6300

3 2 145 6 7 8

Q6301

2 1PAD6300

2 1PAD6301

2 1PAD6400

21R6307

21

C63

01

21

C63

10

21

C63

12

21

C63

11

21

PA

D63

10

21

C63

00

21

R63

03

21

R76

30

21

C76

30

21

C6315

21

C63

16

21

R6315

4

1

9

6

12

2

17 16

8

15

3

7

14

10

11

5

13

U6300

2 1

C6319

21

C63

08

10

10

22

19

19

22

25

POWERPAD_2_0610

CSC0805_DY


22UF_6.3V_5

CYN_PCMB063T_R33MS_4P

POWERPAD_2_0610

POWERPAD_2_0610

POWERPAD_2_0610

4.7UF_25V_5

10UF_25V_5

FDMC7696

RSC_0603_DY

CSC0402_DY

FDMS0306AS

0.1UF_16V_22.2_5%_3

2.2UF_6.3V_3

TI_TPS51219RTER_QFN_16P

200K_5%_2

47.5K_1%_2

0.01UF_50V_2

0_5%_2_DY

0.01uF_50V_2

11.3K_1%_2

2.2UF_10V_3

10K_5%_2

A3 CS

Block Diagram

P5V0A

P1V05S_VCCP

P1V0S_VCCP

P1V0S_VCCP

PVBAT

VRP1V05S_VCCP

VRP1V05S_VCCP

VRP1V05S_VCCP_PH

VCC_SENSE_VCCIO

VRP1V05S_VCCP_HG

VRP1V05S_VCCP_LG

EN_P1V0_VCCP

P1V0_VCCP_PG

VSS_SENSE_VCCIO

VCCIO_SEL

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

43

21

NM

OS

_4D3S

D

G SSG

D

12 IN

12

OUT

12

+

IN

IN

12

OUTIN

IN

VSNS

VREF

V5

TR

IP

SW

REFIN

PW

PD

PG

OO

D

PG

ND

MO

DE

GSNS

GN

D

EN

DL

DH

CO

MP

BS

T

OCP=4.5AMP

OCP=4.5AMP

1.84V=((R6973/R6972)+1)*0.8

6711

AX11310A24893-0 MTR

LV1.1_Lauren


2 1PAD6970

21

C69

70

21

C69

74

21

R69

73

21

R69

72

21L6970

21

C69

73

21

C69

71

8

1

9

2

6

7

3

4

5

U6970

21

R69

70

21

C69

72

11

11

19

POWERPAD_2_0610

22UF_6.3V_5

CSC0402_DY

PAN_ELL5PR2R2N

13K_1%_2

10K_1%_2

GMT_AT1530F11U_SOP8_8P

0.1UF_16V_2

10UF_6.3V_3

10_5%_2

0.1UF_16V_2

A3 CS

Block Diagram

P3V3A

P3V3A

P1V8S

VRP1V8S

VRP1V8S

VRP1V8S_PH

EN_P1V8

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

VIN

VCC

TML

REF

PG

ND

LX

GN

D

FB

ENIN

12 IN

OUT

OCP=7AMP

OCP=7AMP

6712

AX11310A24893-0 MTR

LV1.1_Lauren


21

C65

10

21PAD6510

2 1PAD6500

4321

L6500

21

R6525

21

R65

202

1

C65

24

21

C65

23

21

C65

20

21

C6503

21

C6502

21

C6501

21

C6500

21

C6522

21

R6521

21

C6515

21

R6502

21

C65

21

2 5

242322

15 141718

25

987

1110

416

212019

61

13

3

12

U6500

21

R6524

21

C65

11

12

12

12

12

25

19

25

25

19

12

22UF_6.3V_5_DY22UF_6.3V_5

POWERPAD_2_0610

22UF_6.3V_522UF_6.3V_5

CYN_PCMB063T_R33MS_4P

0.01UF_50V_2

3300PF_50V_2

0.22UF_6.3V_2

0.1UF_16V_2

RSC_0402_DY

TI_TPS51461RGER_QFN_24P

0_5%_2

0_5%_2

0_5%_2

5.11K_1%_2

1UF_6.3V_2

1UF_6.3V_2

22uF_6.3V_5

POWERPAD1X1M

0.1UF_16V_2

A3 CS

Block Diagram

P5V0A

PVSA

VRPVSAVRPVSA_PH

VRPVCCSA_IN

VRPVCCSA_IN

VRPVSA

VCCSA_SENSE

EN_SA

VCCSA_VID1

VCCSA_VID0

SA_PG

VRPVCCSA_IN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

1 2 OUT

IN12

43

21

IN

IN OUT

IN

IN

IN

OUT

IN

VR

EF

VO

UT

VID

1V

ID0

V5F

ILT

V5D

RV

TML

SLE

WP

GO

OD

MO

DE

GN

D

EN

CO

MP

BST

SW

SW

SWVIN

VIN

VIN

PGND

PGND

PGND

SW

SW

R6624 NAER L6610/L6620

R6621 NEAR ONE PH HI SIDE

R6719 NEAR L66710/L6720

6713

AX11310A24893-0 MTR

LV1.1_Lauren


21

C67

30

21

C67

29

21R6717

21R6627

21R6626

21

C66

292

1C

6731

21

C66

31

21

C66

30

21

C66

38

1T

P88

21

R67

16

21

C66

40

21

R66

36

21

R66

35

2 1

C6724

2 1

R6715

2 1

C6726

2 1

R6711

2 1R6714

21C6636

21

R6628

2 1

C6634

21R6631

21

R66

24

21

R66

33

21

R67

19

21

C6728

2 1

C6727

2 1

C6633

2 1

C6632

2 1

C6635

2 1

R6630

2 1

R6629

2 1

C6637

2 1

R6712

21

C6723

2 1

R6713

2 1

C6725

21

R66

23

21 R

6625

21

C66

26

21

C66

27

21 C

6628

21

R67

20

21

R67

18

21

C67

33

21

C67

32

21

R6723

21

R6721

21

R6722

21

R6620

21

R6622

21

R6621

21

R66

34

21

C66

39

9

8

25

26

29

32

21

7

5

39

16

24

35

28

33

22

36

19

41

4

10

27

34

23

1

14

40

1511

3

12

2

1338

17

37

18

30

3120

6 U6600

25

22

1314

14

14

14

1314

14

14

1314

14

1314

1322

14

1322

14

14

14

14

33

14

14

14

14

14

22

25

14

14

14

14

1322

22

19

2140

1322

14

0.1UF_10V_2

130_1%_2

54.9_1%_2

169K_1%_2

330PF_50V_22K_1%_2

150PF_50V_2

47PF_50V_2

267K_1%_2

499_1%_2

3.65K_1%_2

470PF_50V_2

330PF_50V_2

1_5%_2

1uF_6.3V_2

5.76K_1%_2

0_5%_2

2.2UF_10V_3

47PF_50V_2

150PF_50V_2

680PF_50V_2

267K_1%_2

2K_1%_2

499_1%_2470PF_50V_2

3.65K_1%_2

330PF_50V_2

1000PF_50V_2

0_5%_2_DY

1000PF_50V_2

549_1%_2

0.22UF_10V_2

CSC0402_DY

11.3K_1%_2

0.1UF_16V_2

10K_5%_NTC

2.61K_1%_2

TP24

INTERSIL_ISL95836HRTZ_T_TQFN_40P

866_1%_2

0.22UF_6.3V_2

0.22UF_16V_2

CSC0402_DY

0.22UF_16V_2

3.83K_1%_2

0.22UF_16V_2

27.4K_1%_2

470K_5%_NTC

3.83K_1%_227.4K_1%_2

470K_5%_NTC

0.22UF_16V_2

0.22UF_16V_2

2.61K_1%_2

11.3K_1%_2

10K_5%_NTC

0.1UF_16V_2

A3 CS

Block Diagram

P5V0A

P5V0A

P1V0S_VCCP

GFX_VCC_SENSE

VCCSENSE

VSUMG-

ISEN1

ISEN1G

VSUMG+

VSUMG-

ISEN2G

ISEN3

VSUM-

VSUM+

VSUM-

VR_SVID_CLK

VRPVAXG_BOOT1

VR_SVID_DATA

VRPVCORE_LG2

VRPVCORE_BOOT2

VRPVCORE_HG2

VRPVCORE_PH2

CORE_PG

VRPVCORE_BOOT1

VRPVCORE_HG1

CPWM3

VRPVCORE_PH1

VRPVCORE_LG1

VSSSENSE

GFX_VSS_SENSE

VRPVAXG_PH1

VRPVAXG_HG1

GPWM2

VRPVAXG_LG1

VR_SVID_CLK

VR_SVID_ALERT#

EN_CORE

CPU_PROCHOT#

VR_SVID_DATA

ISEN2

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

IN

IN

OU

T

IN

IN

IN

OU

T

OUT

OU

T

IN

OUT

BI

IN

OUT

OU

T

OUT

BI

OU

T

OUT

OUT

OUT

IN

IN

IN

OUT

IN

OUT

VR_ON

VR_HOT#

VDD

VCCP

UGATE2

UG

AT

E1G

UGATE1

SDA

SCKL

RT

NG

RT

N

PWM3

PW

M2G

PHASE2

PH

AS

E1G

PHASE1

PG

OO

DG

PG

OO

D

PAD

NTCG

NTC

LGATE2

LGA

TE

1G

LGATE1

ISUMPG

ISU

MP

ISU

MN

G

ISU

MN

ISE

N3_

FB

2

ISEN2G

ISE

N2

ISEN1G

ISE

N1

FB

G

FB

CO

MP

G

CO

MP

BOOT2

BO

OT

1GB

OO

T1

ALERT#

PVCORE OCP=112A

PVAXG OCP=55A

6714

AX11310A24893-0 MTR

LV1.1_Lauren


4321

L6710

4321

L6720

4321

L6630

4321

L6620

43

21

L6610

21

C68

02

21

C68

01

321

C66

03

98765 4

321

U6720

98765 4

321

U6630

3 2 145 6 7 8

Q6720

3 2 145 6 7 8

Q6710

21

C67

122

1C

6710

21

PAD6701

3 2 145 6 7 8

Q6721

3 2 145 6 7 8

Q6711

21

C67

132

1C

6711

21

C66

15

21

C66

14

21

C66

13

21

C66

16

21

C66

17

3 2 145 6 7 8

Q6630

3 2 145 6 7 8

Q6631

3 2 145 6 7 8

Q6621

3 2 145 6 7 8

Q6620

3 2 145 6 7 8

Q6611

3 2 145 6 7 8

Q6610

21

C66

12

21

C66

11

21

C66

10

21

C68

00

21

C68

03

21 C6722

21 C6721

21C6720

21

C66

25

21C6624

21C6623

21C6622

21R6615

21R6614

21R6616

21

R7663

21

C7663

21R6613

21R6607

21

C7662

21

R7662

21R6610

21R6609

21R6608

321

C6602

21

C7672

21

R7672

21R6709

21R6707

21R6708

21R6706

21

C7671

21

R7671

21R6704

21R6702

21R6703

321

C6700

21R6701

21

PAD6700

321

C6601

321

C66002

1

PAD6600

21

C7661

21

R7661

21 R6603

21 R6604

21 R6602

21R6601

13

13

13

13

1314

1314

13

1314

1314

13

13

13

13

13

13

13

13

1314

1314

13

1314

1314

1314

1314

13

13

13

13

13

POWERPAD_2_0610

470UF_2V

470UF_2V

ETQP4LR36AFM

10K_1%_2

3.65K_1%_2

10_1%_2

10UF_25V_5

10UF_25V_5

RSC_0603_DY

CSC0402_DY

ETQP4LR36AFM

10K_1%_2

3.65K_1%_2

10_1%_2

10UF_25V_5

4.7UF_25V_5_DY

RSC_0603_DY

FDMS0306AS

CSC0402_DY

FDMC7696

FDMS0306AS

0.1UF_16V_22.2_5%_3

POWERPAD_2_0610

470UF_2V

FDMC7696

0.1UF_16V_22.2_5%_3

INTERSIL_ISL6208BCRZ_T_QFN_8P1UF_6.3V_2

ETQP4LR36AFM

10K_1%_2

10UF_25V_5

10UF_25V_5

CSC0805_DY

RSC_0603_DY

POWERPAD_2_0610

FDMS7692

FDMS0300S

0.1UF_16V_22.2_5%_3

15UF_25V

100UF_25V

100UF_25V

68UF_25V

470UF_2V

3.65K_1%_2

10_1%_2

470UF_2V

ETQP4LR36AFM

10K_1%_2

3.65K_1%_2

10_1%_2

10UF_25V_5

CSC0805_DY

CSC0402_DY

CSC0805_DY

RSC_0603_DY

CSC0402_DY

ETQP4LR36AFM

10K_1%_2

3.65K_1%_2

10_1%_2

10UF_25V_5

FDMS7692 C

SC0805_DY

RSC_0603_DY

CSC0402_DY

FDMS0300S

FDMS7692

FDMS0300S

0.1UF_16V_22.2_5%_3

0.1UF_16V_22.2_5%_3

INTERSIL_ISL6208BCRZ_T_QFN_8P

1UF_6.3V_2

A3 CS

Block Diagram

P5V0A

PVBAT

PVCORE

PVCORE

PVCORE

P5V0A

PVBAT

PVBAT

PVAXG

PVAXG

VRPVBAT_AGX

VRPVAXG_PH1

VRPVBAT_CPU

VRPVCORE_PH1

VRPVCORE_PH2

ISEN1G

VSUMG+

VSUMG-

ISEN2G

VSUMG+

VSUMG-

VRPVAXG_LG1

VRPVAXG_HG1

VRPVAXG_BOOT1

GPWM2

VRPVCORE_HG1

VRPVCORE_LG1

VRPVCORE_BOOT1

ISEN1

VSUM+

VSUM-

ISEN2

VSUM-

VSUM+

VSUM+

VSUM-

ISEN3

VRPVCORE_HG2

VRPVCORE_LG2

VRPVCORE_BOOT2

VRPVCORE_HG3

VRPVCORE_PH3

CPWM3

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

+

OUT

OUT

OUTIN

OUT

OUT

OUT +

IN

IN

IN

IN

12

++

12

OUT

++

+TML

PHASE

FCCM

VCC

LGATE GND

PWM

BOOT

UGATE

OUT

TML

PHASE

FCCM

VCC

LGATE GND

PWM

BOOT

UGATE

NM

OS

_4D3S

D

G S

NM

OS

_4D3S

D

G S

OUT

12

SG

DSG

D

IN

IN

NM

OS

_4D3S

D

G SSG

D

SG

D

NM

OS

_4D3S

D

G SSG

D

NM

OS

_4D3S

D

G S

IN

+ +

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OCP=25AMPOCP=25AMP

6715

AX11310A24893-0 MTR

LV1.1_Lauren


21R6762

21

R67

612

1

R67

60

21

R67

592

1

R67

57

21

R67

56

21R6758

21

R67

50

21

R67

51

21

R67

54

21

C67

58

21

C67

57 21

R6753

21 R6755

21 C6754

9876

543

21 20

2

19 18 17 16

1514131211

10

1

U6750

21

C67

51

321

C67

50

3 2 145 6 7 8

Q6752

3 2 145 6 7 8

Q6751

3 2 145 6 7 8

Q6750

4321

L6750

21

C67

62

21

C67

61

21

C67

60

21

C6753

21

R76

752

1

C76

75

21

R6752

15

15

56

56

56

18

18

CSC0805_DY

10UF_25V_5

4.7UF_25V_5_DY

FDMS7692

0.001_1%_1W


0_5%_2

470UF_2V

RSC_0402_DY

PAN_ETQP4LR36ZFC_4P

RSC_0603_DY

CSC0402_DY

FDMS0310AS

FDMS0310AS

360K_1%_2

10UF_6.3V_3

49.9K_1%_2

RICH_RT8232AZQW_QFN_20P

0.1UF_16V_22.2_5%_3

49.9K_1%_234.8K_1%_2

2K_1%_2

2.1K_1%_2

2.15K_1%

2K_1%_2

2.15K_1%

1000PF_50V_2

0.22UF_10V_2

A3 CS

Block Diagram

P5V0A

PVBAT

PVCORE_DGPUVRPVCORE_DGPU

VRPVCORE_DGPU_PH

VRPVCORE_DGPU

POW_SW1

POW_SW2

POW_SW0

VRPVCORE_DGPU_HG

VRPVCORE_DGPU_LGEN_DGPU

DGPU_PG

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

IN

GN

DT

ON G0

G1

G2

CS

UGATE

PHASE

BOOT

VDD

GATE

D0

D1

D2

S1

S2

REFIN

REFO

PGOOD

FB

EN_MODE

+

IN

IN

IN

+

SG

D

SG

D

NM

OS

_4D3S

D

G S

OUT

ININ

OCP=6AMP

HIGH : 0.908V = 0.5 [ 1 + ( ( R6941//R6943) / R6942 ) ]LOW : 0.954V=0.5 ( 1+ R6941/R6942 )

6716

AX11310A24893-0 MTR

LV1.1_Lauren


21

R69

43

21

R69

422

1R

6941

21

C69

47

3 2 145 6 7 8

Q6940

21

C69

43

S

G

D

Q6941

21

PA

D69

40

21

C69

45

21

C69

40

21R6944

21

R69

40

21

C69

44

21

C69

41

1

32

4

65

U6940

21

C69

42

56

18

18

22UF_6.3V_5

22UF_6.3V_5

1K_5%_2

POWERPAD_2_0610

FDMC7672

806_1%_2

1000pF_50V_2

SSM3K17FU

90.9_1%_2

CSC0402_DY

100_1%_2

4.7UF_6.3V_3

47_5%_2

GMT_G9330TB1U_SOT23_6P

0.033UF_16V_2

0.1UF_16V_2

A3 CS

Block Diagram

P5V0A

P1V0S_VCCP

PVDDCI

VDDCI_SWVDDCI_PG

EN_VDDCI

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

NM

OS

_4D3S

D

G S

G

DS

12

IN

PGD

DRV

ADJ

VCC

EN

GND

OUT

IN

0.943V=0.5(1+R6951/R6952)

OCP=6AMP

6717

AX11310A24893-0 MTR

LV1.1_Lauren


21

R69

51

3 2 145 6 7 8

Q6950

21

C69

50

21

R69

52

21

C69

55

21

R69

50

1

32

4

65

U6950

21

C69

52

21

C69

51

21

PA

D69

50

18

FDMC7696

22UF_6.3V_5

POWERPAD1X1M

4.7UF_6.3V_3

90.9_1%_2

47_5%_2

0.033UF_16V_2

100_1%_2

GMT_G9330TB1U_SOT23_6P

0.1UF_16V_2

A3 CS

Block Diagram

P5V0A

P1V0S_VCCP PVPCIE

EN_VPCIE

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

NM

OS

_4D3S

D

G S

PGD

DRV

ADJ

VCC

EN

GND

IN

12

SI 1012

6718

AX11310A24893-0 MTR

LV1.1_Lauren


3

2 1

D6997

3

2 1

D6998

21

C69

53

21R3807

21

C38

04

21

C38

05

2 1R6953

21R754

21R3809

21

C69

46

2

13

D3801

21

R20

6

21

R20

5

21R3808

21PAD6135

2 1

C6997

2 1

C6998

21

C69

94

21

C69

95

21

C69

96

21

R6945

21R6999

18323655

16

15

16

8

17

3640 8

8

192540

18 32 36 55

15

55

DGPU_PWR_EN

P15V0A

100K_5%_2_DY

EN_VDDCI

EN_DGPU

0_5%_2

CSC0402_DY

VDDCI_PG

10K_5%_2

BAV99W_7_F

0.1UF_25V_2

0.1UF_25V_2

P3V3S P3V3S

P3V3AL

VRP5V0A

EN_VPCIE

DGPU_PWROKSKIP_3V_5V

VRP5V0A_LG

Block Diagram

CS

0.1UF_25V_2

A3

5V_PG

POWERPAD1X1M

CORE_PWEN

0.1UF_25V_20.1UF_25V_2

BAV99W_7_F

DGPU_PWR_EN

10K_5%_2

0.1uF_16V_2

DIODE-BAT54-TAP-PHP

DGPU_PG

10K_5%_2

0_5%_2

0.1uF_16V_2

0.1uF_16V_2

8.2K_5%_20_5%_2_DY

0_5%_2

PX_MODE

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

IN

1 2 OUTIN

IN

IN

OUT

IN

IN

OUT

OUT

IN

NC

IN

OUT OUT

(3.5A)

SI 1012

SI2 1229

(2.2A)

(6A)

AX11310A24893-0 MTR

19 67

LV1.1_Lauren


5

43

2

1

U5521

R76

9

21

C69

99

21

R76

8

21

R69

982

1R

6997

21

R95

3

21R952

21

C76

4

2

1

R362

21R3800

21R3801

21

C38

00

21

C38

032

1C

900

21R3806

21R3805

21

R38

04

21R3803

21

C38

02

21R3802

2

13

D3800

21

C38

01

21

C829

21

R688

21R52

21R624

2

1

3

Q13

21

C39

21

R76

321

45678

Q12

21

C85

1

21

C84

2

2

1

C682

2

1

C679

4

36521

Q85

4

36521

Q81

21R65

21R700

21R634

2

1

C845

2

13

Q49

2

1

R451

2

13

Q36

2

1

3Q90

2

1

R701

21 40

11

8

12

9

918192540

10

192140

13

9

12

8

18192540

40

40

10

40

18192540

49

192140

I112

P5V0S

P3V3S

P1V5

P15V0A

P5V0A

P3V3A P3V3S

P1V5S

P5V0S

P3V3S

P3V3AL

P3V3S

ALL_PWRGD_IN

EN_P1V8

EN_3V_5V

EN_SA

EN_P1V5

EN_P0V75CORE_PWEN

EN_P1V0_VCCP

CORE_PWEN#

EN_CORE

10K_5%_2

1000PF_50V_2

100_5%_2

100_5%_2P1V5_PG

SA_PG

1M_1%_2

CSC0402_DY

100K_1%_2

VBATP

CSC0402_DY

383K_1%_2

0.01UF_50V_2

10K_5%_2

CORE_PWEN

ALWAYS_PW_EN

0_5%_2

10K_5%_2

CSC0402_DY

0_5%_2

0_5%_2

+V5S & +V3S

CSA3

CPU_PWEN

P1V0_VCCP_PG

ON_LMV331SN3T1G_TSOP_5P

DIODE-BAT54-TAP-PHP

10K_5%_2

100K_1%_2

0.1uF_25V_2_DY

RESUME_PWEN

0.01UF_50V_2

100K_5%_2

10UF_6.3V_3

100K_1%_2

0.1UF_16V_2_DY

10UF_6.3V_3100_5%_2

0.1UF_16V_2

0.01UF_50V_210K_5%_2

CORE_PWEN

10uF_6.3V_3

AO6402AL

V3S_EN

0_5%_2

1M_5%_2

V3S_R_EN

2200PF_50V_2

SSM3K7002FU

AO6402AL

V5S_EN

AON7410

0_5%_247_5%_5

SSM3K7002FU

0_5%_2

CORE_PWEN#

47_5%_5

SSM3K7002FU

SSM3K7002FU

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

OUT

IN OUT

OUTIN

OUTIN

IN OUT

NC

OUTIN

OUTIN

OUT

IN

IN

IN G

DS

NMOS_4D3S

D

G

S

D

G

S

NMOS_4D1S

D

G

S

NMOS_4D1S

G

DS

G

DS

IN

+

OUT- -

+

GD

S

IN

IN

OUT

CPU

6720

AX11310A24893-0 MTR

LV1.1_Lauren


BLANK

CSA3

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

CPU SOCKET PN: 6026B0222201

SI 1201

AX1

67

LV1.1_Lauren

1310A24893-0 MTR


21

R11

82

1

R711

21R559

21R217

21R486

21R485

21

R487

21

C588

21R488

21

R479

2

13

Q5521 R116

21

R117

2

13

Q18

45

3

12

U6

21R556

21R558

21R226

21R227

21R213

21R225

21R222

1TP381TP361TP35

1TP301TP37

1TP321TP221TP26

1TP40

1TP181TP27

1TP281TP201TP17

1TP211TP24

21R48021R48421R119

21R70521R704

21R50821R506

21R541

21R544

21

R218

21R482

21R203

21

C693

21

R561

21R562

21R529

21

R531

AP33

AP30AR27

AN32

AP26AR28

AR26

A4A5AK1

R8

V8

AN34

AR33

AL32

C26

AP27AP29

AM34

AN33

A15A16

AL35

AL33

AR32AT31AR31AP32AT30AR30AR29AT28

A27A28

CN19

21

36

36

21

1340

33

32

32

32

28 29

32

21

2532

19 40

33

36

3640

3540

51

66

21

1940

P3V3A

P1V0S_VCCP

P3V3A P1V5S

P1V8S P1V8S

P1V5

P1V0S_VCCP

P3V3S

P1V0S_VCCPCLK_DP_P_RCLK_DP_N_R

DDR3_DRAMRST#_CPU

NV_CLE

H_PWRGD

PM_DRAM_PWRGD_CPU

CPU_PROCHOT#

PM_DRAM_PWRGD

CLK_DMI_PCH#CLK_DMI_PCH0_5%_2

0_5%_2CLK_DMI_PCH#_RCLK_DMI_PCH_R

0_5%_2 CLK_DP_P

1K_5%_2

51_5%_2

51_5%_2

51_5%_2

51_5%_2_DY

51_5%_2

51_5%_2

DDR3_DRAMRST#

1K_5%_2

1K_1%_2

0_5%_2_DY

4.99K_1%_2

XDP_TCLK

XDP_TRST#

XDP_TDI_R

XDP_PREQ#

XDP_TMS

XDP_TDO

XDP_DBRESET#

CLK_DP_N0_5%_2

1K_5%_2_DY

1K_5%_2_DY

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

TP24

140_1%_2

200_1%_225.5_1%_2

DDR3_DRAMRST#_CPU

XDP_PREQ#

XDP_TCLKXDP_TMSXDP_TRST#

XDP_TDOXDP_TDI_R

XDP_DBRESET#

TP24

TP24

TP24

BSS1380_5%_2

3300PF_50V_2

PCH_DDR_RST

FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER

2.2K_5%_2

1K_5%_2

1K_5%_2_DY

CORE_PWEN#

200_5%_2

SSM3K7002FU_DY

750_1%_2

RSC_0402_DY

43_5%_2

NXP_74AHC1G09GV_SOT753_5P

H_PM_SYNC

56_5%_2

PM_THRMTRIP#

H_PECI

130_1%_2

10K_5%_2

BUF_PLT_RST#

PM_DRAM_PWRGD_CPU

62_5%_2

47PF_50V_2

1.5K_5%_2

1K_5%_2

ALL_PWRGD_IN

CS

CPU-1

A3

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

IN

IN G

DS

OUT

ING

DS

OUTINOUT

Y

VCC

GND

B

A

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

ININ

ININ

IN

IN

IN

BI

IN

OUT

OUT

JTA

G &

BP

MM

ISCDD

R3

PW

R M

AN

AG

EM

EN

TT

HE

RM

AL

MIS

C

CLO

CK

S

UNCOREPWRGOOD

PROC_SELECT#

SKTOCC#

PM_SYNC

BPM#[7]

BPM#[6]

BPM#[5]

BPM#[4]

BPM#[3]

BPM#[2]

BPM#[1]

BPM#[0]

DBR#

TDO

TDI

TRST#

TMS

TCK

PREQ#

PRDY#

RESET#

SM_DRAMPWROK

THERMTRIP#

PROCHOT#

PECI

CATERR#

DPLL_REF_CLK

DPLL_REF_CLK#

BCLK

BCLK#

SM_RCOMP[0]

SM_DRAMRST#

SM_RCOMP[2]

SM_RCOMP[1]

R212 CLOSE TO CPU

(8.5A)

CLOSE TO VR

(94A)

67

AX11310A24893-0 MTR

LV1.1_Lauren


21

C12

6

21

C17

1

21

C17

2

21

C15

3

21

C15

8

21

C14

5

21

C15

1

21

C15

6

21

C16

5

21

C16

4

21

R491

21

R495

21

R200

21

R199

21

R22

4

21

R23

9

21

R21

1

21R22321R25021R212

21

R230

21

C60

72

1C

643

21

C60

8

21

C61

4

21

C60

6

21

C12

7

21

C13

12

1C

624

21

C11

8

21

C11

7

21

C12

4

21

C60

5

21

C33

2

21

C65

2

21

C63

5

21

C64

6

21

C65

5

21

C65

3

21

C32

5

21

C30

3

21

C61

8

21

C30

8

A10

AJ34

AJ28AJ30AJ29

B10

J14L10P10U10Y10

J23

AC10

A11A12A13A14B12B14C11C12C13C14

AG10

D11D12D13D14E11

E12E14F11F12F13

AH10

F14G12G13G14H11H12H14J11J12J13

AH13

AJ35

P27P28P29P30P31P32P33P34P35R26

AG27

R27R28R29R30R31R32R33R34R35U26

AG28

U27U28U29U30U31U32U33U34U35V26

AG29

V27V28V29V30V31V32V33V34V35Y26

AG30

Y27Y28Y29Y30Y31Y32Y33Y34Y35

AA26

AG31

AA27AA28AA29AA30AA31AA32AA33AA34AA35AC26

AG32

AC27AC28AC29AC30AC31AC32AC33AC34AC35AD26

AG33

AD27AD28AD29AD30AD31AD32AD33AD34AD35AF26

AG34

AF27AF28AF29AF30AF31AF32AF33AF34AF35

P26

AG26

AG35

CN19

13

13

13

13

13

10

10

PVCORE

P1V0S_VCCP

PVCORE

P1V0S_VCCP

P1V0S_VCCP

VR_SVID_DATAVR_SVID_CLKVR_SVID_ALERT#

VCCSENSEVSSSENSE

VCC_SENSE_VCCIOVSS_SENSE_VCCIO

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

130_1%_2

54.9_1%_2

CPU-2

CSA3

75_1%_2

43_5%_2

0_5%_20_5%_2

130_1%_2

100_1%_2

100_1%_2

10_5%_2

10_5%_2


10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

22UF_6.3V_5

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

OUTOUT

OUTOUT

OUTOUTOUTS

VID

SE

NS

E L

INE

S

PE

G A

ND

DD

R

CO

RE

SU

PP

LY

POWER

VCCIO40

VCCIO_SENSE

VCCIO31

VCCIO30

VCCIO29

VCCIO28

VCCIO27

VCCIO26

VCCIO39

VCCIO38

VCCIO37

VCCIO36

VCCIO35

VCCIO34

VCCIO33

VCCIO32

VCCIO25

VCCIO17

VCCIO16

VCCIO15

VCCIO14

VCCIO13

VCCIO11

VCCIO10

VCCIO9

VCCIO8

VCCIO7

VCCIO6

VCCIO5

VCCIO4

VCCIO3

VCCIO2

VCCIO24

VCCIO23

VCCIO22

VCCIO21

VCCIO20

VCCIO19

VCCIO18

VCCIO12

VCCIO1

VCC100

VCC99

VCC98

VCC97

VCC96

VCC95

VCC94

VCC93

VCC92

VCC91

VCC90

VCC89

VCC88

VCC87

VCC86

VCC85

VCC84

VCC83

VCC82

VCC81

VCC80

VCC79

VCC78

VCC77

VCC76

VCC75

VCC74

VCC73

VCC72

VCC71

VCC70

VCC69

VCC68

VCC67

VCC66

VCC65

VCC64

VCC63

VCC62

VCC61

VCC60

VCC59

VCC58

VCC57

VCC56

VCC55

VCC54

VCC53

VCC52

VCC51

VCC50

VCC49

VCC48

VCC47

VCC46

VCC45

VCC44

VCC43

VCC42

VCC41

VCC40

VCC39

VCC38

VCC37

VCC36

VCC35

VCC34

VCC33

VCC32

VCC31

VCC30

VCC29

VCC28

VCC27

VCC26

VCC25

VCC24

VCC23

VCC22

VCC21

VCC20

VCC19

VCC18

VCC17

VCC16

VCC15

VCC14

VCC13

VCC12

VCC11

VCC10

VCC9

VCC8

VCC7

VCC6

VCC5

VCC4

VCC3

VCC2

VCC1

VSS_SENSE_VCCIO

VIDSOUT

VIDSCLK

VIDALERT#

VSS_SENSE

VCC_SENSE

CLOSED TO CPU

C IS 0402

C IS 0402

AX1

67

1310A24893-0 MTR

23

LV1.1_Lauren


21C697

21C742

21C740

21C736

21C731

21C725

21C715

21C709

21C702

21C741

21C738

21C733

21C727

21C720

21C711

21C706

21R148

21R517

H28J27J29K27K30L28L31M30

D25E26D27F28E28G28

M33M28

H29J28J30K28K31L29L32M31

E25F26D28F27E29G27

M32M29

E35F30F33G31G34H32H35K34

B32C33E31D34F32E33

L35J33

F35G30G33H31H34J32J35L34

C32B33D31D33E32E34

M35K33

H22J21J22

H20

F17D19C19B20

E17D18C20B21

H17

J17

G18E20G19A22

F18E19H19A21

J19

J18

G15C16F16C17

F15D16E16C18

A17B16

A18

D15C15

C21F20D22G22

D21F21E22G21

B23A24B26B28

B24A25B25B27

CN19

54

54

54

23

23

23

54

54

54

54

54

54

54

54

54

54

54

54

54

23

23

23

23

23

23

23

23

23

23

23

23

23

54

54

54

54

54

54

54

54

33

33

33

33

33

33

33

33

33

33

33

33

54

54

54

54

54

54

54

54

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

44

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

44

44

44

44

44

44

P1V0S_VCCP

P1V0S_VCCP

PEG_C_TXN2

PEG_C_TXN1

PEG_C_TXN00.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2PEG_TXN2

PEG_TXN1

PEG_TXN0

PEG_C_TXP6

PEG_C_TXP7

PEG_C_TXP5

PEG_C_TXP4

PEG_C_TXP3

PEG_C_TXP1

PEG_C_TXP2

PEG_C_TXP0

PEG_C_TXN7

PEG_C_TXN5

PEG_C_TXN6

PEG_C_TXN3

PEG_C_TXN4

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

CPU-3

CSA3

PEG_TXN7

PEG_TXN6

PEG_TXN5

PEG_TXN3

PEG_TXN4

PEG_TXP0

PEG_TXP5

PEG_TXP4

PEG_TXP3

PEG_TXP2

PEG_TXP1

PEG_TXP6

PEG_TXP7

24.9_1%_2

PEG_C_RXN7PEG_C_RXN6PEG_C_RXN5PEG_C_RXN4PEG_C_RXN3PEG_C_RXN2PEG_C_RXN1PEG_C_RXN0

DMI_RXN(3)DMI_RXN(2)DMI_RXN(1)DMI_RXN(0)

DMI_TXP(3)

DMI_TXP(0)DMI_TXP(1)DMI_TXP(2)

DMI_TXN(3)DMI_TXN(2)DMI_TXN(1)DMI_TXN(0)

PEG_C_RXP7PEG_C_RXP6




PEG_TXP0

PEG_TXN7

PEG_TXN5PEG_TXN6

PEG_TXN3PEG_TXN4

PEG_TXN2

PEG_TXN0PEG_TXN1

PEG_TXP1

PEG_TXP6PEG_TXP7

PEG_TXP4PEG_TXP5

PEG_TXP3PEG_TXP2


24.9_1%_2

NB_EDP_HPD#

FDI_LSYNC1FDI_LSYNC0

FDI_INT

FDI_TXP(7)FDI_TXP(6)

FDI_FSYNC1FDI_FSYNC0

FDI_TXP(5)FDI_TXP(4)FDI_TXP(3)FDI_TXP(2)FDI_TXP(1)FDI_TXP(0)

FDI_TXN(7)FDI_TXN(6)FDI_TXN(5)FDI_TXN(4)FDI_TXN(3)FDI_TXN(2)FDI_TXN(1)FDI_TXN(0)

DMI_RXP(2)DMI_RXP(3)

DMI_RXP(1)DMI_RXP(0)

NB_EDP_AUX_DPNB_EDP_AUX_DN

NB_EDP_TX0_DPNB_EDP_TX1_DP

NB_EDP_TX0_DNNB_EDP_TX1_DN

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

IN

OUTOUTOUTOUTOUTOUTOUTOUT

IN

OUTOUTOUTOUTOUTOUTOUTOUT

ININ

IN

ININ

ININININ

INININININ

ININ

ININ

IN

ININ

ININ

ININ

IN

IN

OUTOUT

OUTOUT

OUT

OUTOUTOUTOUT

IN

OUTOUTOUTOUT

OUTOUTOUTOUT

OUTOUT

IN

OUTOUT

OUT

IN OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUTIN

IN

OUT

OUT

OUT

OUTOUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUTINOUT

OUTIN

OUTOUTOUT

eDP

Inte

l(R)

FD

ID

MI

PC

I EX

PR

ES

S*

- G

RA

PH

ICS

eDP_ICOMPO

eDP_HDP#

eDP_COMPIO

eDP_TX#[3]

eDP_TX#[2]

eDP_TX#[1]

eDP_TX#[0]

eDP_TX[3]

eDP_TX[2]

eDP_TX[1]

eDP_TX[0]

eDP_AUX#

eDP_AUX

PEG_TX[15]

PEG_TX[14]

PEG_TX[13]

PEG_TX[12]

PEG_TX[11]

PEG_TX[10]

PEG_TX[9]

PEG_TX[8]

PEG_TX[7]

PEG_TX[6]

PEG_TX[5]

PEG_TX[4]

PEG_TX[3]

PEG_TX[2]

PEG_TX[1]

PEG_TX[0]

PEG_TX#[15]

PEG_TX#[14]

PEG_TX#[13]

PEG_TX#[12]

PEG_TX#[11]

PEG_TX#[10]

PEG_TX#[9]

PEG_TX#[8]

PEG_TX#[7]

PEG_TX#[6]

PEG_TX#[5]

PEG_TX#[4]

PEG_TX#[3]

PEG_TX#[2]

PEG_TX#[1]

PEG_TX#[0]

PEG_RX[15]

PEG_RX[14]

PEG_RX[13]

PEG_RX[12]

PEG_RX[11]

PEG_RX[10]

PEG_RX[9]

PEG_RX[8]

PEG_RX[7]

PEG_RX[6]

PEG_RX[5]

PEG_RX[4]

PEG_RX[3]

PEG_RX[2]

PEG_RX[1]

PEG_RX[0]

PEG_RX#[15]

PEG_RX#[14]

PEG_RX#[13]

PEG_RX#[12]

PEG_RX#[11]

PEG_RX#[10]

PEG_RX#[9]

PEG_RX#[8]

PEG_RX#[7]

PEG_RX#[6]

PEG_RX#[5]

PEG_RX#[4]

PEG_RX#[3]

PEG_RX#[2]

PEG_RX#[1]

PEG_RX#[0]

PEG_RCOMPO

PEG_ICOMPO

PEG_ICOMPI

FDI1_LSYNC

FDI0_LSYNC

FDI_INT

FDI1_FSYNC

FDI0_FSYNC

FDI1_TX[3]

FDI1_TX[2]

FDI1_TX[1]

FDI1_TX[0]

FDI0_TX[3]

FDI0_TX[2]

FDI0_TX[1]

FDI0_TX[0]

FDI1_TX#[3]

FDI1_TX#[2]

FDI1_TX#[1]

FDI1_TX#[0]

FDI0_TX#[3]

FDI0_TX#[2]

FDI0_TX#[1]

FDI0_TX#[0]

DMI_TX[2]

DMI_TX[3]

DMI_TX[1]

DMI_TX[0]

DMI_TX#[3]

DMI_TX#[2]

DMI_TX#[1]

DMI_TX#[0]

DMI_RX[3]

DMI_RX[2]

DMI_RX[1]

DMI_RX[0]

DMI_RX#[3]

DMI_RX#[2]

DMI_RX#[1]

DMI_RX#[0]

AX11310A24893-0 MTR

24 67

LV1.1_Lauren

David Cheng 12-12-2011

AB9AB8

AD4AE4

R4R5AB10T1R1AB7R3T5R2T3T4T2T6R7T7AA8

AP15AK12AP9AN5N3K6F3D7

AP14AK11AP8AN6M3J6G3C7

AT15AR15AN15AT12AT14AR14AN14AT11AH12AJ12AR8

AH11AT9AT8

AJ11AR9AR5AR6AN8AP6AT6AT5AN9AP5AP2AN1AN2AN3AP3AR3AM6AM5

M1M2N5M4N1N2N4M5K7K8

J10J9K9

K10J8J7G2F2F5G5G1F1F4G4D8D9A8A9C8

D10A7C9

AE3AD3

AD1

AD2

AE1

AE2

R10

R9

AA10

R6AA7AA9

AE5AD5

AE6AD6

T10AB1AA1

T9AA2AB2

CN19

AF9AD9

AG3AH3

V7V5AF8W4V4AD8W5V1W6W3V2V3W7W2W1AD10

AM15AR12AM8AL6M6J3G6C4

AM14AR11AM9AL5N6K3F6D4

AH15AJ15AK14AL14AK15AL15AH14AJ14AN12AP12AL11

AM11AM12AL12AN11AP11

AL8AL9AH9AH8AK9AJ9AK8AJ8AJ6AJ5AH6AH5AK5AK6AG5AG6

M7N9M9

M10N7N8

N10M8K2J2J4J5J1K1K5K4G7G8F7F9G9

G10F8

F10C3C2C6D6D2D3D5C5

AL3AK3

AB5

AA6

AA5

AB6

V10

V9

AE8

V6AF10AE10

AH2AG2

AH1AG1

W10AA3AB3

W9AA4AB4

CN19

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

M_CKE3M_CLK_DDR#3M_CLK_DDR3

M_CLK_DDR2M_CLK_DDR#2M_CKE2

M_B_DQ(12)M_B_DQ(11)M_B_DQ(10)

M_B_DQ(8)M_B_DQ(9)

M_B_DQ(7)

M_B_DQ(5)M_B_DQ(6)

M_B_DQ(4)M_B_DQ(3)M_B_DQ(2)M_B_DQ(1)M_B_DQ(0)

M_B_DQ(13)

M_CS#3

M_ODT3M_ODT2

M_CS#2

M_B_DQS(4)

M_B_DQS(0)M_B_DQS(1)M_B_DQS(2)M_B_DQS(3)

M_B_DQS#(7)M_B_DQS#(6)




M_B_DQS(5)

CPU-4

M_B_A(13)

M_B_A(11)M_B_A(12)

M_B_A(9)M_B_A(8)

M_B_A(10)

M_B_A(5)M_B_A(4)M_B_A(3)

M_B_A(7)M_B_A(6)

M_B_A(0)M_B_A(1)M_B_A(2)

M_B_DQS(7)M_B_DQS(6)

CSA3

M_B_A(14)M_B_A(15)


M_B_DQ(33)

M_B_DQ(31)M_B_DQ(32)



M_B_DQ(25)




M_B_DQ(17)M_B_DQ(16)M_B_DQ(15)M_B_DQ(14)

M_B_DQ(53)







M_B_DQ(38)



M_B_DQ(54)

M_B_CAS#

M_B_BS2M_B_BS1M_B_BS0


M_B_DQ(61)




M_B_WE#M_B_RAS#

M_CLK_DDR1M_CLK_DDR#1M_CKE1

M_CKE0

M_CLK_DDR0M_CLK_DDR#0

M_A_DQ(0)

M_A_DQ(10)

M_A_DQ(8)M_A_DQ(9)

M_A_DQ(7)M_A_DQ(6)M_A_DQ(5)M_A_DQ(4)M_A_DQ(3)M_A_DQ(2)M_A_DQ(1)

M_A_DQS(2)M_A_DQS(1)M_A_DQS(0)

M_A_DQS#(4)M_A_DQS#(5)M_A_DQS#(6)M_A_DQS#(7)

M_A_DQS#(2)M_A_DQS#(3)

M_A_DQS#(1)M_A_DQS#(0)

M_ODT1

M_CS#0M_CS#1

M_ODT0

M_A_A(15)

M_A_A(12)M_A_A(13)M_A_A(14)

M_A_A(11)M_A_A(10)

M_A_A(8)M_A_A(7)M_A_A(6)

M_A_A(9)

M_A_A(5)M_A_A(4)M_A_A(3)M_A_A(2)M_A_A(1)M_A_A(0)

M_A_DQS(3)

M_A_DQS(7)M_A_DQS(6)M_A_DQS(5)M_A_DQS(4)


M_A_DQ(20)

M_A_DQ(18)M_A_DQ(19)


M_A_DQ(15)



M_A_DQ(21)

M_A_DQ(30)M_A_DQ(29)M_A_DQ(28)M_A_DQ(27)M_A_DQ(26)M_A_DQ(25)M_A_DQ(24)M_A_DQ(23)M_A_DQ(22)

M_A_DQ(31)


M_A_DQ(38)M_A_DQ(37)M_A_DQ(36)



M_A_DQ(41)

M_A_DQ(51)


M_A_DQ(48)M_A_DQ(47)M_A_DQ(46)



M_A_DQ(52)M_A_DQ(53)M_A_DQ(54)M_A_DQ(55)M_A_DQ(56)M_A_DQ(57)M_A_DQ(58)M_A_DQ(59)M_A_DQ(60)M_A_DQ(61)M_A_DQ(62)M_A_DQ(63)

M_A_BS2M_A_BS1M_A_BS0

M_A_WE#M_A_RAS#M_A_CAS#

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

BIBI

BIBI

BIBI

BI

BIBI

BI

BI

BI

BIBIBI

BIBI

BIBIBIBI

BI BIBIBIBIBI

BIBI

BI

OUT

BIBIBIBI

BIBIBI

BI

BI

BIBIBIBIBIBI

BIBI

BI

BI

BIBIBI

BIBIBIBIBIBI

BI

BI

BI

BIBIBIBI

BIBIBIBIBI

BI

BI

BIBI

BI

BI

BIBI

BI

BI

BI

BIBIBIBI

BIBI

BIBI

BI

BIBI

BIBIBIBIBI

BIBI

BI

BI

BI

BIBIBIBI

BIBI

BIBI

BI

OUT

BI

OUT

OUTOUT

OUTOUTOUT

OUTOUTOUT

OUT

BI

DD

R S

YS

TE

M M

EM

OR

Y B

SB_DQ[0]

SB_DQ[63]

RSVD_TP[20]

RSVD_TP[19]

RSVD_TP[18]

RSVD_TP[17]

SB_CS#[1]

SB_CS#[0]

RSVD_TP[16]

RSVD_TP[15]

RSVD_TP[14]

RSVD_TP[13]

RSVD_TP[12]

RSVD_TP[11]

SB_DQ[62]

SB_DQ[61]

SB_DQ[60]

SB_DQ[59]

SB_DQ[58]

SB_DQ[57]

SB_DQ[56]

SB_DQ[55]

SB_DQ[54]

SB_DQ[53]

SB_DQ[52]

SB_DQ[51]

SB_DQ[50]

SB_DQ[49]

SB_DQ[48]

SB_DQ[47]

SB_DQ[46]

SB_DQ[45]

SB_DQ[44]

SB_DQ[43]

SB_DQ[42]

SB_DQ[41]

SB_DQ[40]

SB_DQ[39]

SB_DQ[38]

SB_DQ[37]

SB_DQ[36]

SB_DQ[35]

SB_DQ[34]

SB_DQ[33]

SB_DQ[32]

SB_DQ[31]

SB_DQ[30]

SB_DQ[29]

SB_DQ[28]

SB_DQ[27]

SB_DQ[26]

SB_DQ[25]

SB_DQ[24]

SB_DQ[23]

SB_DQ[22]

SB_DQ[21]

SB_DQ[20]

SB_DQ[19]

SB_DQ[18]

SB_DQ[17]

SB_DQ[16]

SB_DQ[15]

SB_DQ[14]

SB_DQ[13]

SB_DQ[12]

SB_DQ[11]

SB_DQ[10]

SB_DQ[9]

SB_DQ[8]

SB_DQ[7]

SB_DQ[6]

SB_DQ[5]

SB_DQ[4]

SB_DQ[3]

SB_DQ[2]

SB_DQ[1]

SB_MA[15]

SB_MA[14]

SB_MA[13]

SB_MA[12]

SB_MA[11]

SB_MA[10]

SB_MA[9]

SB_MA[8]

SB_MA[7]

SB_MA[6]

SB_MA[5]

SB_MA[4]

SB_MA[3]

SB_MA[2]

SB_MA[1]

SB_MA[0]

SB_DQS#[3]

SB_DQS[3]

SB_DQS#[2]

SB_DQS[2]

SB_DQS#[1]

SB_DQS[1]

SB_DQS#[0]

SB_DQS[0]

SB_DQS#[7]

SB_DQS[7]

SB_DQS#[6]

SB_DQS[6]

SB_DQS#[5]

SB_DQS[5]

SB_DQS#[4]

SB_DQS[4]

SB_ODT[1]

SB_ODT[0]

SB_CKE[1]

SB_CKE[0]

SB_CLK#[1]

SB_CLK#[0]

SB_CLK[1]

SB_CLK[0]

SB_WE#

SB_RAS#

SB_CAS#

SB_BS[2]

SB_BS[1]

SB_BS[0]

OUTOUTOUT

OUTOUT

OUTOUTOUTOUT

OUT

BI

OUTOUT

OUTOUTOUT

OUT

OUTOUT

BI

OUT

OUTOUTOUT

OUTOUTOUT

OUTOUTOUT

BI

OUTOUTOUT

OUTOUT

OUTOUTBI

OUTOUTOUT

OUTOUTOUT

OUTOUTOUT

OUT

BI

OUTOUT

OUTOUTOUT

OUTOUT

BI

BIBIBI

BIBI

BIBI

BI

BI

BIBI

BIBIBIBIBIBIBI

BI

BI

BIBI

BI

BIBI

BIBI

BIBI

BI

BI

BIBI

BIBIBIBIBIBIBI

BI

DD

R S

YS

TE

M M

EM

OR

Y A

RSVD_TP[10]

RSVD_TP[9]

RSVD_TP[8]

RSVD_TP[7]

RSVD_TP[6]

RSVD_TP[3]

RSVD_TP[5]

RSVD_TP[4]

RSVD_TP[2]

RSVD_TP[1]

SA_DQ[63]

SA_DQ[62]

SA_DQ[61]

SA_DQ[60]

SA_DQ[59]

SA_DQ[58]

SA_DQ[57]

SA_DQ[56]

SA_DQ[55]

SA_DQ[54]

SA_DQ[53]

SA_DQ[52]

SA_DQ[51]

SA_DQ[50]

SA_DQ[49]

SA_DQ[48]

SA_DQ[47]

SA_DQ[46]

SA_DQ[45]

SA_DQ[44]

SA_DQ[43]

SA_DQ[42]

SA_DQ[41]

SA_DQ[40]

SA_DQ[39]

SA_DQ[38]

SA_DQ[37]

SA_DQ[36]

SA_DQ[35]

SA_DQ[34]

SA_DQ[33]

SA_DQ[32]

SA_DQ[31]

SA_DQ[30]

SA_DQ[29]

SA_DQ[28]

SA_DQ[27]

SA_DQ[26]

SA_DQ[25]

SA_DQ[24]

SA_DQ[23]

SA_DQ[22]

SA_DQ[21]

SA_DQ[20]

SA_DQ[19]

SA_DQ[18]

SA_DQ[17]

SA_DQ[16]

SA_DQ[15]

SA_DQ[14]

SA_DQ[13]

SA_DQ[12]

SA_DQ[11]

SA_DQ[10]

SA_DQ[9]

SA_DQ[8]

SA_DQ[7]

SA_DQ[6]

SA_DQ[5]

SA_DQ[4]

SA_DQ[3]

SA_DQ[2]

SA_DQ[1]

SA_DQ[0]

SA_MA[15]

SA_MA[14]

SA_MA[13]

SA_MA[12]

SA_MA[11]

SA_MA[10]

SA_MA[9]

SA_MA[8]

SA_MA[7]

SA_MA[6]

SA_MA[5]

SA_MA[4]

SA_MA[3]

SA_MA[2]

SA_MA[1]

SA_MA[0]

SA_DQS#[7]

SA_DQS[7]

SA_DQS#[6]

SA_DQS[6]

SA_DQS#[5]

SA_DQS[5]

SA_DQS#[4]

SA_DQS[4]

SA_DQS#[3]

SA_DQS[3]

SA_DQS#[2]

SA_DQS[2]

SA_DQS#[1]

SA_DQS[1]

SA_DQS#[0]

SA_DQS[0]

SA_ODT[1]

SA_ODT[0]

SA_CS#[1]

SA_CS#[0]

SA_CKE[1]

SA_CKE[0]

SA_CLK#[1]

SA_CLK#[0]

SA_CLK[1]

SA_CLK[0]

SA_WE#

SA_RAS#

SA_CAS#

SA_BS[2]

SA_BS[1]

SA_BS[0]

(10A)

SB MOUNT R490

SB OPENSB MOUNT

(1.2A)

(6A)

SB OPEN

IVYB MOUNT R483

Stuff

NAFor SB

Q1 R109

NA

R111Q5

For IB

SB MOUNT

Stuff

(26A)

SI 1102

AX1

6725

1310A24893-0 MTR

LV1.1_Lauren


21

C63

7

21

C16

7

21

C16

6

21

C65

4

21

R240

21

R202

21

R201

2 1R481

21

R47

8

21

R65

23 21

R65

22

21R490

21

R52

6

21

R11

1

21R112

2

1

3

Q5

2

1

3

Q1

21

R10

9

21R110

21

C94

21

C587

2 1R483

2

1

3

Q51

21

C93

21

C60

9

21

C59

6

21

C60

1

21

C61

0

21

C14

6

21

C16

0

21

C15

7

21

C14

7

21

C14

9

21

C14

8

21

C16

1

21

C15

9

21

C11

4

21

C11

3

21

C11

1

21

C11

2

21

C11

6

21

C11

5

AK34

Y1Y4Y7AC1AC4AC7AF1AF4

P1P4P7U1U4U7

AF7

C24C22

H23

H25H26J24J25J26L26M26M27

A2A6B6

A19

AK35

AR21AR23AR24AT17

AH17AH18AH20AH21AH23

AT18

AH24AJ17AJ18AJ20AJ21AJ23AJ24AK17AK18AK20

AT20

AK21AK23AK24AL17AL18AL20AL21AL23AL24

AM17

AT21

AM18AM20AM21AM23AM24AN17AN18AN20AN21AN23

AT23

AN24AP17AP18AP20AP21AP23AP24AR17AR18AR20

AT24

AL1

D1B4

CN19

13

13

12

12

12

10

2525

181940

212532

21 25 32

25

21 25 32

P1V8S

PVAXG PVAXG

CPUDDR_WR_VREF1_M

PVSA

PVSA

P1V5S

PVAXG

CPUDDR_WR_VREF2_M

P0V75M_VREF

P0V75M_VREF_H

P0V75M_VREF_H P1V5S

GFX_VCC_SENSEGFX_VSS_SENSE

VCCSA_VID0VCCSA_VID1

VCCSA_SENSE

VCCIO_SEL

DDR_WR_VREF02DDR_WR_VREF01

1K_1%_2_DY

1K_1%_2_DY

3300PF_50V_2

0_5%_2_DY

0_5%_2

AM2302N

CORE_PWEN

PCH_DDR_RST100_1%_2

100_1%_2

PCH_DDR_RST

AM2302N

0.1UF_16V_2_DY

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

10uF_6.3V_3

10uF_6.3V_3

10uF_6.3V_3

CPU-5

CSA3

10K_5%_2

2.2UF_6.3V_2_DY

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

DDR_WR_VREF02DDR_WR_VREF01

100_1%_2

10K_5%_2

10K_5%_2_DY

0_5%_2_DY


1K_5%_2_DY

22UF_6.3V_5

22UF_6.3V_5

AM2302N

PCH_DDR_RST

0_5%_2_DY

1K_5%_2_DY

22UF_6.3V_5

22UF_6.3V_5

470uF_2V

22UF_6.3V_5

22UF_6.3V_5

10UF_6.3V_3

10UF_6.3V_3

22UF_6.3V_5

22UF_6.3V_5

1UF_6.3V_2

1UF_6.3V_2

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

IN

IN

IN

G

DS

IN

IN

G

DS

OUTOUT

OUTOUT

OUT

OUT

G

D S

IN

OUTOUT

+

MIS

CV

RE

FS

A R

AIL

1.8V

RA

IL

LIN

ES

SE

NS

ED

DR

3 -1

.5V

RA

ILSG

RA

PH

ICS

POWER

VCCIO_SEL

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

VCCSA_VID[0]

VCCPLL3

VCCSA_VID[1]

VCCSA_SENSE

VCCSA8

VCCSA7

VCCSA6

VCCSA5

VCCSA4

VCCSA3

VCCSA2

VCCSA1

VCCPLL2

VCCPLL1

VDDQ10

VDDQ9

VDDQ8

VDDQ7

VDDQ6

VDDQ5

VDDQ4

VDDQ3

VDDQ2

VDDQ1

VDDQ15

VDDQ14

VDDQ13

VDDQ12

VDDQ11

VAXG54

VAXG53

VAXG52

VAXG51

VAXG50

VAXG49

VAXG48

VAXG47

VAXG46

VAXG45

VAXG44

VAXG43

VAXG42

VAXG41

VAXG40

VAXG39

VAXG38

VAXG37

VAXG36

VAXG35

VAXG34

VAXG33

VAXG32

VAXG31

VAXG30

VAXG29

VAXG28

VAXG27

VAXG26

VAXG25

VAXG24

VAXG23

VAXG22

VAXG21

VAXG20

VAXG19

VAXG18

VAXG17

VAXG16

VAXG15

VAXG14

VAXG13

VAXG12

VAXG11

VAXG10

VAXG9

VAXG8

VAXG7

VAXG6

VAXG5

VAXG4

VAXG3

VAXG2

VAXG1 VAXG_SENSE

VSSAXG_SENSE

SM_VREF

SI 1115

SI 1115

PCIE PORT BIFURCATION STRAP

SB MOUNT

PEGX16 STATIC LAN REVERSAL

DISPLAY PORT PRESENCE STRAP

PEG DEFER TRAINING

STRAP PIN

PEG X4 LANE REVERSAL

AX1

6726

LV1.1_Lauren

1310A24893-0 MTR


21 R233

21R557

21R555

21R546

21R543

21R540

21R554

AH31

AH33

AH26

AJ33

AH27

AJ31

B35A34A33B34

AR34AP35AT33AT34

AR1AT1AT2

C35

AR35

F24F25

AM35

AK32AJ32

AJ26

G16H16J16T8

AJ27AM33AT26

W8AK2AE7AG7L7

J15

B18J20

C29A30B31D30B29B30A31C30D23E23G24G25D24F23

B1

AM30AM32AM31AL30AL29AK26AL27AL26

AN29AK31AM27AN26AN31AN28AM26AM28

AK29AK28

AN35

CN19

A3A20A23A26A29A32A35B2B3B5B7B8B9B11B13B15B17B19B22C1C10C23C25C27C28C31C34D17D20D26D29D32D35E1E2E3E4E5E6E7E8E9E10E13E15E18E21E24E27E30F19F22

F29F31F34G11G17G20G23G26G29G32G35H1H2H3H4H5H6H7H8H9

H10H13H15H18H21H24H27H30H33J31J34K26K29K32K35

L1L2L3L4L5L6L8L9

L27L30L33

M34N26N27N28N29N30N31N32N33N34N35

P2P3P5P6P8P9

T26T27T28T29T30T31T32T33T34T35

CN19

AH22AH25

AH28AH29AH30AH32AH34AH35AJ1

AT13 AJ2AJ3AJ4AJ7AJ10AJ13AJ16AJ19AJ22

AJ25

AT16

AK4AK7

AK10AK13AK16AK19AK22AK25AK27AK30

AT19

AK33AL2AL4AL7

AL10AL13AL16AL19AL22AL25

AT22

AL28AL31AL34AM1AM2AM3AM4AM7

AM10AM13

AT25

AM16AM19AM22AM25AM29

AN4AN7

AN10AN13AN16

AT27

AN19AN22AN25AN27AN30AP1AP4AP7

AP10AP13

AT29

AP16AP19AP22AP25AP28AP31AP34AR2AR4AR7

AT32

AR10AR13AR16

U2

AR19

U3U5U6U8U9W26W27W28W29W30

AR22

W31W32W33W34W35Y2Y3Y5Y6Y8

AR25

Y9AB26AB27AB28AB29AB30AB31AB32AB33AB34

AT3

AB35AC2AC3AC5AC6AC8AC9AD7AE9AE26

AT4

AE27AE28AE29AE30AE31AE32AE33AE34AE35AF2

AT7

AF3AF5AF6AG4AG8AG9AH4AH7AH16AH19

AT10

AT35

CN19

26

26

26

26

26

26

26

26

26

0_5%_2_DY

CFG(2)

CFG(7)

CFG(5)CFG(6)

CFG(4)CFG(3)

1K_5%_2_DY

1K_1%_2_DY

1K_5%_2

1K_5%_2

1K_5%_2

1K_1%_2_DY

CFG(2)

CFG(3)

CFG(7)

CFG(6)

CFG(5)

CFG(4)




A3 CS

CPU-6

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

IN

IN

IN

IN

IN

IN

RE

SE

RV

ED

VSS_DIE_SENSE

VCC_DIE_SENSE

BCLK_ITP#

BCLK_ITP

KEY

VSS_VAL_SENSE

VCC_VAL_SENSE

VSSAXG_VAL_SENSE

VAXG_VAL_SENSE

RSVD5

RSVD10

RSVD_NCTF4

RSVD25

RSVD33

RSVD32

RSVD14

RSVD13

RSVD12

RSVD11

RSVD9

RSVD8

RSVD37

RSVD24

RSVD23

RSVD21

RSVD22

RSVD19

RSVD20

RSVD18

RSVD17

RSVD15

RSVD16

RSVD27

RSVD29

RSVD28

RSVD31

RSVD30

RSVD52

RSVD51

RSVD_NCTF10

RSVD_NCTF9

RSVD_NCTF8

RSVD_NCTF7

RSVD_NCTF6

RSVD_NCTF13

RSVD_NCTF12

RSVD_NCTF11

RSVD_NCTF5

RSVD_NCTF3

RSVD_NCTF1

RSVD40

RSVD39

RSVD_NCTF2

RSVD38

RSVD35

RSVD34

CFG[17]

CFG[16]

CFG[15]

CFG[14]

CFG[13]

CFG[12]

CFG[11]

CFG[10]

CFG[9]

CFG[8]

CFG[7]

CFG[6]

CFG[5]

CFG[4]

CFG[3]

CFG[2]

CFG[1]

CFG[0]

VSS

VSS285

VSS284

VSS283

VSS282

VSS281

VSS280

VSS279

VSS278

VSS277

VSS276

VSS275

VSS274

VSS273

VSS272

VSS271

VSS270

VSS269

VSS268

VSS267

VSS266

VSS265

VSS264

VSS263

VSS262

VSS261

VSS260

VSS259

VSS258

VSS257

VSS256

VSS255

VSS254

VSS253

VSS252

VSS251

VSS250

VSS249

VSS248

VSS247

VSS246

VSS245

VSS244

VSS243

VSS242

VSS241

VSS240

VSS239

VSS238

VSS237

VSS236

VSS235

VSS234

VSS233

VSS232

VSS231

VSS230

VSS229

VSS228

VSS227

VSS226

VSS225

VSS224

VSS223

VSS222

VSS221

VSS220

VSS219

VSS218

VSS217

VSS216

VSS215

VSS214

VSS213

VSS212

VSS211

VSS210

VSS209

VSS208

VSS207

VSS206

VSS205

VSS204

VSS203

VSS202

VSS201

VSS200

VSS199

VSS198

VSS197

VSS196

VSS195

VSS194

VSS193

VSS192

VSS191

VSS190

VSS189

VSS188

VSS187

VSS186

VSS185

VSS184

VSS183

VSS182

VSS181

VSS180

VSS179

VSS178

VSS177

VSS176

VSS175

VSS174

VSS173

VSS172

VSS171

VSS170

VSS169

VSS168

VSS167

VSS166

VSS165

VSS164

VSS163

VSS162

VSS161

ININININ

ININ

VSS

VSS160

VSS159

VSS158

VSS157

VSS156

VSS155

VSS154

VSS153

VSS152

VSS151

VSS150

VSS149

VSS148

VSS147

VSS146

VSS145

VSS144

VSS143

VSS142

VSS141

VSS140

VSS139

VSS138

VSS137

VSS136

VSS135

VSS134

VSS133

VSS132

VSS131

VSS130

VSS129

VSS128

VSS127

VSS126

VSS125

VSS124

VSS123

VSS122

VSS121

VSS120

VSS119

VSS118

VSS117

VSS116

VSS115

VSS114

VSS113

VSS112

VSS111

VSS110

VSS109

VSS108

VSS107

VSS106

VSS105

VSS104

VSS103

VSS102

VSS101

VSS100

VSS99

VSS98

VSS96

VSS95

VSS94

VSS93

VSS92

VSS91

VSS90

VSS89

VSS88

VSS87

VSS86

VSS85

VSS84

VSS83

VSS82

VSS81

VSS80

VSS79

VSS78

VSS77

VSS76

VSS75

VSS74

VSS73

VSS72

VSS71

VSS70

VSS69

VSS68

VSS67

VSS66

VSS65

VSS64

VSS63

VSS62

VSS61

VSS60

VSS59

VSS58

VSS57

VSS56

VSS55

VSS54

VSS53

VSS52

VSS51

VSS50

VSS49

VSS48

VSS47

VSS46

VSS45

VSS44

VSS43

VSS42

VSS41

VSS40

VSS39

VSS38

VSS37

VSS36

VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19

VSS18

VSS17

VSS16

VSS15

VSS14

VSS13

VSS12

VSS11

VSS10

VSS9

VSS8

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

PN: 6019B0843501

FAN CONN

PN: 6012A0081607

6727

AX11310A24893-0 MTR

LV1.1_Lauren


21

C66

2

561

3 42

U33

21

R3

21

R706

21

R533

21

R535

21

R534

21

C577

21

C578

21

R474

21

C583

G2G1

4321

CN17

40 54 56

40

40

P3V3S

P3V3S

P3V3S

P3V3S

P5V0S

THRMTRIP#

TACH0CPUFAN1_ON

4.7UF_6.3V_3

FAN

CSA3

0.01UF_50V_2

10K_5%_210K_5%_2

2.2uF_6.3V_3

100_5%_2

ACES_50273_0047N_001_4P

TI_TMP302BDRLR_SOT_6P

4.7K_5%_2

100PF_50V_2_DY

10K_5%_2

10K_5%_2_DY

DOC.NUMBER

DATE

SIZE CODE

8

8 7

7 6

6 5

5 4

3 2 1

DD

CC

B

AA

4

1

ofSHEET

TITLE

CHANGE by

23

INVENTEC

REV

B

OUTIN G

G

4

3

2

1

VS

TRIPSET1TRIPSET0

OUT# HYSTSET

GND

OUT

SI2 1230

IF SA0_DIM0=0 , SA1_DIM0=0SO-DIMMA SPD ADDRESS IS 0XA0SO-DIMMA TS ADDRESS IS 0X30IF SA0_DIM0=1 , SA1_DIM0=0SO-DIMMA SPD ADDRESS IS 0XA2

DDR3 SOCKET (RV_800) PN: 6026B0221101

SB OPEN

SO-DIMMA TS ADDRESS IS 0X32

(1A)

(4.32A)

NOTE:

DDR3 SO-DIMM 0

AX11310A24893-0 MTR

6728

LV1.1_Lauren


21

C86

21

C63

21R115

21R95

21

R11

42

1R

113

21

R92

21

R91

21

R181

21R94

21

R85

21

R81

21

R87

21

C78

21

C66

21

C49

21

C44

21

C83

21

C65

21

C68

21

C75

21

C77

21

C60

21

C88

21

C62

21

C87

21

C72

204203

25201914

196195190

13

189185184179178173172168167162

9

161156155151150145144139138134

8

13312812772716665616055

3

54494844

433837323126

2

1126

199

9994938887828176

124123118117112111106105100

75

30

12512277

G2G1

198

CN15

113

200202201197

121114

110

120116

18817115413764472912

18616915213562452710

232118

194192182180

16

193191183181176174166164177175

6

165163160158148146159157149147

4

1421401321301431411311297068

17

58566967595752504240

15

53514139363424223533

75

18717015313663462811

7473

104102103101

115

79108109

8589869091929596

7880

1198384

107

9798

CN15

24

28

28

2129

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

2424

24

24

24

24

24

24

24

24

24

24

24

24

lv1.1 lauren all 0103 1930 -...

Documents