LT3800

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TYPICAL APPLICATIO

U

APPLICATIO SU

FEATURES Wide 4V to 60V Input Voltage Range Output Voltages up to 36V Adaptive Nonoverlap Circuitry Prevents Switch

Shoot-Through Reverse Inductor Current Inhibit for Discontinuous

Operation Improves Efficiency with Light Loads Output Slew Rate Controlled Soft-Start with

Auto-Reset 100µA No Load Quiescent Current Low 10µA Current Shutdown 1% Regulation Accuracy 200kHz Operating Frequency Standard Gate N-Channel Power MOSFETs Current Limit Unaffected by Duty Cycle Reverse Overcurrent Protection 16-Lead Thermally Enhanced TSSOP Package

High-Voltage SynchronousCurrent Mode Step-Down

Controller

The LT®3800 is a 200kHz fixed frequency high voltagesynchronous current mode step-down switching regula-tor controller. The IC drives standard gate N-channel powerMOSFETs and can operate with input voltages from 4V to60V. An onboard regulator provides IC power directly fromVIN and provides for output-derived power to minimize VINquiescent current. MOSFET drivers employ an internaldynamic bootstrap feature, maximizing gate-source “ON”voltages during normal operation for improved operatingefficiencies. The LT3800 incorporates Burst Mode® opera-tion, which reduces no load quiescent current to under100µA. Light load efficiencies are also improved througha reverse inductor current inhibit, allowing the controllerto support discontinuous operation. Both Burst Modeoperation and the reverse-current inhibit features can bedisabled if desired. The LT3800 incorporates a program-mable soft-start that directly controls the voltage slew rateof the converter output for reduced startup surge currentsand overshoot errors. The LT3800 is available in a 16-leadthermally enhanced TSSOP package.

DESCRIPTIO

U

12V and 42V Automotive and Heavy Equipment 48V Telecom Power Supplies Avionics and Industrial Control Systems Distributed Power Converters

12V 75W DC/DC Converter with Reverse Current Inhibit and Input UVLO

Efficiency and Power Loss

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.Burst Mode is a registered trademark of Linear Technology Corporation.All other trademarks are the property of their respective owners.Protected by U.S. Patents, including 5481178, 6611131, 6304066, 6498466, 6580258.

VIN

SHDN

CSS

BURST_EN

VFB

VC

SENSE–

BOOST

TG

SW

VCC

BG

PGND

SENSE+

LT3800

SGND

1.5nF 200k

100pF

680pF

174k1%20k

1%

82.5k

1M82.5k

0.015Ω

BAS19

1N4148

1µF

1µF

1µF×3

56µF×2

+

10µF 270µF+

Si7850DP

Si7370DP B160

15µH

VIN20V TO 55V

VOUT12V AT 75W

3800 TA01a

ILOAD (A)

EFFI

CIEN

CY (%

)

POWER LOSS (W

)

100

95

90

3800 TA01b

70

75

85

80

6

5

4

0

1

3

2

100.1 1

VIN = 24V

LOSS (48V)

VIN = 48V

VIN = 60V

VIN = 36V

LT3800

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FE PACKAGE16-LEAD PLASTIC TSSOP

1

2

3

4

5

6

7

8

TOP VIEW

16

15

14

13

12

11

10

9

VIN

NC

SHDN

CSS

BURST_EN

VFB

VC

SENSE–

BOOST

TG

SW

NC

VCC

BG

PGND

SENSE+

17

Supply VoltagesInput Supply Pin (VIN) .............................. –0.3V to 65VBoosted Supply Pin (BOOST) ................... –0.3V to 80VBoosted Supply Voltage (BOOST – SW) .. –0.3V to 24VBoosted Supply Reference Pin (SW) ........... –2V to 65VLocal Supply Pin (VCC) ............................. –0.3V to 24VInput VoltagesSENSE+, SENSE– ...................................... –0.3V to 40VSENSE+ – SENSE– ......................................... –1V to 1VBURST_EN Pin ......................................... –0.3V to 24VOther Inputs (SHDN, CSS, VFB, VC) .......... –0.3V to 5.0VInput CurrentsSHDN, CSS ............................................... –1mA to 1mAMaximum TemperaturesOperating Junction Temperature Range (Note 2)

LT3800E (Note 3) ............................. –40°C to 125°CLT3800I ............................................ –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°CLead Temperature (Soldering, 10 sec)................. 300°C

TJMAX = 125°C, θJA = 40°C/W, θJC = 10°C/WEXPOSED PAD (PIN 17) IS SGND

MUST BE SOLDERED TO PCB

ABSOLUTE AXI U RATI GS

W WW U

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Operating Voltage Range (Note 4) 4 60 VMinimum Start Voltage 7.5 VUVLO Threshold (Falling) 3.65 3.80 3.95 VUVLO Hysteresis 670 mV

IVIN VIN Supply Current VCC > 9V 20 µAVIN Burst Mode Current VBURST_EN = 0V, VFB = 1.35V 20 µAVIN Shutdown Current VSHDN = 0V 8 15 µA

VBOOST Operating Voltage 75 VOperating Voltage Range (Note 5) VBOOST – VSW 20 VUVLO Threshold (Rising) VBOOST – VSW 5 VUVLO Hysteresis VBOOST – VSW 0.4 V

PI CO FIGURATIO

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ORDER I FOR ATIOU UW

Consult LTC Marketing for parts specified with wider operating temperature ranges.Consult LTC Marketing for information on nonstandard lead based finish parts.For more information on lead free part marking, go to: http://www.linear.com/leadfree/For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGELT3800EFE#PBF LT3800EFE#TRPBF 3800EFE 16-Lead Plastic TSSOP –40°C to 125°CLT3800IFE#PBF LT3800IFE#TRPBF 3800IFE 16-Lead Plastic TSSOP –40°C to 125°C

(Note 1)

LT3800

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IBOOST BOOST Supply Current (Note 6) 1.4 mABOOST Burst Mode Current VBURST_EN = 0V 0.1 µABOOST Shutdown Current VSHDN = 0V 0.1 µA

VCC Operating Voltage (Note 5) 20 VOutput Voltage 8.0 8.3 VUVLO Threshold (Rising) 6.25 VUVLO Hysteresis 500 mV

IVCC VCC Supply Current (Note 6) 3 3.6 mAVCC Burst Mode Current VBURST_EN = 0V 80 µAVCC Shutdown Current VSHDN = 0V 20 µAShort-Circuit Current –40 –120 mA

VSHDN Enable Threshold (Rising) 1.30 1.35 1.40 VThreshold Hysteresis 120 mV

VSENSE Common Mode Range 0 36Current Limit Sense Voltage VSENSE

+ – VSENSE– 140 150 175 mV

Reverse Protect Sense Voltage VSENSE+ – VSENSE

–, VBURST_EN = VCC –150 mVReverse Current Offset VBURST_EN = 0V or VBURST_EN = VFB 10 mV

ISENSE Input Current VSENSE(CM) = 0V 0.8 mA(ISENSE

+ + ISENSE–) VSENSE(CM) = 2.75V –20 µA

VSENSE(CM) > 4V –0.3 mA

fO Operating Frequency 190 200 210 kHz 175 220 kHz

VFB Error Amp Reference Voltage Measured at VFB Pin 1.224 1.231 1.238 V 1.215 1.245 V

IFB Feedback Input Current 25 nA

VFB(SS) Soft-Start Disable Voltage VFB Rising 1.185 VSoft-Start Disable Hysteresis 300 mV

ICSS Soft-Start Capacitor Control Current 2 µA

gm Error Amp Transconductance 275 350 400 µmhos

AV Error Amp DC Voltage Gain 62 dB

VC Error Amp Output Range Zero Current to Current Limit 1.2 V

IVC Error Amp Sink/Source Current ±30 µA

VTG,BG Gate Drive Output On Voltage (Note 7) 9.8 VGate Drive Output Off Voltage 0.1 V

tTG,BG Gate Drive Rise/Fall Time 10% to 90% or 90% to 10% 50 ns

tTG(OFF) Minimum Off Time 450 ns

tTG(ON) Minimum On Time 300 500 ns

tNOL Gate Drive Nonoverlap Time TG Fall to BG Rise 200 nsBG Fall to TG Rise 150 ns

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted.

LT3800

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TYPICAL PERFOR A CE CHARACTERISTICS

UW

ICC Current Limit vs Temperature

Shutdown Threshold (Rising)vs Temperature VCC vs Temperature

Shutdown Threshold (Falling)vs Temperature

VCC vs ICC(LOAD) VCC vs VIN

TEMPERATURE (°C)–50 –25

1.37

1.36

1.35

1.34

1.33100

3800 G01

0 50 12525 75

SHUT

DOW

N TH

RESH

OLD,

RIS

ING

(V)

–50 –25 1000 50 12525 75TEMPERATURE (°C)

1.240

1.235

1.230

1.225

1.220

3800 G02

SHUT

DOW

N TH

RESH

OLD,

FAL

LING

(V)

TEMPERATURE (°C)–50 –25

V CC

(V)

8.0

8.1

7.8

7.9

125

3800 G03

0 5025 75 100

ICC = 0mA

ICC = 20mA

ICC(LOAD) (mA)0

V CC

(V)

40

3800 G04

10 20 30

8.05

8.00

7.95

7.90

7.855 15 25 35

TA = 25°C

VIN (V)4

V CC

(V)

8

7

6

5

4

37 9 12

3800 G05

5 6 8 10 11

ICC = 20mATA = 25°C

–50 –25 1000 50 12525 75TEMPERATURE (°C)

200

175

150

125

100

75

50

3800 G06

I CC

CURR

ENT

LIM

IT (m

A)

Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition for extended periods may affect devicereliability and lifetime.Note 2: This IC includes overtemperature protection that is intended toprotect the device during momentary overload conditions. Junctiontemperature will exceed 125°C when overtemperature protection is active.Continuous operation above the specified maximum operating junctiontemperature may impair device reliability.Note 3: The LT3800E is guaranteed to meet performance specifications from0°C to 125°C junction temperature. Specifications over the –40°C to 125°Coperating junction temperature range are assured by design, characterizationand correlation with statistical process controls. The LT3800I is guaranteedover the full –40°C to 125°C operating junction temperature range.

Note 4: VIN voltages below the start-up threshold (7.5V) are onlysupported when VCC is externally driven above 6.5V.Note 5: Operating range dictated by MOSFET absolute maximum gate-source voltage ratings.Note 6: Supply current specification does not include switch drivecurrents. Actual supply currents will be higher.Note 7: DC measurement of gate drive output “ON” voltage is typically8.6V. Internal dynamic bootstrap operation yields typical gate “ON”voltages of 9.8V during standard switching operation. Standard operationgate “ON” voltage is not tested but guaranteed by design.

ELECTRICAL CHARACTERISTICS

LT3800

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Operating Frequencyvs Temperature

TYPICAL PERFOR A CE CHARACTERISTICS

UW

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PI FU CTIO SVIN (Pin 1): Converter Input Supply.

NC (Pin 2): No Connection.

SHDN (Pin 3): Precision Shutdown Pin. Enable thresholdis 1.35V (rising) with 120mV of input hysteresis. When inshutdown mode, all internal IC functions are disabled. Theprecision threshold allows use of the SHDN pin to incor-porate UVLO functions. If the SHDN pin is pulled below0.7V, the IC enters a low current shutdown mode withIVIN < 10µA. In low-current shutdown, the IC will sink 20µAfrom the VCC pin until that local supply has collapsed.Typical pin input bias current is <10nA and the pin isinternally clamped to 6V.

CSS (Pin 4): Soft-Start AC Coupling Capacitor Input.Connect capacitor (CSS) in series with a 200k resistor frompin to converter output (VOUT). Controls converter start-up output voltage slew rate (∆VOUT/∆t). Slew rate corre-sponds to 2µA average current through the soft-startcoupling capacitor. The capacitor value for a desiredoutput startup slew rate follows the relation:

CSS = 2µA/(∆VOUT/∆t)

Shorting this pin to SGND disables the soft-start function

BURST_EN (Pin 5): Burst Mode Operation Enable Pin.This pin also controls reverse-inhibit mode of operation.When the pin voltage is below 0.5V, Burst Mode operation

Error Amp Referencevs TemperatureI(SENSE

+ + SENSE

–) vs VSENSE(CM)

VSENSE(CM) (V)0 0.5 1.5 2.5 3.5 4.5

I (SEN

SE+ +

SEN

SE– ) (

µA)

800

600

400

200

0

–200

–4001.0 2.0 3.0 4.0

3800 G09

5.0

TA = 25°C

TEMPERATURE (°C)3800 G10

–50

220

210

200

190

180–25

OPER

ATIN

G FR

EQUE

NCY

(kHz

)

1000 50 12525 75 –50 –25 1000 50 12525 75TEMPERATURE (°C)

ERRO

R AM

P RE

FERE

NCE

(V)

1.232

1.231

1.230

1.229

1.228

1.227

3800 G11

VCC UVLO Threshold (Rising)vs Temperature

Error Amp Transconductancevs Temperature

TEMPERATURE (°C)–50 –25 100

3800 G07

0 50 12525 75

6.30

6.25

6.20

6.15

V CC

UVLO

THR

ESHO

LD, R

ISIN

G (V

)

ICC vs VCC (SHDN = 0V)

VCC (V)0

I CC

(µA)

15

20

25

16

3800 G12

10

5

02 4 6 8 10 12 14 18 20

TA = 25°C

TEMPERATURE (°C)–50 –25 1000 50 12525 75

380

360

340

320

3800 G08

ERRO

R AM

P TR

ANSC

ONDU

CTAN

CE (µ

mho

)

LT3800

63800fb

and reverse-current inhibit functions are enabled. Whenthe pin voltage is above 0.5V, Burst Mode operation isdisabled, but reverse-current inhibit operation is main-tained. DC/DC converters operating with reverse-currentinhibit operation (BURST_EN = VFB) have a 1mA minimumload requirement. Reverse-current inhibit is disabled whenthe pin voltage is above 2.5V. This pin is typically shortedto ground to enable Burst Mode operation and reverse-current inhibit, shorted to VFB to disable Burst Modeoperation while enabling reverse-current inhibit, and con-nected to VCC pin to disable both functions. See Applica-tions Information section.

VFB (Pin 6): Error Amplifier Inverting Input. Thenoninverting input of the error amplifier is connected to aninternal 1.231V reference. Desired converter output volt-age (VOUT) is programmed by connecting a resistivedivider from the converter output to the VFB pin. Values forthe resistor connected from VOUT to VFB (R2) and theresistor connected from VFB to ground (R1) can be calcu-lated via the following relationship:

R RVOUT2 11 231

1= ⎛⎝⎜

⎞⎠⎟

•.

–

The VFB pin input bias current is 25nA, so use of extremelyhigh value feedback resistors could cause a converteroutput that is slightly higher than expected. Bias currenterror at the output can be estimated as:

∆VOUT(BIAS) = 25nA • R2

VC (Pin 7): Error Amplifier Output. The voltage on the VCpin corresponds to the maximum (peak) switch currentper oscillator cycle. The error amplifier is typically config-ured as an integrator by connecting an RC network fromthis pin to ground. This network creates the dominant polefor the converter voltage regulation feedback loop. Spe-cific integrator characteristics can be configured to opti-mize transient response. Connecting a 100pF or greaterhigh frequency bypass capacitor from this pin to groundis also recommended. When Burst Mode operation isenabled (see Pin 5 description), an internal low impedance

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PI FU CTIO Sclamp on the VC pin is set at 100mV below the burstthreshold, which limits the negative excursion of the pinvoltage. Therefore, this pin cannot be pulled low with alow-impedance source. If the VC pin must be externallymanipulated, do so through a 1kΩ series resistance.

SENSE– (Pin 8): Negative Input for Current Sense Ampli-fier. Sensed inductor current limit set at ±150mV acrossSENSE inputs.

SENSE+ (Pin 9): Positive Input for Current Sense Ampli-fier. Sensed inductor current limit set at ±150mV acrossSENSE inputs.

PGND (Pin 10): High Current Ground Reference for Syn-chronous Switch. Current path from pin to negative termi-nal of VCC decoupling capacitor must not corrupt SGND.

BG (Pin 11): Synchronous Switch Gate Drive Output.

VCC (Pin 12): Internal Regulator Output. Most IC func-tions are powered from this pin. Driving this pin from anexternal source reduces VIN pin current to 20µA. This pinis decoupled with a low ESR 1µF capacitor to PGND.In shutdown mode, this pin sinks 20µA until the pinvoltage is discharged to 0V. See Typical PerformanceCharacteristics.

NC (Pin 13): No Connection.

SW (Pin 14): Reference for VBOOST Supply and HighCurrent Return for Bootstrapped Switch.

TG (Pin 15): Bootstrapped Switch Gate Drive Output.

BOOST (Pin 16): Bootstrapped Supply – Maximum Oper-ating Voltage (Ground Referred) to 75V. This pin isdecoupled with a low ESR 1µF capacitor to pin SW. Thevoltage on the decoupling capacitor is refreshed througha rectifier from either VCC or an external source.

Exposed Package Backside (SGND) (Pin 17): Low NoiseGround Reference. SGND connection is made through theexposed lead frame on back of TSSOP package whichmust be soldered to the PCB ground.

LT3800

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FU CTIO AL DIAGRA

UU W

– +

– +

–

+

–

+

–

+

VINUVLO(<4V)

BSTUVLO

8VREG

FEEDBACKREFERENCE

–

+1.231V

3.8VREG

INTERNALSUPPLY RAIL

116

15

14

12

10

9

17

3

5

7

4

6

VINVCC

UVLO(<6V)

SHDN

DRIVECONTROL

DRIVECONTROL

NOLSWITCHLOGIC

DRIVECONTROL

BURST_EN

VC

CSS

SENSE–

VFB

–

+

1.185V

1V

0.5VERRORAMP

2µA

Burst ModeOPERATION

8

SOFT-STARTDISABLE/BURST

ENABLE

R

SQ

OSCILLATOR

SLOPE COMPGENERATOR

BOOST

TG

SW

VCC

11 BG

PGND

SENSE+

GND

3800 FD

BOOSTEDSWITCHDRIVER

CURRENTSENSE

COMPARATOR

gm– +

R

S

Q

– +

160mV

SYNCHRONOUSSWITCH DRIVER

REVERSECURRENTINHIBIT

10mV

–

+

LT3800

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Overview

The LT3800 is a high input voltage range step-downsynchronous DC/DC converter controller IC that uses a200kHz constant frequency, current mode architecturewith external N-channel MOSFET switches.

The LT3800 has provisions for high efficiency, low loadoperation for battery-powered applications. Burst Modeoperation reduces total average input quiescent currentsto 100µA during no load conditions. A low current shutdownmode can also be activated, reducing quiescent current to<10µA. Burst Mode operation can be disabled if desired.

The LT3800 also employs a reverse-current inhibit fea-ture, allowing increased efficiencies during light loadsthrough nonsynchronous operation. This feature disablesthe synchronous switch if inductor current approacheszero. If full time synchronous operation is desired, thisfeature can be disabled.

Much of the LT3800’s internal circuitry is biased from aninternal linear regulator. The output of this regulator is theVCC pin, allowing bypassing of the internal regulator. Theassociated internal circuitry can be powered from theoutput of the converter, increasing overall converter effi-ciency. Using externally derived power also eliminates theIC’s power dissipation associated with the internal VIN toVCC regulator.

Theory of Operation (See Block Diagram)

The LT3800 senses converter output voltage via the VFBpin. The difference between the voltage on this pin and aninternal 1.231V reference is amplified to generate an errorvoltage on the VC pin which is, in turn, used as a thresholdfor the current sense comparator.

During normal operation, the LT3800 internal oscillatorruns at 200kHz. At the beginning of each oscillator cycle,the switch drive is enabled. The switch drive stays enableduntil the sensed switch current exceeds the VC derivedthreshold for the current sense comparator and, in turn,disables the switch driver. If the current comparator

APPLICATIO S I FOR ATIO

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threshold is not obtained for the entire oscillator cycle, theswitch driver is disabled at the end of the cycle for 450ns.This minimum off-time mode of operation assures regen-eration of the BOOST bootstrapped supply.

Power Requirements

The LT3800 is biased using a local linear regulator togenerate internal operational voltages from the VIN pin.Virtually all of the circuitry in the LT3800 is biased via aninternal linear regulator output (VCC). This pin is decoupledwith a low ESR 1µF capacitor to PGND.

The VCC regulator generates an 8V output provided thereis ample voltage on the VIN pin. The VCC regulator hasapproximately 1V of dropout, and will follow the VIN pinwith voltages below the dropout threshold.

The LT3800 has a start-up requirement of VIN > 7.5V. Thisassures that the onboard regulator has ample headroomto bring the VCC pin above its UVLO threshold. The VCCregulator can only source current, so forcing the VCC pinabove its 8V regulated voltage allows use of externallyderived power for the IC, minimizing power dissipation inthe IC. Using the onboard regulator for start-up, thenderiving power for VCC from the converter output maxi-mizes conversion efficiencies and is common practice. IfVCC is maintained above 6.5V using an external source, theLT3800 can continue to operate with VIN as low as 4V.

The LT3800 operates with 3mA quiescent current from theVCC supply. This current is a fraction of the actual VCCquiescent currents during normal operation. Additionalcurrent is produced from the MOSFET switching currentsfor both the boosted and synchronous switches and aretypically derived from the VCC supply.

Because the LT3800 uses a linear regulator to generateVCC, power dissipation can become a concern with highVIN voltages. Gate drive currents are typically in the rangeof 5mA to 15mA per MOSFET, so gate drive currents cancreate substantial power dissipation. It is advisable toderive VCC and VBOOST power from an external sourcewhenever possible.

LT3800

93800fb

The onboard VCC regulator will provide gate drive power forstart-up under all conditions with total MOSFET gate chargeloads up to 180nC. The regulator can operate the LT3800continuously, provided the VIN voltage and/or MOSFET gatecharge currents do not create excessive power dissipationin the IC. Safe operating conditions for continuous regu-lator use are shown in Figure 1. In applications where theseconditions are exceeded, VCC must be derived from anexternal source after start-up.

APPLICATIO S I FOR ATIO

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Charge Pump Doubler

TOTAL FET GATE CHARGE (nC)0

10

V IN

(V)

20

30

40

50

60

70

50 100 150 200

3800 F01

SAFEOPERATINGCONDITIONS

Figure 1. VCC Regulator Continuous Operating Conditions

VOUT

1µF

B0520 B0520

1µF

Si1555DL

LT3800

VCC

BG

VOUT

1µF

B0520

B0520

1µF

1µF

Si1555DLSi1555DLLT3800

VCC

BG

B0520

3800 AI01

TG

VOUT

3800 AI04

VCC

SW

BG

N

•

•LT3800

Inductor Auxiliary Winding

Charge Pump Tripler

In LT3800 converter applications with output voltages inthe 9V to 20V range, back-feeding VCC and VBOOST fromthe converter output is trivial, accomplished by connect-ing diodes from the output to these supply pins. Derivingthese supplies from output voltages greater than 20V willrequire additional regulation to reduce the feedback volt-age. Outputs lower than 9V will require step-up techniquesto increase the feedback voltage to something greater thanthe 8V VCC regulated output. Low power boost switchersare sometimes used to provide the step-up function, buta simple charge-pump can perform this function in manyinstances.

LT3800

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Burst Mode

The LT3800 employs low current Burst Mode functionalityto maximize efficiency during no load and low load condi-tions. Burst Mode operation is enabled by shorting theBURST_EN pin to SGND. Burst Mode operation can bedisabled by shorting BURST_EN to either VFB or VCC.

When the required switch current, sensed via the VC pinvoltage, is below 15% of maximum, the Burst Modeoperation is employed and that level of sense current islatched onto the IC control path. If the output load requiresless than this latched current level, the converter willoverdrive the output slightly during each switch cycle.This overdrive condition is sensed internally and forcesthe voltage on the VC pin to continue to drop. When thevoltage on VC drops 150mV below the 15% load level,switching is disabled and the LT3800 shuts down most ofits internal circuitry, reducing total quiescent current to100µA. When the converter output begins to fall, the VC pinvoltage begins to climb. When the voltage on the VC pinclimbs back to the 15% load level, the IC returns to normaloperation and switching resumes. An internal clamp onthe VC pin is set at 100mV below the switch disablethreshold, which limits the negative excursion of the pinvoltage, minimizing the converter output ripple duringBurst Mode operation.

During Burst Mode operation, VIN pin current is 20µA andVCC current is reduced to 80µA. If no external drive isprovided for VCC, all VCC bias currents originate from theVIN pin, giving a total VIN current of 100µA. Burst currentcan be reduced further when VCC is driven using an outputderived source, as the VCC component of VIN current isthen reduced by the converter buck ratio.

Reverse-Current Inhibit

The LT3800 contains a reverse-current inhibit feature tomaximize efficiency during light load conditions. Thismode of operation allows discontinuous operation, and issometimes referred to as “pulse-skipping” mode. Refer toFigure 2.

This feature is enabled with Burst Mode operation, and canalso be enabled while Burst Mode operation is disabled byshorting the BURST_EN pin to VFB.

When reverse-current inhibit is enabled, the LT3800 senseamplifier detects inductor currents approaching zero anddisables the synchronous switch for the remainder of theswitch cycle. If the inductor current is allowed to gonegative before the synchronous switch is disabled, theswitch node could inductively kick positive with a highdv/dt. The LT3800 prevents this by incorporating a 10mVpositive offset at the sense inputs.

APPLICATIO S I FOR ATIO

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PULSE SKIP MODEIL IL

FORCED CONTINUOUS

DECREASINGLOAD

CURRENT

3800 F02

Figure 2. Inductor Current vs Mode

LT3800

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With the reverse-current inhibit feature enabled, an LT3800converter will operate much like a nonsynchronousconverter during light loads. Reverse-current inhibit re-duces resistive losses associated with inductor ripplecurrents, which improves operating efficiencies duringlight-load conditions.

An LT3800 DC/DC converter that is operating in reverse-inhibit mode has a minimum load requirement of 1mA(BURST_EN = VFB). Since most applications use output-generated power for the LT3800, this requirement is metby the bias currents of the IC, however, for applicationsthat do not derive power from the output, this require-ment is easily accomplished by using a 1.2k resistorconnected from VFB to ground as one of the converteroutput voltage programming resistors (R1). There are nominimum load restrictions when in Burst Mode operation(BURST_EN < 0.5V) or continuous conduction mode(BURST_EN > 2.5V).

Soft-Start

The LT3800 incorporates a programmable soft-start func-tion to control start-up surge currents, limit output over-shoot and for use in supply sequencing. The soft-startfunction directly monitors and controls output voltageslew rate during converter start-up.

As the output voltage of the converter rises, the soft-startcircuit monitors δV/δt current through a coupling capaci-tor and adjusts the voltage on the VC pin to maintain anaverage value of 2µA. The soft-start function forces theprogrammed slew rate while the converter output rises to95% regulation, which corresponds to 1.185V on the VFBpin. Once 95% regulation is achieved, the soft-start circuitis disabled. The soft-start circuit will re-enable when the VFBpin drops below 70% regulation, which corresponds to300mV of control hysteresis on the VFB pin, which allowsfor a controlled recovery from a ‘brown-out’ condition.

The desired soft-start rise time (tSS) is programmed viaa programming capacitor CSS1, using a value that

corresponds to 2µA average current during the soft-startinterval. This capacitor value follows the relation:

CE

SS162=

– • tV

SS

OUT

RSS is typically set to 200k for most applications.

APPLICATIO S I FOR ATIO

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CSSVOUT

CSS1 RSSA

3800 AI06

LT3800

Considerations for Low Voltage Output Applications

The LT3800 CSS pin biases to 220mV during the soft-startcycle, and this voltage is increased at network node “A” bythe 2µA signal current through RSS, so the output has toreach this value before the soft-start function is engaged.The value of this output soft-start start-up voltage offset(VOUT(SS)) follows the relation:

VOUT(SS) = 220mV + RSS • 2E–6

which is typically 0.64V for RSS = 200k.

In some low voltage output applications, it may be desir-able to reduce the value of this soft-start start-up voltageoffset. This is possible by reducing the value of RSS. Withreduced values of RSS, the signal component caused byvoltage ripple on the output must be minimized for propersoft-start operation.

Peak-to-peak output voltage ripple (∆VOUT) will be im-posed on node “A” through the capacitor CSS1. The valueof RSS can be set using the following equation:

RV

SSOUT= ∆

1.3E–6

It is important to use low ESR output capacitors forLT3800 voltage converter designs to minimize this ripplevoltage component. A design with an excessive ripplecomponent can be evidenced by observing the VC pinduring the start cycle.

LT3800

123800fb

The soft-start cycle should be evaluated to verify that thereduced RSS value allows operation without excessivemodulation of the VC pin before finalizing the design.

If the VC pin has an excessive ripple component during thesoft-start cycle, converter output ripple should be reducedor RSS increased. Reduction in converter output ripple istypically accomplished by increasing output capacitanceand/or reducing output capacitor ESR.

External Current Limit Foldback Circuit

An additional start-up voltage offset can occur during theperiod before the LT3800 soft-start circuit becomes ac-tive. Before the soft-start circuit throttles back the VC pinin response to the rising output voltage, current as high asthe peak programmed current limit (IMAX) can flow in theinductor. Switching will stop once the soft-start circuittakes hold and reduces the voltage on the VC pin, but theoutput voltage will continue to increase as the storedenergy in the inductor is transferred to the output capaci-tor. With IMAX flowing in the inductor, the resulting lead-ing-edge rise on VOUT due to energy stored in the inductorfollows the relationship:

∆ = ⎛⎝⎜

⎞⎠⎟

V IL

COUT MAXOUT

•/1 2

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Soft-Start Characteristic Showing Excessive Ripple Component Desirable Soft-Start Characteristic

Inductor current typically doesn’t reach IMAX in the fewcycles that occur before soft-start becomes active, but canwith high input voltages or small inductors, so the aboverelation is useful as a worst-case scenario.

This energy transfer increase in output voltage is typicallysmall, but for some low voltage applications with relativelysmall output capacitors, it can become significant. Thevoltage rise can be reduced by increasing output capaci-tance, which puts additional limitations on COUT for theselow voltage supplies. Another approach is to add anexternal current limit foldback circuit which reduces thevalue of IMAX during start-up.

An external current limit foldback circuit can be easilyincorporated into an LT3800 DC/DC converter applicationby placing a 1N4148 diode and a 47k resistor from theconverter output (VOUT) to the LT3800’s VC pin. This limitsthe peak current to 0.25 • IMAX when VOUT = 0V. A currentlimit foldback circuit also has the added advantage ofproviding a reduced output current in the DC/DC converterduring short-circuit fault conditions, so a foldback circuitmay be useful even if the soft-start function is disabled.

If the soft-start circuit is disabled by shorting the CSS pinto ground, the external current limit fold-back circuit mustbe modified by adding an additional diode and resistor.The 2-diode, 2-resistor network shown also provides0.25 • IMAX when VOUT = 0V.

VOUT

VOUT(SS)V(VC)

250µs/DIV3800 AI07

VOUT

VOUT(SS)V(VC)

250µs/DIV3800 AI08

LT3800

133800fb

Adaptive Nonoverlap (NOL) Output Stage

The FET driver output stages implement adaptivenonoverlap control. This feature maintains a constantdead time, preventing shoot-through switch currents,independent of the type, size or operating conditions of theexternal switch elements.

Each of the two switch drivers contains a NOL controlcircuit, which monitors the output gate drive signal of theother switch driver. The NOL control circuits interrupt the“turn on” command to their associated switch driver untilthe other switch gate is fully discharged.

Antislope Compensation

Most current mode switching controllers use slope com-pensation to prevent current mode instability. The LT3800is no exception. A slope-compensation circuit imposes anartificial ramp on the sensed current to increase the risingslope as duty cycle increases. Unfortunately, this addi-tional ramp corrupts the sensed current value, reducingthe achievable current limit value by the same amount asthe added ramp represents. As such, current limit istypically reduced as duty cycles increase. The LT3800contains circuitry to eliminate the current limit reductiontypically associated with slope compensation. As theslope-compensation ramp is added to the sensed current,a similar ramp is added to the current limit thresholdreference. The end result is that current limit is notcompromised, so a LT3800 converter can provide fullpower regardless of required duty cycle.

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Shutdown

The LT3800 SHDN pin uses a bandgap generated refer-ence threshold of 1.35V. This precision threshold allowsuse of the SHDN pin for both logic-level controlled appli-cations and analog monitoring applications such as powersupply sequencing.

The LT3800 operational status is primarily controlled by aUVLO circuit on the VCC regulator pin. When the IC isenabled via the SHDN pin, only the VCC regulator is en-abled. Switching remains disabled until the UVLO thresh-old is achieved at the VCC pin, when the remainder of theIC is enabled and switching commences.

Because an LT3800 controlled converter is a power trans-fer device, a voltage that is lower than expected on theinput supply could require currents that exceed the sourc-ing capabilities of that supply, causing the system to lockup in an undervoltage state. Input supply start-up protec-tion can be achieved by enabling the SHDN pin using aresistive divider from the VIN supply to ground. Setting thedivider output to 1.35V when that supply is at an adequatevoltage prevents an LT3800 converter from drawing largecurrents until the input supply is able to provide therequired power. 120mV of input hysteresis on the SHDNpin allows for almost 10% of input supply droop beforedisabling the converter.

VC

VOUT

1N4148

3800 AI09

47k

VC

VOUT

1N4148

1N4148

3800 AI10

39k27k

Current Limit Foldback Circuit forApplications That Use Soft-Start

Alternative Current Limit Foldback Circuit for Applications ThatHave Soft-Start Disabled

LT3800

143800fb

The UVLO voltage, VIN(UVLO), is set using the followingrelation:

R RV V

VA BIN UVLO= •

– ..

( ) 1 351 35

If additional hysteresis is desired for the enable function,an external positive feedback resistor can be used from theLT3800 regulator output.

The shutdown function can be disabled by connecting theSHDN pin to VIN through a large value pull-up resistor.This pin contains a low impedance clamp at 6V, so theSHDN pin will sink current from the pull-up resistor (RPU):

IV V

RSHDNIN

PU= – 6

Because this arrangement will pull the SHDN pin to the 6Vclamp voltage, it will violate the 5V absolute maximumvoltage rating of the pin. This is permitted, however, aslong as the absolute maximum input current rating of 1mAis not exceeded. Input SHDN pin currents of <100µA arerecommended; a 1MΩ or greater pull-up resistor is typi-cally used for this configuration.

Inductor Selection

The primary criterion for inductor value selection in LT3800applications is ripple current created in that inductor.Basic design considerations for ripple current are outputvoltage ripple, and the ability of the internal slope compen-sation waveform to prevent current mode instability. Oncethe value is determined, an inductor must also have asaturation current equal to or exceeding the maximumpeak current in the inductor.

Ripple current (∆IL) in an inductor for a given value (L) canbe approximated using the relation:

∆ = ⎛⎝⎜

⎞⎠⎟

IVV

Vf LL

OUT

IN

OUT

O1– •

•

The typical range of values for ∆I is 20% to 40% ofIOUT(MAX), where IOUT(MAX) is the maximum converteroutput load current. Ripple currents in this range typicallyyield a good design compromise between inductor perfor-mance versus inductor size and cost, and values in thisrange are generally a good starting point. A starting pointinductor value can thus be determined using the relation:

L V

VV

f IOUT

OUT

IN

O OUT MAX=

⎛⎝⎜

⎞⎠⎟

•–

• . • ( )

1

0 3

Use of smaller inductors increase output ripple currents,requiring more capacitance on the converter output. Also,with converter operation with duty cycles greater than50%, the slope compensation criterion, described later,must be met. Designing for smaller ripple currents re-quires larger inductor values, which can increase con-verter cost and/or footprint.

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Programming LT3800 VIN UVLO

3800 AI02

LT3800

VIN

RB

RA

3

17

SHDN

SGND

LT3800

153800fb

Some magnetics vendors specify a volt-second product intheir data sheet. If they do not, consult the vendor to makesure the specification is not being exceeded by yourdesign. The required volt-second product is calculated asfollows:

Voltf

VVO

OUT

IN- Second

VOUT≥ ⎛⎝⎜

⎞⎠⎟

• –1

Magnetics vendors specify either the saturation current,the RMS current, or both. When selecting an inductorbased on inductor saturation current, the peak currentthrough the inductor, IOUT(MAX) + (∆I/2), is used. Whenselecting an inductor based on RMS current the maximumload current, IOUT(MAX), is used.

The requirement for avoiding current mode instability iskeeping the rising slope of sensed inductor ripple current(S1) greater than the falling slope (S2). During continuous-current switcher operation, the rising slope of the currentwaveform in the switched inductor is less than the fallingslope when operating at duty cycles (DC) greater than 50%.To avoid the instability condition during this operation, afalse signal is added to the sensed current, increasing theperceived rising slope. To prevent current mode instabil-ity, the slope of this false signal (Sx) must be sufficient suchthat the sensed rising slope exceeds the falling slope, orS1 + Sx ≥ S2. This leads to the following relations:

Sx ≥ S2 (2DC – 1)/DC

where:

S2 ~ VOUT/L

Solving for L yields a relation for the minimum inductancethat will satisfy slope compensation requirements:

L VDC

DC SxMIN OUT= •–

•2 1

The LT3800 maximizes available dynamic range using aslope compensation generator that continuously increasesthe additional signal slope as duty cycle increases. Theslope compensation waveform is calibrated at an 80%

duty cycle, to generate an equivalent slope of at least1E5 • ILIMIT A/sec, where ILIMIT is the programmed con-verter current limit. Current limit is programmed by usinga sense resistor (RS) such that ILIMIT = 150mV/RS, so theequation for the minimum inductance to meet the currentmode instability criterion can be reduced to:

LMIN = (5E–5)(VOUT)(RS)

For example, with VOUT = 5V and RS = 20mΩ:

LMIN = (5E–5)(5)(0.02) = 5µH

After calculating the minimum inductance value, the volt-second product, the saturation current and the RMScurrent for your design, an off the shelf inductor can beselected from a magnetics vendor. A list of magneticsvendors can be found at http://www.linear.com/ezone/vlinks or by contacting the Linear Technology Applicationsdepartment.

Output Voltage Programming

Output voltage is programmed through a resistor feed-back network to VFB (Pin 6) on the LT3800. This pin is theinverting input of the error amplifier, which is internallyreferenced to 1.231V. The divider is ratioed to provide1.231V at the VFB pin when the output is at its desiredvalue. The output voltage is thus set following the relation:

R RVOUT2 11 231

1= ⎛⎝⎜

⎞⎠⎟

•.

–

when an external resistor divider is connected to theoutput as shown.

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Programming LT3800 Output Voltage

3800 AI03

LT3800

VOUT

R2

R1

6

17

VFB

SGND

LT3800

163800fb

Power MOSFET Selection

External N-channel MOSFET switches are used with theLT3800. The positive gate-source drive voltage of theLT3800 for both switches is roughly equivalent to the VCCsupply voltage, for use of standard threshold MOSFETs.

Selection criteria for the power MOSFETs include the “ON”resistance (RDS(ON)), total gate charge (QG), reverse transfercapacitance (CRSS), maximum drain-source voltage (VDSS)and maximum current.

The power FETs selected must have a maximum operatingVDSS exceeding the maximum VIN. VGS voltage maximummust exceed the VCC supply voltage.

Total gate charge (QG) is used to determine the FET gatedrive currents required. QG increases with applied gatevoltage, so the QG for the maximum applied gate voltagemust be used. A graph of QG vs. VGS is typically providedin MOSFET datasheets.

In a configuration where the LT3800 linear regulator isproviding VCC and VBOOST currents, the VCC 8V outputvoltage can be used to determine QG. Required drivecurrent for a given FET follows the simple relation:

IGATE = QG(8V) • fOQG(8V) is the total FET gate charge for VGS = 8V, and f0 =operating frequency. If these currents are externally de-rived by backdriving VCC, use the backfeed voltage todetermine QG. Be aware, however, that even in a backfeedconfiguration, the drive currents for both boosted andsynchronous FETs are still typically supplied by the LT3800internal VCC regulator during start-up. The LT3800 canstart using FETs with a combined QG(8V) up to 180nC.

Once voltage requirements have been determined, RDS(ON)can be selected based on allowable power dissipation andrequired output current.

In an LT3800 buck converter, the average inductor currentis equal to the DC load current. The average currentsthrough the main (bootstrapped) and synchronous(ground-referred) switches are:

IMAIN = (ILOAD)(DC)

ISYNC = (ILOAD)(1 – DC)

The RDS(ON) required for a given conduction loss can becalculated using the relation:

PLOSS = ISWITCH2 • RDS(ON)

In high voltage applications (VIN > 20V), the main switchis required to slew very large voltages. MOSFET transitionlosses are proportional to VIN

2 and can become thedominant power loss term in the main switch. This transi-tion loss takes the form:

PTR ≈ (k)(VIN)2(ISWITCH)(CRSS)(fO)

where k is a constant inversely related to the gate drivecurrent, approximated by k = 2 in LT3800 applications,and ISWITCH is the converter output current. The powerloss terms for the switches are thus:

PMAIN = (DC)(ISWITCH)2(1 + d)(RDS(ON)) +2(VIN)2(ISWITCH)(CRSS)(fO)

PSYNC = (1 – DC)(ISWITCH)2(1 + d)(RDS(ON))

The (1 + d) term in the above relations is the temperaturedependency of RDS(ON), typically given in the form of anormalized RDS(ON) vs Temperature curve in a MOSFETdata sheet.

The CRSS term is typically smaller for higher voltage FETs,and it is often advantageous to use a FET with a higher VDSrating to minimize transition losses at the expense ofadditional RDS(ON) losses.

In some applications, parasitic FET capacitances couplethe negative going switch node transient onto the bottomgate drive pin of the LT3800, causing a negative voltage inexcess of the Absolute Maximum Rating to be imposed onthat pin. Connection of a catch Schottky diode from thispin to ground will eliminate this effect. A 1A current ratingis typically sufficient for the diode.

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LT3800

173800fb

Input Capacitor Selection

The large currents typical of LT3800 applications requirespecial consideration for the converter input and outputsupply decoupling capacitors. Under normal steady statebuck operation, the source current of the main switchMOSFET is a square wave of duty cycle VOUT/VIN. Most ofthis current is provided by the input bypass capacitor. Toprevent large input voltage transients and avoid bypasscapacitor heating, a low ESR input capacitor sized for themaximum RMS current must be used. This maximumcapacitor RMS current follows the relation:

II V V V

VRMSMAX OUT IN OUT

IN=

( )( )–12

which peaks at a 50% duty cycle, when IRMS = IMAX/2.

The bulk capacitance is calculated based on an acceptablemaximum input ripple voltage, ∆VIN, which follows therelation:

C I

VV

V fIN BULK OUT MAX

OUT

IN

IN O( ) ( ) •

•=

∆

∆V is typically on the order of 100mV to 200mV. Alumi-num electrolytic capacitors are a good choice for highvoltage, bulk capacitance due to their high capacitance perunit area.

The capacitor voltage rating must be rated greater thanVIN(MAX). The combination of aluminum electrolytic ca-pacitors and ceramic capacitors is a common approach tomeeting supply input capacitor requirements. Multiplecapacitors are also commonly paralleled to meet size orheight requirements in a design.

Capacitor ripple current ratings are often based on only2000 hours (three months) lifetime; it is advisable toderate either the ESR or temperature rating of the capaci-tor for increased MTBF of the regulator.

Output Capacitor Selection

The output capacitor in a buck converter generally hasmuch less ripple current than the input capacitor. Peak-to-peak ripple current is equal to that in the inductor (∆IL),typically a fraction of the load current. COUT is selected toreduce output voltage ripple to a desirable value given anexpected output ripple current. Output ripple (∆VOUT) isapproximated by:

∆VOUT ≈ ∆IL(ESR + [(8)(fO) • COUT]–1)

where fO = operating frequency.

∆VOUT increases with input voltage, so the maximumoperating input voltage should be used for worst-casecalculations. Multiple capacitors are often paralleled tomeet ESR requirements. Typically, once the ESR require-ment is satisfied, the capacitance is adequate for filteringand has the required RMS current rating. An additionalceramic capacitor in parallel is commonly used to reducethe effect of parasitic inductance in the output capacitor,which reduces high frequency switching noise on theconverter output.

Increasing inductance is an option to reduce ESR require-ments. For extremely low ∆VOUT, an additional LC filterstage can be added to the output of the supply. Applica-tion Note 44 has information on sizing an additionaloutput LC filter.

Layout Considerations

The LT3800 is typically used in DC/DC converter designsthat involve substantial switching transients. The switchdrivers on the IC are designed to drive large capacitancesand, as such, generate significant transient currents them-selves. Careful consideration must be made regardingsupply bypass capacitor locations to avoid corrupting theground reference used by IC.

Typically, high current paths and transients from the inputsupply and any local drive supplies must be kept isolatedfrom SGND, to which sensitive circuits such as the erroramp reference and the current sense circuits are referred.

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LT3800

183800fb

Effective grounding can be achieved by considering switchcurrent in the ground plane, and the return current pathsof each respective bypass capacitor. The VIN bypassreturn, VCC bypass return, and the source of the synchro-nous FET carry PGND currents. SGND originates at thenegative terminal of the VOUT bypass capacitor, and is thesmall signal reference for the LT3800.

Don’t be tempted to run small traces to separate groundpaths. A good ground plane is important as always, butPGND referred bypass elements must be oriented suchthat transient currents in these return paths do notcorrupt the SGND reference.

During the dead-time between switch conduction, thebody diode of the synchronous FET conducts inductorcurrent. Commutating this diode requires a significantcharge contribution from the main switch. At the instantthe body diode commutates, a current discontinuity iscreated and parasitic inductance causes the switch nodeto fly up in response to this discontinuity. High currentsand excessive parasitic inductance can generate extremelyfast dV/dt rise times. This phenomenon can causeavalanche breakdown in the synchronous FET body di-ode, significant inductive overshoot on the switch node,and shoot-through currents via parasitic turn-on of thesynchronous FET. Layout practices and component ori-entations that minimize parasitic inductance on this nodeis critical for reducing these effects.

Ringing waveforms in a converter circuit can lead todevice failure, excessive EMI, or instability. In many cases,you can damp a ringing waveform with a series RCnetwork across the offending device. In LT3800 applica-tions, any ringing will typically occur on the switch node,which can usually be reduced by placing a snubber acrossthe synchronous FET. Use of a snubber network, however,should be considered a last resort. Effective layout prac-tices typically reduce ringing and overshoot, and willeliminate the need for such solutions.

Effective grounding techniques are critical for successfulDC/DC converter layouts. Orient power path components

such that current paths in the ground plane do not crossthrough signal ground areas. Signal ground refers to theExposed Pad on the backside of the LT3800 IC. SGND isreferenced to the (–) terminal of the VOUT decouplingcapacitor and is used as the converter voltage feedbackreference. Power ground currents are controlled on theLT3800 via the PGND pin, and this ground references thehigh current synchronous switch drive components, aswell as the local VCC supply. It is important to keep PGNDand SGND voltages consistent with each other, so sepa-rating these grounds with thin traces is not recommended.When the synchronous FET is turned on, gate drive surgecurrents return to the LT3800 PGND pin from the FETsource. The BOOST supply refresh surge currents alsoreturn through this same path. The synchronous FET mustbe oriented such that these PGND return currents do notcorrupt the SGND reference. Problems caused by thePGND return path are generally recognized during heavyload conditions, and are typically evidenced as multipleswitch pulses occurring during a single 5µs switch cycle.This behavior indicates that SGND is being corrupted andgrounding should be improved. SGND corruption canoften be eliminated, however, by adding a small capacitor(100pF-200pF) across the synchronous switch FET fromdrain to source.

The high di/dt loop formed by the switch MOSFETs and theinput capacitor (CIN) should have short wide traces tominimize high frequency noise and voltage stress frominductive ringing. Surface mount components are pre-ferred to reduce parasitic inductances from componentleads. Connect the drain of the main switch MOSFETdirectly to the (+) plate of CIN, and connect the source ofthe synchronous switch MOSFET directly to the (–) termi-nal of CIN. This capacitor provides the AC current to theswitch MOSFETs. Switch path currents can be controlledby orienting switch FETs, the switched inductor, and inputand output decoupling capacitors in close proximity toeach other.

Locate the VCC and BOOST decoupling capacitors in closeproximity to the IC. These capacitors carry the MOSFET

APPLICATIO S I FOR ATIO

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LT3800

193800fb

BOOST

VCC

SW

PGNDSGND

LT3800SGNDREFERRED

COMPONENTS

+

+ BG

TG

VOUT

3800 AI05

VIN

ISENSE

SW

Orientation of Components Isolates Power Path and PGND Currents,Preventing Corruption of SGND Reference

drivers’ high peak currents. Locate the small-signal compo-nents away from high frequency switching nodes (BOOST,SW, TG, VCC and BG). Small-signal nodes are oriented onthe left side of the LT3800, while high current switchingnodes are oriented on the right side of the IC to simplifylayout. This also helps prevent corruption of the SGNDreference.

Connect the VFB pin directly to the feedback resistors in-dependent of any other nodes, such as the SENSE– pin.The feedback resistors should be connected between the(+) and (–) terminals of the output capacitor (COUT).

Locate the feedback resistors in close proximity to theLT3800 to minimize the length of the high impedance VFBnode.

The SENSE– and SENSE+ traces should be routed to-gether and kept as short as possible.

The LT3800 packaging has been designed to efficientlyremove heat from the IC via the Exposed Pad on thebackside of the package. The Exposed Pad is soldered toa copper footprint on the PCB. This footprint should bemade as large as possible to reduce the thermal resistanceof the IC case to ambient air.

APPLICATIO S I FOR ATIO

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LT3800

203800fb

TYPICAL APPLICATIO S

U

6.5V-55V to 5V 10A DC/DC Converter with Charge Pump Doubler VCC Refresh and Current Limit Foldback

VIN

NC

SHDN

CSS

BURST_EN

VFB

VC

SENSE–

BOOST

TG

SW

NC

VCC

BG

PGND

SENSE+

LT3800

SGND

C71.5nF

R362k R5

47k

D21N4148

R4 75k

C9470pF

C10100pF

R2309k1%

R1100k1%

RA1M

RS0.01Ω

D1BAS19

C1 1µF16V X7R

C3 1µF16V X7R

C21µF100VX7R ×3

C856µF63V×2

+

C610µF6.3VX7R

C5220µF×2

+

M1Si7850DP×2

M2Si7370DP×2

M31/2 Si1555DL

M41/2 Si1555DL

DS3B160×2

DS1MBRO520L

C41µF

DS2 MBRO520L

L15.6µH

VIN6.5V TO 55V

VOUT5V AT 10A

3800 TA02a

C5: SANYO POSCAP 6TP220ML1: IHLP-5050FD-01

IOUT (A)0

70

EFFI

CIEN

CY (%

)POW

ER LOSS (W)

75

80

85

90

95

100

0

2

4

6

8

10

12

2 4 6 8

3800 TA02b

10

VIN = 13.8V

VIN = 55V

VIN = 24VVIN = 48V

POWER LOSSVIN = 48V

POWER LOSSVIN = 13.8V

Efficiency and Power Loss

LT3800

213800fb

TYPICAL APPLICATIO S

U

9V-38V to 3.3V 10A DC/DC Converter with Input UVLO and Burst Mode OperationNo Load I(VIN) = 100µA

Efficiency and Power Loss

VIN

NC

SHDN

CSS

BURST_EN

VFB

VC

SENSE–

BOOST

TG

SW

NC

VCC

BG

PGND

SENSE+

LT3800

SGND

C1 1nF

C3100pF

C2330pF

C10100pF

R2169k1%

R1100k1%

R4 39k

R382k

RA1MRB

187k

RS0.01Ω

D1MBR520

C5 1µF16V X7R

C4 1µF16V X7R

C94.7µF50VX7R ×3

C8100µF50V×2

+

C710µF6.3VX7R

C6470µF×2

+

M1Si7884DP

M2Si7884DP

DS1SS14×2

L13.3µH

VIN9V TO 38V

VOUT3.3V AT 10A

3800 TA03a

C6: SANYO POSCAP 4TPD470ML1: IHLP-5050FD-01

ILOAD (A)

78

84

82

80

92

90

88

86

0

3

2

1

7

6

5

4

3800 TA03b

EFFI

CIEN

CY (%

)POW

ER LOSS (W)

0.1 101

VIN = 13.8V

LT3800

223800fb

TYPICAL APPLICATIO S

U

VIN

NC

SHDN

CSS

BURST_EN

VFB

VC

SENSE–

BOOST

TG

SW

NC

VCC

BG

PGND

SENSE+

LT3800

SGND

C1 3.9nF

C9 1nF

C3100pF

C21nF

C647pF

R2154k1%

R149.9k1%

R547k

D21N4148

R4 51k

R327k

RA1M

RB 187k

RS0.02Ω

D1BAS19

C5 1µF10V X7R

C4 1µF10V X7R

C822µF×3

C7100µF×2

M1Si7884DP

M2Si7884DP

DS1SS14

L110µH

VIN9V TO 38V

VOUT5V AT 6A3800 TA05a

C7: TDK C4532X5R0J107MTC8: TDK C5750X7R1E226MTL1: IHLP-5050FD-01

9V-38V to 5V 6A DC/DC Converter with All Ceramic Capacitors, Input UVLO,Burst Mode Operation and Current Limit Foldback

Efficiency and Power Loss

ILOAD (A)

70

EFFI

CIEN

CY (%

)POW

ER LOSS (W)

80

85

95

100

0.001 0.1 1 10

3800 TA05b

600.01

90

75

65

0.80

1.60

2.00

2.80

3.20

0

2.40

1.20

0.40

VIN = 13.8V

LT3800

233800fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

FE Package16-Lead Plastic TSSOP (4.4mm)(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BC

PACKAGE DESCRIPTIO

U

FE16 (BC) TSSOP 0204

0.09 – 0.20(.0035 – .0079)

0° – 8°

0.25REF

0.50 – 0.75(.020 – .030)

4.30 – 4.50*(.169 – .177)

1 3 4 5 6 7 8

10 9

4.90 – 5.10*(.193 – .201)

16 1514 13 12 11

1.10(.0433)

MAX

0.05 – 0.15(.002 – .006)

0.65(.0256)

BSC

2.94(.116)

0.195 – 0.30(.0077 – .0118)

TYP

2RECOMMENDED SOLDER PAD LAYOUT

0.45 ±0.05

0.65 BSC

4.50 ±0.10

6.60 ±0.10

1.05 ±0.10

2.94(.116)

3.58(.141)

3.58(.141)

MILLIMETERS(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT

6.40(.252)BSC

LT3800

243800fb

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005

LT 1007 REV B • PRINTED IN USA

24V-48V to –12V 75W Inverting DC/DC Converter with VIN UVLO

RELATED PARTSPART NUMBER DESCRIPTION COMMENTSLTC1735 Synchronous Step-Down Controller 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 6V, IOUT ≤ 20ALTC1778 No RSENSE

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LTC3703-5 60V Synchronous Step-Down Controller Large 1Ω Gate Drivers, No RSENSE

LTC3727-1 High VOUT 2-Phase Dual Step-Down Controller 0.8V ≤ VOUT ≤ 14V, PLL: 250kHz to 550kHzLTC3728L 2-Phase, Dual Synchronous Step-Down Controller 550kHz, PLL: 250kHz to 550kHz, 4V ≤ VIN ≤ 36VNo RSENSE and ThinSOT are trademarks of Linear Technology Corporation.

VIN

NC

SHDN

CSS

BURST_EN

VFB

VC

SENSE–

BOOST

TG

SW

NC

VCC

BG

PGND

SENSE+

LT3800

SGND

C1 1nF R1 200k

C3470pF

R81M

R31M

R71M

R6130k

R439k

R520k1%

R2174k1%

C2 1µF16V X7R

C4100pF

C84.7µF16VX7R

C5270µF16VSPRAGUE SP

C7150pF100V

D21N4148D1

BAS19

C956µF63V×2

C101µF100VX7R×4

C61µF16VX7R

M1FDD3570

M2FDD3570

L1: COEV MGPWL-00099

VIN24V TO 48V

VOUT–12V 75W

RS0.01Ω

L115µH

DS1B180

2N3906

3800 TA04a

+

+

ILOAD (A)0.1

40

EFFI

CIEN

CY (%

)POW

ER LOSS (W)

50

60

70

80

100

1 10

3800 TA04b

90

0

2

4

6

8

12

10VIN = 24V

VIN = 48V

VIN = 36V LOSS

VIN = 36V

Efficiency and Power Loss

TYPICAL APPLICATIO

U