lsisas1068 8-port, 3 gbit/s serial attached scsi...

DB08-000240-04 December 2004 1 of 32Version 2.0 Copyright © 2004 by LSI Logic Corporation. All rights reserved.

LSISAS1068 8-Port, 3 Gbit/s SerialAttached SCSI ControllerDatasheetVersion 2.0

The LSISAS1068 is an eight, port 3.0 Gbit/s SAS/SATA controller that iscompliant with the Fusion-MPT™ architecture, provides a PCI-Xinterface, and supports Integrated RAID.

Each of the eight phys on the LSISAS1068 is capable of 3.0 Gbit/s and1.5 Gbit/s link rates. The user can configure ports as wide or narrow.Narrow ports have one phy per port. Wide ports have between two andfour phys per port. Each port supports the SSP, SMP, STP, and SATAprotocols.

The SAS interface uses the proven SCSI command set to ensure reliabledata transfers, while providing the connectivity and flexibility of point-to-point serial data transfers. The SAS interface provides improvedperformance, simplified cabling, smaller connectors, lower pin count, andlower power requirements when compared to parallel SCSI. SAScontrollers leverage an electrical and physical connection interface thatis compatible with Serial ATA technology. The LSISAS1068 supports theANSI Serial Attached SCSI standard. Figure 1 and Figure 2 provideexamples of LSISAS1068 applications.

Figure 1 LSISAS1068 Direct-Connect Example

Flash ROM/

LSISAS106864-Bit, 133 MHzPCI-X Controller

PSBRAM/

I2C

PCI/PCI-X Interface

NVSRAM

SAS/SATADrives

32-bit MemoryAddress/Data

Bus

SAS/SATADrives

2 of 32 LSISAS1068 8-Port, 3 Gbit/s Serial Attached SCSI ControllerDB08-000240-04 December 2004 - Version 2.0 Copyright © 2004 by LSI Logic Corporation. All rights reserved.

Figure 2 LSISAS1068 Controller and LSISASx12 Expander Example

The LSISAS1068 supports a 133 MHz, 64-bit PCI-X bus. With theexception that the PCI interface is not tolerant of 5V PCI, the interface isbackward compatible with all revisions of the PCI/PCI-X bus. TheLSISAS1068 supports PCI-X split completion cycles and 32-bit or 64-bitdata bursts with variable burst length. The LSISAS1068 supports thePCI-X Addendum to the Peripheral Components Interface Specification,Revision 2.0, and the Peripheral Components Interface Specification,Revision 3.0.

The LSISAS1068 supports the Integrated RAID hardware solution, whichis a highly integrated, low cost RAID solution. It is designed for systemsrequiring redundancy and high availability, but not needing a full-featuredRAID implementation. Integrated RAID includes Integrated Mirroring™(IM) and Integrated Striping™ (IS) technology. IM provides physicalmirroring up to eight physical drives, and can perform mirroring of theboot volume through the LSISAS1068 firmware. IM requires an NVSRAMto support write journaling. IS enables data striping across up to eightphysical drives. Integrated RAID is OS independent, easy to install andconfigure, and does not require a special driver. A single firmware build

LSISAS1068

LSISASx12

Flash ROM/32-bit MemoryAddress/Data

Bus PSBRAM/

I2C

NVSRAM

LSISASx12

SAS/SATADrives

PCI/PCI-X Interface

SAS/SATADrives

SAS/SATADrives

SAS/SATADrives

SAS/SATADrives

LSISAS1068 8-Port, 3 Gbit/s Serial Attached SCSI Controller 3 of 32DB08-000240-04 December 2004 - Version 2.0 Copyright © 2004 by LSI Logic Corporation. All rights reserved.

supports all Integrated RAID capabilities. The LSISAS1068 also providesZero Channel RAID (ZCR) support.

The LSISAS1068 uses the Fusion-MPT (Message Passing Technology)architecture, which features a performance based message passingprotocol that offloads the host CPU by completely managing all I/Os andminimizes system bus overhead by coalescing interrupts. TheFusion-MPT architecture requires only thin, easy to develop devicedrivers that are independent of the I/O bus. LSI Logic provides thesedevice drivers.

To meet its flexibility and data transfer requirements, the LSISAS1068uses an ARM966 processor that operates at 225 MHz. LSI Logicmanufactures the LSISAS1068 controller using Gflx™ technology.

Features

This section lists the features of the LSISAS1068.

SAS Features

This section describes the SAS features.

• Each phy supports 3.0 Gbit/s and 1.5 Gbit/s SAS data transfers

• Provides a serial, point-to-point, enterprise-level storage interface

• Supports wide transfers consisting of 2 to 4 phys

• Supports narrow ports consisting of a single phy

• Transfers data using SCSI information units

• Compatible with SATA target devices

STP/SATA Features

This section describes the STP and SATA features.

• Supports 3.0 Gbit/s and 1.5 Gbit/s SATA data transfers

• Supports STP data transfers of 3.0 Gbits/s and 1.5 Gbits/s

• Allows addressing of multiple SATA targets through an expander


• Allows multiple initiators to address a single target (in a fail-overconfiguration) through an expander

PCI Performance

The LSISAS1068 supports these PCI features:

• 133 MHz, 64-bit PCI/PCI-X interface that:

– Operates up to 133 MHz PCI-X

– Operates at 33 MHz or 66 MHz PCI

– Supports 32-bit or 64-bit data transfers

– Supports 32-bit or 64-bit addressing through Dual AddressCycles (DAC)

– Provides a theoretical 1066 Mbytes/s PCI bandwidth

– Complies with the PCI Local Bus Specification, Revision 3.0

– Complies with the PCI-X Addendum to the PCI Local BusSpecification, Revision 2.0

– Complies with the PCI Power Management InterfaceSpecification, Revision 1.2

– Complies with the PC2001 Specification

• Provides unequalled performance through the Fusion-MPTarchitecture

• Provides high throughput and low CPU utilization to offload the hostprocessor

• Uses a dedicated ARM966 processor

• Presents a single electrical load to the PCI Bus

• Reduces Interrupt Service Routine (ISR) overhead with interruptcoalescing

• Supports 32-bit or 64-bit data bursts with variable burst lengths

• Supports the PCI Cache Line Size register

• Supports the PCI Memory Write and Invalidate, Memory Read Line,and Memory Read Multiple commands

• Supports the PCI-X Memory Read Dword, Split Completion, MemoryRead Block, Memory Write Block commands


• Supports a maximum of 16 outstanding PCI-X Split Transactions

Integration

These features make the LSISAS1068 easy to integrate:

• Supports backwards compatibility with previous revisions of the PCIspecification

• Provides a full 32-bit or 64-bit PCI-X DMA bus master

• Reduces time to market with the Fusion-MPT architecture

– Single driver binary for SAS/SATA, SCSI, and Fibre Channelproducts

– One firmware build supports all Integrated RAID capabilities

– Thin, easy to develop drivers

– Reduced integration and certification effort

Usability

This section describes the usability features.

• Simplifies cabling with point-to-point, serial architecture

• Provides drive spin-up sequencing control

• Provides up to two LED signals for each phy to indicate drive activityand faults

Flexibility

These features increase the flexibility of the LSISAS1068:

• Supports an 8-bit Flash ROM interface, an 8-bit nonvolatile RAM(NVSRAM) interface, and a 32-bit pipelined synchronous burstSRAM (PSBRAM) interface

• Offers a flexible programming interface to tune I/O performance

• Allows mixed connections to SAS or SATA targets

• Leverages compatible connectors for SAS and Serial ATAconnections

• Allows grouping of any phys within a quad port to form a wide port


• Supports Integrated RAID, which provides for Integrated Mirroringand/or Integrated Striping technology

• Provides 17 LED signals (16 of these configurable as GPIOs)

• Provides four independent GPIO signals

Reliability

These features enhance the reliability of the LSISAS1068:

• Uses proven GigaBlaze® transceivers

• Provides ESD protection

• Provides latch-up protection

• Has a high proportion of power and ground pins

• Integrated Mirroring technology provides physical mirroring of theboot volume

• Supports Zero Channel RAID

Testability

These features enhance the testability of the LSISAS1068:

• Offers JTAG boundary scan

• Offers ARM® Multi-ICE technology for debugging the ARM9processor

Block Diagram Description

Figure 3 provides the block diagram for the LSISAS1068 controller. Thefollowing subsections discuss the block diagram. There is a single HostInterface module and 2 Quad Port modules. Each Quad Port moduleprovides four phys.


Figure 3 LSISAS1068 Block Diagram

DMA Arbiter

PCI/PCI-XInterface

TimerConfig

IRQ Controller

Context RAM

AHB Arbiter

System Interface

UART

(ARM966)IOP

PCI

SAS Phy

SAS Link

AHB Bridge

Port Layer Connection

AHB InterfaceSECONDARY

QueueSATA Engine

PCI-X 133 MHzTimerConfig

ICE I/F

GPIO/LED

Management

Transport Module

Management and Switch

SAS Phy

SAS Link

SAS Phy

SAS Link

SAS Phy

SAS Link

Quad PortDMA Arbiter

AHB InterfaceCONTEXT

Quad Port 0 Module

S. EEPROM

I2CI2C

SAS Phy

SAS Link

AHB Bridge

Port Layer Connection

AHB InterfaceSECONDARY

QueueSATA EngineManagement

Transport Module

Management and Switch

SAS Phy

SAS Link

SAS Phy

SAS Link

SAS Phy

SAS Link

Quad PortDMA Arbiter

AHB InterfaceCONTEXT

Quad Port 1 Module

Pri

mar

y A

HB

Bu

s

Qu

ad P

ort

Co

nte

xt A

HB

Bu

s

SIO B

SIO ASIO A

SIO B

Host Interface Module

ExternalXMEM Bus

Memory

UART


Host Interface Module

The LSISAS1068 interfaces with the host through the host interfacemodule. The host interface module contains the PCI/PCI-X interface,system interface, PCI timer and configuration, DMA arbiter, IOP, I2C, SIOA, SIO B, UART, and external memory blocks.

PCI/PCI-X Interface

The LSISAS1068 provides a PCI-X interface that supports up to a 64-bit,133 MHz PCI-X bus. With the exception that the PCI interface is nottolerant of 5V PCI, the interface is backward compatible with all revisionsof the PCI/PCI-X bus.

System Interface

In combination with the IOP, the system interface supports theFusion-MPT architecture. The system interface efficiently passesmessages between the LSISAS1068 and the host interface using a high-performance, packetized mailbox architecture. The LSISAS1068 systeminterface coalesces PCI interrupts to minimize traffic on the PCI bus andmaximize system performance.

IOP

The LSISAS1068 I/O processor controls the system interface andmanages the host side of the Fusion-MPT architecture without hostprocessor intervention, which frees the host processor for other tasks.

Timer and Configuration

This block supports the LSISAS1068 LED and GPIO interfaces. TheGPIO interface contains four independent GPIO signals. This block alsosupports internal timing adjustments and power-on sense configurationoptions.

DMA Arbiter

The LSISAS1068 provides the ability to transfer system memory blocksto and from local memory through the descriptor-based DMA arbiter androuter. The DMA channel includes PCI bus master interface logic, asystem DMA FIFO, and the internal bus interface logic.


PCI Timer and Configuration

This PCI Timer and Configuration module supports the PCI configurationregister space, an industry-standard, 2-wire serial EEPROM interface,and a power-on reset (POR). A serial EEPROM is not required for typicalsystem configurations.

SIO A and SIO B

The LSISAS1068 provides two serialized general purpose I/O (SGPIO)interfaces that are compliant with the SFF-8485 specification. The SerialI/O (SIO) modules provide control of the LEDs that are located in therespective Quad Port modules. SIO A controls of the LEDs in Quad PortModule 0. SIO B controls the LEDs in Quad Port Module 1.

External Memory

The external memory controller block provides an interface for FlashROM, NVSRAM, and PSBRAM devices. The external memory busprovides a 32-bit memory bus, parity checking, and chip select signalsfor PSBRAM, NVSRAM, and Flash ROM. The Flash ROM and NVSRAMare capable of 8-bit accesses, while the PSBRAM is capable of 32-bitaccesses.

Typical system configurations require a Flash ROM to store firmware,configuration information, and persistent data information.

I2C

The LSISAS1068 contains an I2C port that communicates withperipherals, such as an enclosure management processor. The I2C portis also referred to as an Industry-Standard 2-Wire Interface (ISTWI). TheI2C block operates as either a master or a slave on the bus and sustainsdata rates up to 400 kbits/s. The I2C block accomplishes byte-wisebidirectional data transfers by using either an interrupt or a pollinghandshake at the completion of each byte. The style and operation of thisinterface closely follows the defacto standard for a two-wire serialinterface chip. The I2C block controls all bus timing and performs bus-specific sequences.

UART

The UART provides test and debug access to the LSISAS1068.


Quad Port Modules 0 and 1

The Quad Port modules in the LSISAS1068 implement the SSP, SMP,and STP/SATA protocols, and manage the SAS/SATA phys. There aretwo Quad Port modules in the LSISASx1068. Each Quad Port modulesupports four phys. The following subsections describe the Quad Portmodules.

Transport Module

The transport modules transmit frames to and from the port layer andimplement the STP, SSP, and SMP protocols. Each Quad Port modulehas four instances of the transport module, one for each SAS/SATA phyon the LSISAS1068. The transport modules also manage DMA transfers.

Queue Manager

The queue manager is responsible for managing various queuestructures that support the SSP, SMP, and SATA/STP protocols. Thequeue structures are the primary means for the IOP to initiate I/Os to thehardware, and for the hardware to notify the IOP of I/O status.

SATA Engine

The SATA engine provides information to the transport modules to enablehandling of SATA commands. The SATA engine tracks queuedcommands per device and provides these tags to the SATA transportlayer blocks.

Port Layer Connection Manager and Switch

The port layer connection monitor and switch manages transmissionrequests from the transport modules and originates connection requeststo the SAS links. It is also responsible for handling SAS wide portconfigurations.

SAS Link

The SAS link layer manages SAS connections between initiator andtarget ports, data clocking, and CRC checking on transmitted data. TheSAS link is also responsible for starting a link reset sequence.


SAS Phy

The SAS phys interface to the physical layer, perform serial-to-parallelconversion of received data and parallel-to-serial conversion of transmitdata, manage phy reset sequences, and perform 8b/10b encoding.

Quad Port Arbiter

The quad port arbiter interfaces with the host interface DMA arbiter anddetermines bus priority between the ports for DMA transfers.

Context RAM

The context RAM is a memory that is shared between the host interfacemodule and the quad port module. The context RAM holds a portion ofthe firmware.

Signal Description

The following subsections provide the signal descriptions for theLSISAS1068. A ‘/’ following the signal indicates an active LOW signal.

PCI Signals

This section describes the PCI signals. Refer to the PCI specification forsignal descriptions.

PCI System Signals

This section describes the PCI system signals.

CLK PCI Clock Input

RST/ Reset Input

PCI Address and Data Signals

This section describes the PCI address and data signals.

AD[63:0] 64-Bit Address/Data Bus Input/Output

C_BE[7:0]/ Command/Byte Enable Input/Output


PAR Parity Input/Output

PAR64 64-Bit Parity Input/Output

PCI Interface Control Signals

This section describes the PCI interface control signals.

GNT/ Grant Input

REQ/ Request Output

REQ64/ Request 64-Bit Input/Output

ACK64/ Acknowledge 64-Bit Input/Output

IDSEL ID Select Input

FRAME/ Frame Input/Output

IRDY/ Initiator Ready Input/Output

TRDY/ Target Ready Input/Output

DEVSEL/ Device Select Input/Output

STOP/ Stop Input/Output

PERR/ Parity Error Input/Output

SERR/ Error Input/Output

INTA/ PCI Interrupt A Output

PCI-Related Signals

ALT_INTA/ Alternate PCI Interrupt A OutputThe alternate interrupt signal is used for ZCR.

ALT_GNT/ Read/Write Chip Select InputThis active LOW signal provides a chip select duringconfiguration read and write transactions. Enabling ZeroChannel RAID enables this signal.


ZCR_EN/ Zero Channel RAID Enable InputThis input configures the LSISAS1068 for ZCR operation.When ZCR_EN/ is asserted, the LSISAS1068 uses theALT_INTA/ and ALT_GNT/ signals. Deasserting this sig-nal configures the LSISAS1068 for standard PCI/PCI-Xoperation, using the INTA/ and IDSEL/ signals. This inputis internally pulled HIGH.

BZR_SET Reference Resistance AnalogThis signal provides the reference resistor node for thePCI-X impedance controller.

BZVDD Reference Resistance AnalogThis signal provides the reference resistor node for PCI-Ximpedance controller.

Compact PCI Signals

This section describes the CompactPCI signals.

CPCI_EN/ CompactPCI Enable InputEnabling this active LOW signal configures theLSISAS1068 for the CompactPCI protocol. This signal isinternally pulled HIGH.

CPCI_SWITCHCompactPCI Switch InputThis active HIGH signal indicates to the LSISAS1068device that a change in the system configuration isimminent. This signal is internally pulled LOW.

CPCI_ENUM/ CompactPCI Input/OutputThis signal informs the system that a board either wasfreshly inserted or is about to be extracted. This signalremains asserted until the system driver services the hot-swapped board.

CPCI64_EN/ CompactPCI 64-Bit Enable InputThis pin indicates the width of the PCI bus when Com-pactPCI is enabled. Designers must provide a pull-up onthis pin when the device is enabled for Compact PCIoperation. When Compact PCI is not enabled, designersmust leave this pin unconnected.


CPCI_LED/ CompactPCI LED OutputThis active LOW pin provides the CompactPCI StatusLED. This is a 3.3 V output.

SAS Signals

This section describes the SAS interface signals.

REFCLK_P, REFCLK_N InputThese pins provide the serial differential clock. Connect a75 MHz oscillator with an accuracy of at least ± 50 ppm tothese pins. To use a single-ended crystal, tie the crystal toREFCLK_P and tie REFCLK_N to a resistor termination.

RTRIM Resistor Reference AnalogThis pin provides the analog resistor reference for theGigaBlaze transceivers.

RX[7:0]− Receive Negative Differential Data InputRX[x]− provides the negative differential data receiver forphy[x].

RX[7:0]+ Receive Positive Differential Data InputRX[x]+ provides the positive differential data receiver forphy[x].

TX[7:0]− Transmit Negative Differential Data OutputTX[x]− provides the negative differential data transmit sig-nal for phy[x].

TX[7:0]+ Transmit Positive Differential Data OutputTX[x]+ provides the positive differential data transmitsignal for each phy[x].

I2C and Serial EEPROM Signals

This section describes the serial EEPROM and I2C signals.

SERIAL_CLK Serial Interface Clock Input/OutputThis pin provides the serial EEPROM clock signal. Thispin is internally pulled HIGH.

SERIAL_DATA Serial Interface Data Input/OutputThis pin provides the serial EEPROM data signal. Thispin is internally pulled HIGH.


ISTWI_CLK I2C Clock Input/OutputThis pin provides the I2C clock signal.

ISTWI_DATA I2C Data Input/OutputThis pin provides the I2C data signal.

Memory Interface Signals

This section describes the memory interface pins.

MCLK Memory Clock OutputAll synchronous RAM control/data signals reference therising edge of this clock.

ADSC/ Address-Strobe-Controller OutputAsserting this active LOW signal initiates READ, WRITE,or chip deselect cycles.

ADV/ Advance OutputAsserting this active LOW signal increments the burstaddress counter of the selected synchronous SRAM.

MAD[31:0] Multiplexed Address/Data Input/OutputThese signals provide the address and data bus to thePSBRAM, Flash ROM, and NVSRAM. These signals alsoprovide Power-On Sense configuration functions to theLSISAS1068. These signals are internally pulled LOW.

Important: Provide pull-up resistors for these pins.

MADP[3:0] Memory Parity Input/OutputThese signals provide parity checking for MAD[31:0].These signals are internally pulled HIGH.

MOE[1:0]/ Memory Output Enables OutputAsserting these active LOW signals enable the selectedPSBRAM, Flash ROM, or NVSRAM device to drive data.MOE[1]/ enables PSBRAM and Flash ROM devices.MOE[0]/ enables NVSRAM devices. MOE[1:0]/ allowinterleaved PSBRAM configurations.

MWE[1:0]/ Memory Write Enables OutputThe LSISAS1068 uses these active LOW bank writesignals for interleaved PSBRAM configurations.


BWE[3:0]/ Memory Byte Write Enables OutputAsserting these active LOW, byte-lane write signalsenable partial word writes to the PSBRAM. BWE[3]/ andBWE[2]/ enable partial word writes to the Flash ROM andthe NVSRAM if FLASH_CS/ or NVSRAM_CS/ areasserted.

NVSRAM_CS/ NVSRAM Chip Select OutputAsserting this active LOW signal selects the NVSRAMdevice.

PSBRAM_CS/ RAM Chip Select OutputAsserting this active LOW signal selects the PSBRAMs.Up to four PSBRAMS are possible in an interleaved anddepth-expanded configuration.

FLASH_CS/ Flash Chip Select OutputAsserting the active LOW signal selects the Flash ROM.The LSISAS1068 maps Flash ROM address space intosystem memory space.

SIO Pins

This section describes the SIO A and SIO B pins.

SIO_CLK_A SIO Clock OutputThis signal provides the clock signal for SIO A.

SIO_CLK_B SIO Clock OutputThis signal provides the clock signal for SIO B.

SIO_DIN_A SIO Data In A InputThis pin provides the data input signal to the SIO inter-face for Quad Port 0.

SIO_DIN_B SIO Data In B InputThis pin provides the data input signal to the SIO inter-face for Quad Port 1.

SIO_DOUT_A SIO Data Out A OutputThis signal provides the data output signal to the SIO busfrom Quad Port 0. This signal controls the Quad Port 0LED drives.


SIO_DOUT_B SIO Data Out B OutputThis signal provides the data output signal to the SIO busfrom Quad Port 1. This signal controls the Quad Port 1LED drives.

SIO_END_A SIO End Control OutputThe SIO module drives this output to end control of theSIO bus on Quad Port 0.

SIO_END_B SIO End Control OutputThe SIO module drives this output to end control of theSIO bus on Quad Port 1.

Configuration and General Purpose Signals

This section describes the configuration and general purpose pins.

TST_RST/ Test Reset InputAsserting this signal forces the chip into a Power-On-Reset (POR) state. This signal has an internal pull-up.

REFCLK_B ARM Reference Clock InputThis pin provides the ARM reference clock. This pin hasan internal pull-down.

Note: See the reference schematics provided by the LSI LogicSSP Systems Engineering group, for details regarding howto connect REFCLK_B to the REFCLK_P and REFCLK_Nnetwork.

MODE[5:0] Mode Select InputThis 6-bit bus defines operational and test modes for thechip. These pins have internal pull-downs.

FAULT_LED[7:0]/Fault LED OutputThese output signals indicate a SAS link fault.

ACTIVE_LED[7:0]/Activity LED OutputThese output signals indicate SAS link activity.

GPIO[3:0] General Purpose I/O Input/OutputThese pins provide general purpose input/output signals.These pins have internal pull-ups.


HB_LED/ Heartbeat LED OutputFirmware intermittently asserts this signal to indicate thatthe IOP is operational.

JTAG and Test Signals

This section describes the test and JTAG signals.

FSELA Clock Select InputLSI Logic factory test only. Pull this signal LOW.

TCK JTAG Debug Clock Input

TRST/ JTAG Debug Reset Input

TDI JTAG Debug Test Data In Input

TDO JTAG Debug Test Data Out Output

TMS JTAG Debug Test Mode Select Input

TCK_ICE Multi-ICE Debug Clock Input

RTCK_ICE Multi-ICE Debug Return Clock Output

TRST_ICE/ Multi-ICE Debug Reset Input

TDI_ICE Multi-ICE Debug Test Data In Input

TDO_ICE Multi-ICE Debug Test Data Out Output

TMS_ICE Multi-ICE Debug Test Mode Select Input

IDDTN IDDQ Test Mode Enable InputLSI Logic factory test only. Pull this signal LOW.

TN/ 3-State Output Enable Control InputLSI Logic factory test only. Pull this signal HIGH.

PROCMON Process Monitor Test Output Driver OutputLSI Logic factory test only.

SCAN_ENABLETest Input Pin InputLSI Logic factory test only. Pull this signal LOW.

SCAN_MODE Test Input Pin InputLSI Logic factory test only. Pull this signal LOW.


ECC[5:2] Test Pins Input/OutputLSI Logic factory test only.

SPARE[3:2] Test Mux Spare Input/OutputLSI Logic factory test only.

TDIODE_P Anode Connection of the Thermal Diode Input

TDIODE_N Cathode Connection of the Thermal Diode Output

UART_RX UART Receive Input

UART_TX UART Transmit Output

RESERVED Reserved InputLSI Logic factory test only. These signals must be leftunconnected.

Power Signals

This section describes the power and ground signals.

REFPLL_VDD PowerThese signals provide 1.2 V power.

REFPLL_VSS GroundThese signals provide ground.

PLL_VDD PowerThese signals provide 1.2 V power.

PLL_VSS GroundThese signals provide ground.

VDD2 PowerThese signals provide 1.2 V core power.

VDDIO33 PowerThese signals provide 3.3 V I/O power.

VSS2 GroundThese signals provide ground.

RX_VSS[7:0], RXB_VSS[7:0], TX_VSS[7:0], TXB_VSS[7:0] GroundThese signals provide ground for the GigaBlaze core.


RX_VDD[7:0], RXB_VDD[7:0], TX_VDD[7:0], TXB_VDD[7:0] PowerThese signals provide 1.2 V power for the GigaBlazecore.

Pin Listing

Table 1 and Table 2 provide pin listings for the LSISAS1068. Figure 4provide the BGA diagram.


Table 1 Listing by Signal Name1

1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locationsmarked RESERVED are for LSI Logic factory test use only. Refer to the Signal Description sectionto determine how to terminate the RESERVED pads.

N/C J2N/C J5N/C J21N/C J26N/C K5N/C K6N/C K21N/C L5N/C L6N/C L21N/C L22N/C M22N/C N1N/C N21N/C N25N/C P6N/C P21N/C R5N/C R22N/C T5N/C U21N/C U22N/C V22N/C W2N/C W6N/C Y5N/C Y7N/C Y21N/C AA7N/C AA8N/C AA9N/C AA13N/C AA14N/C AA15N/C AA17N/C AA18N/C AA21N/C AB3N/C AB8N/C AB10N/C AB11N/C AB12N/C AB17N/C AB19N/C AB23N/C AB26N/C AC13N/C AD4N/C AD9N/C AD18N/C AE9N/C AE14N/C AE18N/C AE25N/C AF15N/C AF17N/C AF18

Signal PinSignal Pin

ACK64/ AC16ACTIVE_LED[0]/ H3ACTIVE_LED[1]/ F1ACTIVE_LED[2]/ H4ACTIVE_LED[3]/ H6ACTIVE_LED[4]/ J6ACTIVE_LED[5]/ J4ACTIVE_LED[6]/ J3ACTIVE_LED[7]/ G1AD[0] AC14AD[1] AB16AD[2] AB14AD[3] AD14AD[4] AF14AD[5] AC15AD[6] AB13AD[7] AE13AD[8] AF12AD[9] AD13AD[10] AF9AD[11] AA12AD[12] AF10AD[13] AF11AD[14] AE10AD[15] AE8AD[16] AC8AD[17] AD8AD[18] AB7AD[19] AF4AD[20] AB6AD[21] AD5AD[22] AA4AD[23] AC7AD[24] AE4AD[25] AC5AD[26] AB5AD[27] AE2AD[28] AC3AD[29] AB4AD[30] V6AD[31] AC4AD[32] AB25AD[33] AC26AD[34] W22AD[35] Y23AD[36] W21AD[37] AC24AD[38] W23AD[39] Y22AD[40] AC25AD[41] AD25AD[42] AC23AD[43] AC22AD[44] Y20AD[45] AD22AD[46] AA20AD[47] AA23AD[48] AB21AD[49] AC21AD[50] AA22

AD[51] AD24AD[52] AA19AD[53] AD23AD[54] AF23AD[55] AE24AD[56] AF22AD[57] AE23AD[58] AE22AD[59] AC20AD[60] AD19AD[61] AB18AD[62] AF20AD[63] AC18ADSC/ R21ADV/ R23ALT_INTA/ U5ALT_GNT/ AA1BZR_SET V21BZVDD AA26BWE[0]/ P22BWE[1]/ P25BWE[2]/ L26BWE[3]/ P26C_BE[0]/ AC12C_BE[1]/ AA11C_BE[2]/ AC9C_BE[3]/ AA6C_BE[4]/ AB15C_BE[5]/ AC17C_BE[6]/ AE17C_BE[7]/ AF19CLK Y6CPCI64_EN/ U6CPCI_EN/ T6CPCI_LED/ N6CPCI_ENUM/ U4CPCI_SWITCH U3DEVSEL/ AF6ECC2 AC1ECC3 W4ECC4 AB1ECC5 V5FAULT_LED[0]/ K3FAULT_LED[1]/ K4FAULT_LED[2]/ H1FAULT_LED[3]/ H2FAULT_LED[4]/ L4FAULT_LED[5]/ J1FAULT_LED[6]/ K1FAULT_LED[7]/ K2FLASH_CS/ L23FRAME/ AB9FSELA E3GNT/ AC2GPIO[0] P5GPIO[1] P4GPIO[2] R1GPIO[3] P3HB_LED/ M5IDSEL AE3

IDDT V2INTA/ Y1IRDY/ AF8ISTWI_CLK H23ISTWI_DATA D24MAD[0] E26MAD[1] F26MAD[2] K22MAD[3] D25MAD[4] G23MAD[5] J24MAD[6] J23MAD[7] E25MAD[8] G26MAD[9] K23MAD[10] H24MAD[11] D26MAD[12] H25MAD[13] J25MAD[14] M21MAD[15] K25MAD[16] U25MAD[17] T26MAD[18] U26MAD[19] R26MAD[20] V26MAD[21] T22MAD[22] W25MAD[23] V25MAD[24] T23MAD[25] V24MAD[26] U24MAD[27] U23MAD[28] W26MAD[29] T21MAD[30] W24MAD[31] V23MCLK P23MODE[0] E2MODE[1] D1MODE[2] G4MODE[3] D2MODE[4] F4MODE[5] G6MOE0/ M26MOE1/ H26MADP[0] J22MADP[1] N24MADP[2] P24MADP[3] Y26MWE0/ N26MWE1/ K26N/C C2N/C C25N/C D3N/C D23N/C E1N/C E24N/C G5N/C H5

Signal Pin Signal Pin


Table 1 Listing by Signal Name (Cont.)1


VDD2 T11VDD2 T13VDD2 T15VDD2 T17VDD2 U10VDD2 U12VDD2 U14VDD2 U16VDDIO33 A24VDDIO33 B2VDDIO33 B11VDDIO33 B12VDDIO33 B15VDDIO33 B16VDDIO33 C1VDDIO33 C5VDDIO33 C6VDDIO33 C20VDDIO33 C21VDDIO33 C26VDDIO33 D13VDDIO33 F2VDDIO33 F25VDDIO33 G2VDDIO33 G9VDDIO33 G11VDDIO33 G12VDDIO33 G13VDDIO33 G14VDDIO33 G15VDDIO33 G17VDDIO33 G19VDDIO33 G25VDDIO33 H7VDDIO33 H20VDDIO33 J7VDDIO33 J20VDDIO33 K7VDDIO33 K20VDDIO33 L2VDDIO33 L7VDDIO33 L20VDDIO33 L25VDDIO33 M2VDDIO33 M7VDDIO33 M20VDDIO33 M25VDDIO33 N7VDDIO33 N20VDDIO33 P7VDDIO33 P20VDDIO33 R2VDDIO33 R7VDDIO33 R20VDDIO33 R25VDDIO33 T2VDDIO33 T7VDDIO33 T20

Signal PinSignal PinN/C AF21NVSRAM_CS/ K24PAR AC11PAR64 AE19PBSRAM_CS/ M23PERR/ AA10PLLVDD AD3PLLVSS AA5PROCMON U2REFCLK_B B13REFCLK_N D12REFCLK_P C13REFPLL_VDD B14REFPLL_VSS A13REQ/ Y4REQ64/ AD17RESERVED V4RESERVED W3RST/ W5RTCK_ICE N3RTRIM C14RX0+ B24RX0– B25RX1+ B20RX1– B21RX2+ A19RX2– A20RX3+ A17RX3– B17RX4+ A10RX4– A11RX5+ B8RX5– A8RX6+ B6RX6– B7RX7+ B3RX7– C3RX_VDD0 E21RX_VDD1 D19RX_VDD2 C18RX_VDD3 D15RX_VDD4 B10RX_VDD5 D9RX_VDD6 D7RX_VDD7 E6RX_VSS0 D22RX_VSS1 F18RX_VSS2 D17RX_VSS3 F15RX_VSS4 E12RX_VSS5 C9RX_VSS6 F9RX_VSS7 E7RXB_VDD0 C23RXB_VDD1 C19RXB_VDD2 F17RXB_VDD3 E15RXB_VDD4 A12

RXB_VDD5 C10RXB_VDD6 E9RXB_VDD7 G8RXB_VSS0 F21RXB_VSS1 F19RXB_VSS2 E17RXB_VSS3 G16RXB_VSS4 F13RXB_VSS5 F11RXB_VSS6 G10RXB_VSS7 C7SCAN_ENABLE E4SCAN_MODE F5SERIAL_CLK F23SERIAL_DATA H21SERR/ AE5SIO_CLK_A F22SIO_CLK_B M4SIO_DIN_A G21SIO_DIN_B M1SIO_DOUT_A G22SIO_DOUT_B M6SIO_END_A C24SIO_END_B L1SPARE2 G20SPARE3 E22STOP/ AF7TCK T1TCK_ICE N5TDI R6TDI_ICE P2TDIODE_P N22TDIODE_VSS N23TDO R4TDO_ICE P1TMS V1TMS_ICE N2TN/ T4TRDY/ AC10TRST/ U1TRST_ICE/ N4TST_RST/ F6TX0+ B22TX0– B23TX1+ A22TX1– A21TX2+ B18TX2– A18TX3+ A16TX3– A15TX4+ A9TX4– B9TX5+ A6TX5– A5TX6+ B4TX6– B5TX7+ A4TX7– A3

TX_VDD0 A23TX_VDD1 D18TX_VDD2 C17TX_VDD3 D14TX_VDD4 D10TX_VDD5 D8TX_VDD6 C4TX_VDD7 E5TX_VSS0 E19TX_VSS1 G18TX_VSS2 D16TX_VSS3 E14TX_VSS4 E11TX_VSS5 A7TX_VSS6 F8TX_VSS7 F7TXB_VDD0 F20TXB_VDD1 E18TXB_VDD2 F16TXB_VDD3 A14TXB_VDD4 F12TXB_VDD5 E10TXB_VDD6 C8TXB_VDD7 G7TXB_VSS0 E20TXB_VSS1 B19TXB_VSS2 E16TXB_VSS3 F14TXB_VSS4 D11TXB_VSS5 F10TXB_VSS6 E8TXB_VSS7 D4UART_RX E23UART_TX H22VDD2 K11VDD2 K13VDD2 K15VDD2 K17VDD2 L10VDD2 L12VDD2 L14VDD2 L16VDD2 M11VDD2 M13VDD2 M15VDD2 M17VDD2 N10VDD2 N12VDD2 N14VDD2 N16VDD2 P11VDD2 P13VDD2 P15VDD2 P17VDD2 R10VDD2 R12VDD2 R14VDD2 R16



Table 1 Listing by Signal Name (Cont.)1


VSS T14VSS T16VSS T19VSS T24VSS U8VSS U11VSS U13VSS U15VSS U17VSS U19VSS V8VSS V19VSS W8VSS W9VSS W10VSS W11VSS W12VSS W13VSS W14VSS W15VSS W16VSS W17VSS W18VSS W19VSS Y3VSS Y24VSS AA3VSS AA24VSS AD6VSS AD7VSS AD11VSS AD12VSS AD15VSS AD16VSS AD20VSS AD21VSS AE1VSS AE26VSS AF2VSS AF25ZCR_EN/ W1

Signal PinSignal PinVDDIO33 T25VDDIO33 U7VDDIO33 U20VDDIO33 V3VDDIO33 V7VDDIO33 V20VDDIO33 W7VDDIO33 W20VDDIO33 Y2VDDIO33 Y8VDDIO33 Y9VDDIO33 Y10VDDIO33 Y11VDDIO33 Y12VDDIO33 Y13VDDIO33 Y14VDDIO33 Y15VDDIO33 Y16VDDIO33 Y17VDDIO33 Y18VDDIO33 Y19VDDIO33 Y25VDDIO33 AA2VDDIO33 AA16VDDIO33 AA25VDDIO33 AB2VDDIO33 AB20VDDIO33 AB22VDDIO33 AB24VDDIO33 AC6VDDIO33 AC19VDDIO33 AD1VDDIO33 AD2VDDIO33 AD10VDDIO33 AD26VDDIO33 AE6VDDIO33 AE7VDDIO33 AE11VDDIO33 AE12VDDIO33 AE15VDDIO33 AE16VDDIO33 AE20

VDDIO33 AE21VDDIO33 AF3VDDIO33 AF5VDDIO33 AF13VDDIO33 AF16VDDIO33 AF24VSS A2VSS A25VSS B1VSS B26VSS C11VSS C12VSS C15VSS C16VSS C22VSS D5VSS D6VSS D20VSS D21VSS E13VSS F3VSS F24VSS G3VSS G24VSS H8VSS H9VSS H10VSS H11VSS H12VSS H13VSS H14VSS H15VSS H16VSS H17VSS H18VSS H19VSS J8VSS J19VSS K8VSS K10VSS K12VSS K14

VSS K16VSS K19VSS L3VSS L8VSS L11VSS L13VSS L15VSS L17VSS L19VSS L24VSS M3VSS M8VSS M10VSS M12VSS M14VSS M16VSS M19VSS M24VSS N8VSS N11VSS N13VSS N15VSS N17VSS N19VSS P8VSS P10VSS P12VSS P14VSS P16VSS P19VSS R3VSS R8VSS R11VSS R13VSS R15VSS R17VSS R19VSS R24VSS T3VSS T8VSS T10VSS T12



Table 2 Listing by Pin Number1


H4 ACTIVE_LED[2]/H5 N/CH6 ACTIVE_LED[3]/H7 VDDIO33H8 VSSH9 VSSH10 VSSH11 VSSH12 VSSH13 VSSH14 VSSH15 VSSH16 VSSH17 VSSH18 VSSH19 VSSH20 VDDIO33H21 SERIAL_DATAH22 UART_TXH23 ISTWI_CLKH24 MAD[10]H25 MAD[12]H26 MOE1/J1 FAULT_LED[5]/J2 N/CJ3 ACTIVE_LED[6]/J4 ACTIVE_LED[5]/J5 N/CJ6 ACTIVE_LED[4]/J7 VDDIO33J8 VSSJ19 VSSJ20 VDDIO33J21 N/CJ22 MADP[0]J23 MAD[6]J24 MAD[5]J25 MAD[13]J26 N/CK1 FAULT_LED[6]/K2 FAULT_LED[7]/K3 FAULT_LED[0]/K4 FAULT_LED[1]/K5 N/CK6 N/CK7 VDDIO33K8 VSSK10 VSSK11 VDD2K12 VSSK13 VDD2K14 VSSK15 VDD2K16 VSSK17 VDD2K19 VSSK20 VDDIO33K21 N/CK22 MAD[2]K23 MAD[9]K24 NVSRAM_CS/


A2 VSSA3 TX7–A4 TX7+A5 TX5–A6 TX5+A7 TX_VSS5A8 RX5–A9 TX4+A10 RX4+A11 RX4–A12 RXB_VDD4A13 REFPLL_VSSA14 TXB_VDD3A15 TX3–A16 TX3+A17 RX3+A18 TX2–A19 RX2+A20 RX2–A21 TX1–A22 TX1+A23 TX_VDD0A24 VDDIO33A25 VSSB1 VSSB2 VDDIO33B3 RX7+B4 TX6+B5 TX6–B6 RX6+B7 RX6–B8 RX5+B9 TX4–B10 RX_VDD4B11 VDDIO33B12 VDDIO33B13 REFCLK_BB14 REFPLL_VDDB15 VDDIO33B16 VDDIO33B17 RX3–B18 TX2+B19 TXB_VSS1B20 RX1+B21 RX1–B22 TX0+B23 TX0–B24 RX0+B25 RX0–B26 VSSC1 VDDIO33C2 N/CC3 RX7–C4 TXVDD6C5 VDDIO33C6 VDDIO33C7 RXB_VSS7C8 TXB_VDD6C9 RX_VSS5C10 RXB_VDD5C11 VSS

C12 VSSC13 REFCLK_PC14 RTRIMC15 VSSC16 VSSC17 TX_VDD2C18 RX_VDD2C19 RXB_VDD1C20 VDDIO33C21 VDDIO33C22 VSSC23 RXB_VDD0C24 SIO_END_AC25 N/CC26 VDDIO33D1 MODE[1]D2 MODE[3]D3 N/CD4 TXB_VSS7D5 VSSD6 VSSD7 RX_VDD6D8 TX_VDD5D9 RX_VDD5D10 TX_VDD4D11 TXB_VSS4D12 REFCLK_ND13 VDDIO33D14 TX_VDD3D15 RX_VDD3D16 TX_VSS2D17 RX_VSS2D18 TX_VDD1D19 RX_VDD1D20 VSSD21 VSSD22 RX_VSS0D23 N/CD24 ISTWI_DATAD25 MAD[3]D26 MAD[11]E1 N/CE2 MODE[0]E3 FSELAE4 SCAN_ENABLEE5 TX_VDD7E6 RX_VDD7E7 RX_VSS7E8 TXB_VSS6E9 RXB_VDD6E10 TXB_VDD5E11 TX_VSS4E12 RX_VSS4E13 VSSE14 TX_VSS3E15 RXB_VDD3E16 TXB_VSS2E17 RXB_VSS2E18 TXB_VDD1E19 TX_VSS0E20 TXB_VSS0

E21 RX_VDD0E22 SPARE3E23 UART_RXE24 N/CE25 MAD[7]E26 MAD[0]F1 ACTIVE_LED[1]/F2 VDDIO33F3 VSSF4 MODE[4]F5 SCAN_MODEF6 TST_RST/F7 TX_VSS7F8 TX_VSS6F9 RX_VSS6F10 TXB_VSS5F11 RXB_VSS5F12 TXB_VDD4F13 RXB_VSS4F14 TXB_VSS3F15 RX_VSS3F16 TXB_VDD2F17 RXB_VDD2F18 RX_VSS1F19 RXB_VSS1F20 TXB_VDD0F21 RXB_VSS0F22 SIO_CLK_AF23 SERIAL_CLKF24 VSSF25 VDDIO33F26 MAD[1]G1 ACTIVE_LED[7]/G2 VDDIO33G3 VSSG4 MODE[2]G5 N/CG6 MODE[5]G7 TXB_VDD7G8 RXB_VDD7G9 VDDIO33G10 RXB_VSS6G11 VDDIO33G12 VDDIO33G13 VDDIO33G14 VDDIO33G15 VDDIO33G16 RXB_VSS3G17 VDDIO33G18 TX_VSS1G19 VDDIO33G20 SPARE2G21 SIO_DIN_AG22 SIO_DOUT_AG23 MAD[4]G24 VSSG25 VDDIO33G26 MAD[8]H1 FAULT_LED[2]/H2 FAULT_LED[3]/H3 ACTIVE_LED[0]/



Table 2 Listing by Pin Number (Cont.)1


V2 IDDTV3 VDDIO33V4 RESERVEDV5 ECC5V6 AD[30]V7 VDDIO33V8 VSSV19 VSSV20 VDDIO33V21 BZR_SETV22 N/CV23 MAD[31]V24 MAD[25]V25 MAD[23]V26 MAD[20]W1 ZCR_EN/W2 N/CW3 RESERVEDW4 ECC3W5 RST/W6 N/CW7 VDDIO33W8 VSSW9 VSSW10 VSSW11 VSSW12 VSSW13 VSSW14 VSSW15 VSSW16 VSSW17 VSSW18 VSSW19 VSSW20 VDDIO33W21 AD[36]W22 AD[34]W23 AD[38]W24 MAD[30]W25 MAD[22]W26 MAD[28]Y1 INTA/Y2 VDDIO33Y3 VSSY4 REQ/Y5 N/CY6 CLKY7 N/CY8 VDDIO33Y9 VDDIO33Y10 VDDIO33Y11 VDDIO33Y12 VDDIO33Y13 VDDIO33Y14 VDDIO33Y15 VDDIO33

Signal PinSignal PinK25 MAD[15]K26 MWE1/L1 SIO_END_BL2 VDDIO33L3 VSSL4 FAULT_LED[4]/L5 N/CL6 N/CL7 VDDIO33L8 VSSL10 VDD2L11 VSSL12 VDD2L13 VSSL14 VDD2L15 VSSL16 VDD2L17 VSSL19 VSSL20 VDDIO33L21 N/CL22 N/CL23 FLASH_CS/L24 VSSL25 VDDIO33L26 BWE[2]/M1 SIO_DIN_BM2 VDDIO33M3 VSSM4 SIO_CLK_BM5 HB_LED/M6 SIO_DOUT_BM7 VDDIO33M8 VSSM10 VSSM11 VDD2M12 VSSM13 VDD2M14 VSSM15 VDD2M16 VSSM17 VDD2M19 VSSM20 VDDIO33M21 MAD[14]M22 N/CM23 PBSRAM_CS/M24 VSSM25 VDDIO33M26 MOE0/N1 N/CN2 TMS_ICEN3 RTCK_ICEN4 TRST_ICE/N5 TCK_ICEN6 CPCI_LED/N7 VDDIO33

N8 VSSN10 VDD2N11 VSSN12 VDD2N13 VSSN14 VDD2N15 VSSN16 VDD2N17 VSSN19 VSSN20 VDDIO33N21 N/CN22 TDIODE_PN23 TDIODE_VSSN24 MADP[1]N25 N/CN26 MWE0/P1 TDO_ICEP2 TDI_ICEP3 GPIO[3]P4 GPIO[1]P5 GPIO[0]P6 N/CP7 VDDIO33P8 VSSP10 VSSP11 VDD2P12 VSSP13 VDD2P14 VSSP15 VDD2P16 VSSP17 VDD2P19 VSSP20 VDDIO33P21 N/CP22 BWE[0]/P23 MCLKP24 MADP[2]P25 BWE[1]/P26 BWE[3]/R1 GPIO[2]R2 VDDIO33R3 VSSR4 TDOR5 N/CR6 TDIR7 VDDIO33R8 VSSR10 VDD2R11 VSSR12 VDD2R13 VSSR14 VDD2R15 VSSR16 VDD2R17 VSS

R19 VSSR20 VDDIO33R21 ADSC/R22 N/CR23 ADV/R24 VSSR25 VDDIO33R26 MAD[19]T1 TCKT2 VDDIO33T3 VSST4 TN/T5 N/CT6 CPCI_EN/T7 VDDIO33T8 VSST10 VSST11 VDD2T12 VSST13 VDD2T14 VSST15 VDD2T16 VSST17 VDD2T19 VSST20 VDDIO33T21 MAD[29]T22 MAD[21]T23 MAD[24]T24 VSST25 VDDIO33T26 MAD[17]U1 TRST/U2 PROCMONU3 CPCI_SWITCHU4 CPCI_ENUM/U5 ALT_INTA/U6 CPCI64_EN/U7 VDDIO33U8 VSSU10 VDD2U11 VSSU12 VDD2U13 VSSU14 VDD2U15 VSSU16 VDD2U17 VSSU19 VSSU20 VDDIO33U21 N/CU22 N/CU23 MAD[27]U24 MAD[26]U25 MAD[16]U26 MAD[18]V1 TMS



Table 2 Listing by Pin Number (Cont.)1


AE12 VDDIO33AE13 AD[7]AE14 N/CAE15 VDDIO33AE16 VDDIO33AE17 C_BE[6]/AE18 N/CAE19 PAR64AE20 VDDIO33AE21 VDDIO33AE22 AD[58]AE23 AD[57]AE24 AD[55]AE25 N/CAE26 VSSAF2 VSSAF3 VDDIO33AF4 AD[19]AF5 VDDIO33AF6 DEVSEL/AF7 STOP/AF8 IRDY/AF9 AD[10]AF10 AD[12]AF11 AD[13]AF12 AD[8]AF13 VDDIO33AF14 AD[4]AF15 N/CAF16 VDDIO33AF17 N/CAF18 N/CAF19 C_BE[7]/AF20 AD[62]AF21 N/CAF22 AD[56]AF23 AD[54]AF24 VDDIO33AF25 VSS


Y16 VDDIO33Y17 VDDIO33Y18 VDDIO33Y19 VDDIO33Y20 AD[44]Y21 N/CY22 AD[39]Y23 AD[35]Y24 VSSY25 VDDIO33Y26 MADP[3]AA1 ALT_GNT/AA2 VDDIO33AA3 VSSAA4 AD[22]AA5 PLLVSSAA6 C_BE[3]/AA7 N/CAA8 N/CAA9 N/CAA10 PERR/AA11 C_BE[1]/AA12 AD[11]AA13 N/CAA14 N/CAA15 N/CAA16 VDDIO33AA17 N/CAA18 N/CAA19 AD[52]AA20 AD[46]AA21 N/CAA22 AD[50]AA23 AD[47]AA24 VSSAA25 VDDIO33AA26 BZVDDAB1 ECC4AB2 VDDIO33AB3 N/CAB4 AD[29]AB5 AD[26]

AB6 AD[20]AB7 AD[18]AB8 N/CAB9 FRAME/AB10 N/CAB11 N/CAB12 N/CAB13 AD[6]AB14 AD[2]AB15 C_BE[4]/AB16 AD[1]AB17 N/CAB18 AD[61]AB19 N/CAB20 VDDIO33AB21 AD[48]AB22 VDDIO33AB23 N/CAB24 VDDIO33AB25 AD[32]AB26 N/CAC1 ECC2AC2 GNT/AC3 AD[28]AC4 AD[31]AC5 AD[25]AC6 VDDIO33AC7 AD[23]AC8 AD[16]AC9 C_BE[2]/AC10 TRDY/AC11 PARAC12 C_BE[0]/AC13 N/CAC14 AD[0]AC15 AD[5]AC16 ACK64/AC17 C_BE[5]/AC18 AD[63]AC19 VDDIO33AC20 AD[59]AC21 AD[49]

AC22 AD[43]AC23 AD[42]AC24 AD[37]AC25 AD[40]AC26 AD[33]AD1 VDDIO33AD2 VDDIO33AD3 PLLVDDAD4 N/CAD5 AD[21]AD6 VSSAD7 VSSAD8 AD[17]AD9 N/CAD10 VDDIO33AD11 VSSAD12 VSSAD13 AD[9]AD14 AD[3]AD15 VSSAD16 VSSAD17 REQ64/AD18 N/CAD19 AD[60]AD20 VSSAD21 VSSAD22 AD[45]AD23 AD[53]AD24 AD[51]AD25 AD[41]AD26 VDDIO33AE1 VSSAE2 AD[27]AE3 IDSELAE4 AD[24]AE5 SERR/AE6 VDDIO33AE7 VDDIO33AE8 AD[15]AE9 N/CAE10 AD[14]AE11 VDDIO33



Figure 4 LSISAS1068 636 EPBGA-T Diagram (Top View)

Package Drawings

The LSISAS1068 uses a 636 EPBGA-T package. The package code is5Y. Figure 5 provides the package drawing.


Figure 5 JZ02-000015-00 (5Y) Mechanical Drawing (Sheet 1 of 3)

Important: For board layout and manufacturing, obtain the most recent engineering drawings fromyour LSI Logic marketing representative by requesting the outline drawing for packagecode 5Y.


Figure 5 JZ02-000015-00 (5Y) Mechanical Drawing; Bottom View (Sheet 2 of 3)



Figure 5 JZ02-000015-00 (5Y) Mechanical Drawing; Bottom View (Sheet 3 of 3)



Notes

AP/DBPrinted in USA

Doc. No. DB08-000240-04

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LSI Logic Corporation reserves the right to make changesto any products and services herein at any time withoutnotice. LSI Logic does not assume any responsibility or lia-bility arising out of the application or use of any product orservice described herein, except as expressly agreed to inwriting by LSI Logic; nor does the purchase, lease, or useof a product or service from LSI Logic convey a licenseunder any patent rights, copyrights, trademark rights, or anyother of the intellectual property rights of LSI Logic or ofthird parties.

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Purchase of I2C components of LSI Logic Corporation, orone of its sublicensed Associated Companies, conveys alicense under the Philips I2C Patent Rights to use thesecomponents in an I2C system, provided that the system con-forms to the I2C standard Specification as defined by Philips.

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