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Low Voltage Single-Stage Amplifierwith Wide Output RangeYang WANGPeking University, Beijing 100871,Chinaywang@pkmedu.cn

Abstract: A single-stage wide output amplifier capableof operating at minimum supply voltage has beendescribed. The simple circuit with low voltage currentmirrors is placed between both input differential pair andpush-pull output for achieving internal low impedancenodes and minimum supply voltage. This amplifier canbe available to work at supply voltage around 1 V forstandard CMOS processes.

I. In troduct ionAs feature size of transistors is scaling down step by

step and portable systems are gaining more importancein electronic products, more and more circuits are beingdemanded to be able to operate in low supply voltageenvironments, which has resulted in researchers'attention paid to 1-Volt electronics"]. Theoretically, theminimum supply voltage can be reduced to a thresholdvoltag e (V,) plus tw o saturation vo ltages (VDSat) forwell-design CMOS low voltage circuits, i.e.,

This value turns out to be around 1V for standard CMOSprocesses.Amplifiers as the most commonly basic buildingblock in analog and mixed-mode circuits have beenextensively investigated for quite a long time. A typicalamplifier that can meet the demand for the minimumsupply voltage is the folded cascode structure in theexisting simple amplifier^[^-^^. However, class-A outputis employed and output voltage swing is limited to nomo re than VDD-3VDS- for this stru ctur e. A single-stageamplifier with low voltage current mirrors (LVCMs) andpush-pull output has been described in this paper so as toobtain the minimum supply voltage, large output rangeand wide bandwidth. After brief description offundamental working principle, analyses oncharacteristics have been carried out and someapproximate relations among the performance and designparameters have been given. Moreover, several of majorissues relating to design have been discussed. As aspecific example, a 1-V amplifier has been designed andsimulated with SPICE.II. Topology of the Amplifier

The block diagram of the low voltage amplifier isgiven in Fig.1, which consists chiefly of the inputdifferential pair, intermediate circuit and push-pulloutput. To achieve the minimum supply voltage, theamplifier requires the intermediate circuit to be able tooperate at the low supply voltage satisfied Eq. (1). Also,to have first-order frequency response, i.e., to formsingle-stage structure, the amplifier has to involve theintermediate circuit with internal low impedance nodeswith respect to small signals. Thus a high impedancenode can b e kept only at the output terminal.

V DD

- 8 . . t . . . .: ,IntermediateCircuit :+< s. . . . . . . . .

GN DFig. 1.Th e block diagram of structure

The typical building blocks applied to theintermediate circuit are usually current mirrors. Since theinput circuit is composed of a differential pair loaded bythe diode connected MOS transistors in the conventionalbalanced amplifier with three simple current mirrors anda single-ended the minimum supply voltage ofthis input differential pair is determined byVDDmin=VGSload+lVDSsatl I+lVDSsatld

where V Gsload s gate-source voltage fo r the diodeconnected MOS transistor (not to draw out in Fig.l),V D S ~ ~ Ind VDSsatl3 are the saturation voltages for inputand tail current transistors respectively. Therefore, theminimum supply voltage for this conventional balancedamp lifier is at least V+3VDssat. It is larger than thatgiven by Eq. (1) even though this structure can meet therequirement of single-pole well.

Fig. 2 represents the overall amplifier working atminimum supply voltage. Transistors, T3, T5, T9 and TI ,,constitute a LVCM"'*' with multiplication factor B, andso do transistors, T4, T6, Tl o and T I*. The LVCM instead

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of the simple current mirror in the conventional balancedamplifier acts as the load of the input differential pair.Because the voltages at nodes, 4 an d 5 , are reduced fromV os ld to V D S ~ ~ ,he minimum supply voltage needed bythe input differen tial pair isVDDmin==(Vl+2VDSsar, 3vDSsatl

For standard CMOS processes, V, is generally largertha n VDS~~, ,o the VDD- satis fies Eq.(1).The minimumsupply voltage of the intermediate circuit is the same asthat of the input differential pair owing to LVCM s. Theminimum supply voltage of push-pull output is~ ~ x { V G S ~ ,Vcss l , ~VDSS~~}.t is normally smaller thanthat of the input and interm ediate circuits. As a result, theminimum attainable supply voltage of this amplifier isconsistent with the Eq.(l), only V, is determined bymaximum of VTnand IVTpl.

- . . . .. . . . . VD D Node Resistance4, l/[gm9gm3(rdss//rdsll)l8,9 l/gni3

. . . . . . . . . . . . . . . . . . -

GNDFig. 2. Th e low voltage amplifier

Node Resistance1gm77 rdsd/rds8

III. Analyses of PropertiesBeing in the saturation region, transistors, TI,z andTI3,demand that input comm on-mode voltage (V,,) ha s

to be in the range:& G C F E - ~ v r i 5vIcM v,, -Jzr,rS;;-JK 'Z - l vn lKeeping output transistors, Ts nd Ts, in saturationrestricts the output voltage to the range:

jzB7;r/-s;;vent 5 vDD -J%ZGFor LVCM, an often concerned problem is themaintenance of T3 and T9 in saturation due to thecascode transistor. It i s unnecessary that Tg is larg e sizeas long as its biasing current (Ill) is a small constant.However, making T3 in saturation must limit its draincurrent to the range:

< +VG9 -vr9-E12 (2 )where p=clC,(W/L). In other words, for a given tailcurrent (Il3). the T3 ought to have aspect ratio enough tokeep it in the saturation region. In addition, to e nsure T3

1an-' ( )+tad(---2nC6GBW 7cc6GBWg m l gm 1where C,, is parasitic capacitance at node n. Incomparison with the conventional balanced amplifier, theIll an d 112 biasing LVCMs will impose on the phase

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marg in owin g to gm9(rdsbs4//Idsl elevan t to them . T hephase shift caused by node 4(5) reaches the minimumwhen Tg and Tlo arrive to the weak inversion.For the n oise sources, the casc ode transistors, Tg andTlo , may be visualized as source followers, the draincurrents of which are directly controlled by the biascurrents, so output noise currents of the cascodetransistors are zero. Moreover, the noise generated byTI3 is common-mode signal. With canceled by taking adifferential output, it does not contribute to the outputvoltage. Consequently, the transistors contributing to theoutput voltage are TI,^, T3,4, T5,6, T7,8, and T11.12. Forthermal noise, V: is equal to 8k TAf/3gm l. Th e totalequivalent input noise level is given by

-

where AV1=(v8-v9)/vin=gml/gd.otice that the T I noisecontributing to output is dependent on gmll/gml.The totalequivalent input noise can be reduced as increasing A,]and/or B.A summary of key properties of this amplifier, whenall transistors operate in the saturation region, is given bythe approximate expressions in Table 2.

Table 2. Key properties of the amplifierAvo Bgml(rdsd/rdsdG, Bgmlrout rdsd/rdsaS R B W C LGBW B ~ ~ I / ~ N C ~ + C L )fnd89 g d 2 7 Gfnd45 gm9gndrds9//rdsl )/27Cc4f n d F f z d 2 gmd2xc6fd7 1/27C (CL+c7)(rdsd/rdsdVDD~- v+2vDSsatVICM,rmge VDD'~VDSsat13~-VDSsaO-~vDSsatlvout, swing, max VDD'2VDSndnPstatic (lfB)(I13+2II 1)VDD

PM Eq. (4)

NnenlwJ Eq . ( 5 )HJ33 PiV?/(32113)B is current ratio of load current mirrors

IV.Design ConsiderationsWith the intention of maintaining the current sourcetransistors, T I1 and Tlz, in saturation, the large aspectratios of T3 and T4have to be taken for reducing voltagesat nodes, 8 and 9. On he other hand, considering the T5in saturation, (W/L)3 should also be designed large

enough to ensure V Ds5>VGss-VT5 or a givenmultiplication factor B. Notice that (W/L), and (WQ,if too large, make A,] decrease, and this will causeperformance deterioration of the total DC gain and noise.For the simple current mirror comp osed of T7 and T8, thelarger the (W/L)7 and (W/L)g become, the easier it is tokeep T5 n saturation due to a rise of voltage at node 6.With due regard for appropriate gain and powerdissipation, the current I l l equal to II 2 s usually biased toa small constant. Also, one of inp ut transistors will be offwhen input differential voltage is large. The smallestcurrent through o utput transistors is equal to B II1 . Them inim um V D ~f output transistors depends in part onBIII . n order to have maximum output swing, both Illan d II2 should be designed as small as possible too.Another merit of the decrease in Il l is the increase ingmgrdsg. Thi s is be neficia l to the phase margin (see

The voltages at nodes, 4 and 5 , which have a bearingon the operating region of T3 and TA , are partiallydetermined by the gate voltages of Tgand Tlo.The bodybiasing effects do not occur if the substrates of T9 andTlo are connected to the sources for P-well process. It isease to make T3 and T4 n satur ation th at VDS, and VDs4are increased in this case.SR (slew rate) and GB W are directly proportional toB. With increasing B, we can obtain a large SR andGBW, but PM will decrease if B is taken too large. Inaddition, in order to guarantee the output noisedominated by the noise of input differential pair, thelarger the gain AV1, the better. On the contrary, thereduction in gd will increase resistance at node 4 anddegrade the phase margin. For those reasons acompromise should be made for parameters of B and A V1during design.Th e DC gain is relevant to transconductance (g,,) ofinput transistors and output resistance (rout). To haveadequate gain, the amplifier should possess enough gmland chann el length of output transistors.In careful consideration of power dissipation, theconfiguration of amplifier may be employed that has(W/L)3=(W/L)5 and (W /L)s=B(W/L)7 under the idealconditions. Nevertheless, the precision of current mirrorsbecomes w orse for low supply voltage. This asymm etricconfiguration will dramatically affect the performance ofthe amplifier.

Eq44)) .

V. Design Example an d Simulation ResultsA 1-V amplifier has been designed as an exampleusing parameters of the MOSIS P-well 2.0um-CMOS

process. The threshold voltages are -0.7V and 0.W orPMOS and nMOS respectively. For a given SR=IV/us,BII3 should be equal to CLS R=~ OUA s a rough

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estimation for capacitance load C,=lOpF. Having atrade-off between the transconductance and phasemargin, we took B=2. Thus II 3 was about 5uA. If thedesigned GBW was 3M&, the aspect ratio of inputtransistors was estimated to be about 100 fo rKP,=18uAN2. After a compromise between phasemargin and noise was made, the gain A,] was chosen as2, i.e ., g,-,=g,12. Supposing I1was approximately equalto I3an d KP,,=2.5KPp, he (W LJ3 was about 10. Due toB=2, the (W/L)5 was equal to 20. If Ill=112=113/10=0.5uAand (W/L)9=6, he feasible gate voltages (V G ~nd VGIO)of cascode transistors in the LVC Ms were from 1.OV to1.5V by Eq. (3). Vm and VGlo were therefore taken asIV(=VDD).The maximum input current for LVCM was9uA from Eq. (2). This was larger than II3+Ill=5.5uA.Consequently, the LV CMs could always be available forthe bias currents.

604 0 -

20[a1

-2 0-40-60

Table 3. Transistor sizesTransistor W/L Transistor W/L

4Od2u

All transistor sizes for the design are shown in Table3. The simulated frequency response is shown in Fig. 3.

0 -

-

Fig. 3. Frequency responseThe chief simulation results predicting performancesof the amplifier are summarized in Table 4 fo r 1V supplyvoltage.

Nthermal 20nVm/./HzPSm' 28dB(f=GBW)Psm- 48dB(f=GBW)1dB

G m 217uAN 6uAvTn=o.8v,vTp=-o.7v.L=lOpF, VDD=lv

VI. ConclusionBecause a circuit with low voltage current mirrors isplaced between both input differential pair and push-pulloutput, the amplifier with minimum supply voltage hasbeen obtained, which has first-order frequency responseand symmetrical loads for the input transistors. Theamplifier working at 1V has been designed andsimulated by SPICE for standard CMOS processes.Despite the fact that low voltage current mirrors lead intwo extra nodes and rise slightly up in power dissipation,those weaknesses can become so small by means ofoptimal design that they have a weak influence on th e

main performances as illustrated in our example.References[ l ] J. Huijsing, R. Plassche, and W. Sansen., Eds.,Analog Circuit Design: 1-Volt Electronics, Mixed-Mode System, Low-Noise and RF Power Amplij?ersfo r Telecommunication, (Kluwer AcademicPublishers, Boston/Dordrecht/London, 1999), p. 1[2] R. Castello, F. Montecchi, F. Rezzi, and A.Baschirotto, IEEE Trans. On CAS-I, 42, 11, 82 7(1995)[3] S. Rabii and B. A. Wooley, IEEE J. Of SSC, 32,6,783 (1997)[4] Y. Wang, Proc. of China Fifieenth Con$ on Circuitsand Systems, (Guangzhou,China,l999), p.159[5 ] E. Sanchez-Sinencio and J. Silva-Martinez, IEEProc.-CDS, 147,1,3(2000)[6] K. Laker and W . Sansen, Design of AnalogIntegrated Circuits and Systems, (McGraw-Hill Inc.1994), p.575[7] A. Baschirotto and R. Castello, in Analog CircuitDesign, eds . ,J. Huijsing, R. Plassche and W. Sansen(Kluwer Academic Publishers, Boston/ DordrechuLondon, 1999), p.69[SI V. Peluso, M. Steyaert, and W. Sansen, Design ofLow-Voltage Low-Power CMOS Delta-Sigma A DConverters, (Kluwer Academic Publishers, Boston/Dordrechtl London, 1999), p.61

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