Low Power RF/Analog Amplifier Design

Low Power RF/Analog Amplifier Design

Tong ZhangAuburn UniversityTong Zhang

Auburn University

Motivation and Design Objective

• MotivationDesign a low power CMOS LNA (Low-Noise Amplifier)

f0 2.4 GHz

NF < 2.5 dB

Vdd 2 V

S12 < -25 dB

Gain > 15 dB

Design Objective

My Work

• This Work1. Design a 2.4 GHz cascode CMOS LNA.

2. Design a low power CMOS LNA with comparable performance.

3. Comparison between the two LNAs.

Tools and Techniques

• ToolsVirtuoso Schematic Composer and Spectre

Simulator from Cadence Design Systems,

Inc.

• Techniques

0.13 µm CMOS process

Circuit Diagram Comparison

Traditional CMOS LNA Low Power CMOS LNA

RFin

out

Ls

Lg

Vg1

Vg2

VDD=2V

Cout

M1

M2

C1

P1

Rout Lout

Ld C2

RFin

out

Ls

Lg

Vg1

Vg2

VDD=2V

Cout

M1

M2

Rout Lout

Schematic of Traditional CMOS LNA

Schematic of Low Power CMOS LNA

Circuit Description

• Traditional CMOS LNA1. A inductance network (Lg, Ls ) is used for are

used for input matching.

2. A RLC filter network (Lout, Cout, Rout ) is used for selecting the output frequency.

3. Vg1 is biased at 0.53V; Vg2 is biased at 1.7V;Vdd is biased at 2 V.

Circuit Description (cont’)

• Low Power CMOS LNA1. M2 and P1 operates as inverter-type amplifier

stages to make LNA high linearity due to its symmetric structure.

2. C1 couples the ac signal amplified by M1 to M2, while the source of M2 is bypassed by C2.

3. 3. Vg1 is biased at 0.5V; Vg2 is biased at 1.3V; Vdd is biased at 2 V.

Simulation Result

• Input reflection coefficient (S11)

• output reflection coefficient (S22)

Traditional CMOS LNA Low Power CMOS LNA

Simulation Result (cont’)

• Power gain(S21)

• noise figure (NF)

Traditional CMOS LNA Low Power CMOS LNA

Simulation Result (cont’)

• Reverse isolation(S12)

S12=-40dB <-20 S12=-49.3dB<-20

Traditional CMOS LNA Low Power CMOS LNA

Simulation Result Summary

Traditional LNA Low Power LNA

Gain (S21) 20 dB 22 dB

NF 1.7 dB 2.8 dB

S12 -40 dB -49 dB

Power 7.23 mW 4.3 mW

Power Consumption

Traditional CMOS LNA

P = Idd x Vdd = 3.668mA x 2V = 7.23 mW

Low Power CMOS LNA

P = Idd x Vdd = 2.147mA x 2V = 4.3 mW

Power Reduction = 41.5%

Conclusion

Highlights• A current reuse technique is used to decreas

e power dissipation with increasing amplifier transconductance for the LNA.

In my project, for nearly the same power gain, by decreasing gates bias we get 41.5% power reduction

• An inverter-type amplifier which has a symmetric structure is used to achieve high linearity for the LNA (not discussed)

Conclusion (cont’)

What need to improve?• Input impedance was not well matched, which

means the ac signal of the input will not be able to be fully delivered to the output.

• Noise figure shows that the noise of output is a little bit large.

A different input matching as well as output matching topology may improve the efficiency and minimize noise of the LNA

Reference

• Ickjin Kwon and Hyungcheol Shin , “Design of a New Low-Power 2.4 GHz CMOS LNA” , Journal of the Korean Physical Society, Vol.40, No. 1, Jan. 2002, pp. 4-7.

• John D. Cressler and Guofu Niu, “Silicon-Germanium Heterojunction Bipolar transistors”, Artech House, inc. Boston, 2002.

• Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.

THANKS!