low power radiation tolerant cmos design using...
TRANSCRIPT
Low Power Radiation Tolerant
CMOS Design using Commercial
Fabrication Processes
November 5, 2010
Amir Hasanbegovic ([email protected])Nanoelectronics Group, Dept. of Informatics, University of Oslo
Overview
• Introduction• Low power design, radiation environments and effects
• Methods• Transistor structures, circuit- and architectural level
hardening, layout considerations
• Design Flow for radiation tolerant ASICs
• Summary
• Low power design techniques• Multiple supply voltages
• MTCMOSMultiple threshold voltage CMOS.
• Level shifters• Subthreshold to above threshold
voltage level shifting
• Radiation hardened by design (RHBD) Methodologies• Circuit level hardening
• Architectural level hardening
• Layout considerations
• => Low power, radiation tolerant circuits
Introduction
Introduction
• Radiation environments• Trapped radiation belts
• Protons, electrons
• Galactic cosmic rays• High energy particles
• Solar flares
• Terrestrial radiation• Cosmic ray induced neutrons
• Radiation effects (soft/hard errors)• Single event transients (SET)
• Single event upsets (SEU)
• Multiple bit upsets (MBU)
• Single event latchup (SEL)
• Total ionizing dose effects (TID)
Particle induced charge
collection causing voltage
fluctuations in circuit nodes
Introduction
• Why VHDL synthesis on ASICs for radiation tolerance
applications?
• Motivations• TID induced leakage currents and Vth shifts in new tech. nodes.
• Power consumption
• Design flexibility on ASICs.
• Speed • Radhard by process technology lag (2-3 generations)
• Challenges• Critical charge, Qcrit
• the amount of charge required to upset a capacitive node in a circuit
• Increased design density
Transistor -Structures and -Properties in
RHBD Applications
• TID induced leakage currents in standard transistors• Inter device leakage
• Intra device leakage
• Annular layout transistors• STI sidewalls do not exist between source and drain
in the annular structure => less leakage currents
• May be relevant for low voltage operation• ION/IOFF ratio
Architectural level hardening
• Triple modular redundancy (TMR)• Temporal Sampling
• Majority voters
• Dual modular redundancy (DMR)• Dual interlocked cell (DICE)
• Guard gates (C-elements)
• Interlocked combinational logic
Circuit level hardening
• Dual data inputs
• Dual clock
• A=C, B=D
• SEU ”immune”
• A SET event on any single node in a DICE configuration is not able to trigger the feedback due
to the fast recovery time imposed by the interlocked node pairs.
DICE latch
C-elements
SET and SEU tolerant layout technique
• Layout considerations for radiation tolerance• Angle of particle impact
• Interleaving of critical nodes
• Inter device leakage• Guard bands
• Spatial distribution
Design Flow for radiation tolerant ASICs
Synopsys SentaurusTCAD
Cadence Virtuoso schematic
Cadence Virtuoso layout
VHDL synthesis
Cadence SoC Encounter RTL Compiler
Low level transistor-/structure characterization
SET, SEU, MBU, TID induced leakage, ++
Cell simulationsCharge injection
simulations/scriptsCell characterization
Post layout simulations Cell characterization
VHDL model Post synthesis analysis Static timing analysis
Floorplan/ power-planning
Macro-/Standard cell placement
Timing analysis and refinement
GDSII
AMS 0.35 um, TSMC 90 nm, STM 65 nm
45 nm available in 2011 (?)
A SOI process is under consideration
Setup for radiation testing
-Soft error detection using a
Spartan 3 development board
- VHDL, MATLAB
Summary
• Design of digital circuits• Robust low power, radiation tolerant
• Radiation tolerant standard cells including level shifters
• Soft error characterization setup
• Possibility for• On-chip MEMS/RF MEMS (“CMOS MEMS”)
• Mixed-signal circuits
Summary
• Thank you for your attention
• Questions?