low power design – part i introduction and vhdl...
TRANSCRIPT
Motivation for Low Power Design
Low power design is important from three different reasons
• Device temperature– Failure rate, Cooling and packaging costs
• Life of the battery– Meantime between charging, System cost
• Environment – Overall energy consumption
ISSCC, Feb. 2001, Keynote
“Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now.
“Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .”
Patrick P. Gelsinger Senior Vice PresidentGeneral ManagerDigital Enterprise Group INTEL CORP.
Distribution of energy dissipation across pipeline stages
In order processor:– Fetch: 37%– Decode: 18%– Issue: 14%– Execute: 9%– Memory: 15%– Writeback: 7%
Low-Power Design• Design practices that reduce power
consumption by at least one order of magnitude; in practice 50% reduction is often acceptable.
• Low-power design methods:– Algorithms and architectures– High-level and software techniques– Gate and circuit-level methods– Test power
Power Projections
40048008
80808085
8086
286 386 486Pentium®
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Powe
r Den
sity
(W
/cm2)
Hot Plate
NuclearReactor
RocketNozzle
Sun’sSurface
Basics
• Power – Direct impact on instantaneous energy
consumption and temperature• Energy
– Power integrated over time is energy and impact on battery shelf life and environment
E(T) = ∫ P(t) dt0
T
Basics
• Dynamic– Transition – Short circuit
• Leakage– Sub-threshold leakage– Diode/Drain leakage– Gate leakageAt 250nm leakage power was only 5% but it is increasing rapidly as geometries decrease
Dynamic Energy Consumption
Energy/transition = CL * VDD2 * P0→1
PowerSwitching
= α * CL * VDD2 * f
Vin Vout
CL
VddTransition Power
PowerSwitching
is called Dynamic Power.
Low Power Design Approaches• System design: Top down
– Effective low power transformations in synthesis
– Fast estimation techniques for an effective exploration of a large design space
• Cell library design: Bottom up– Low power circuit design techniques– Accurate estimation – Effective models for synthesis tools
Design Levels
• System• Algorithmic/Module• RTL• Gate• Circuit• Device technology
System Level DesignSame embedded application running on different systems consume significantly different amounts of power
• System partitioning
• Buses/Memory/IO devices /interfaces
• Choice of components
• Coding
• System states (sleep/snooze etc)
• DVS/DFS/..
Algorithmic/sub-system Level
• Choice of algorithm (operation count etc.)• Word length choices• Module interfaces• Implementation technology
– SW: Processor selection– HW: ASIC/FPGA/..
• Behavioral synthesis constraints and trade-off
RTL
• Pipelining/retiming• Module selection• Multiple frequency and voltage islands• Reduction in switching activity through
transformations
Gate Level
• Clock gating• Power gating• Clock tree optimization• Logic level transformations to reduce
switching activity
Circuit Level
• Transistor sizing• Power efficient circuits• Cell design• Multi-threshold circuits
Device Technology
• Multi-oxide devices• Multiple “cell types” on a single substrate
– Logic, SRAM, Flash etc. • Support for many other low power design
techniques (multiple thresholds, multiple voltages, multiple frequencies etc.)
VHDL for Low Power• Guidelines and good practices for writing
efficient RTL code from a low-power standpoint
• Techniques:– Glitch Reduction– Clock gating– LP for FSMs– LP for Datapaths
• Precomputation• Guarded Evaluation
VHDL for Low Power• Glitch Reduction
– Due to converging combinatorial paths with different propagation delays
– Glitches are not an issue for power consumption only
• Also affect the signal integrity and the timing closure with effects like dynamic cross talk
– Example: multiplexers for a full-adder
VHDL for Low Power• Clock Gating
– Disable or suppress transitions from propagating to parts of the clock path under a certain condition computed by clock gating circuits
– Example: Clock gating register file
VHDL for Low Power• Low Power for FSMs circuits
– Gate-clock FSM for freezing the clock and the input signals when staying at the same state
– State encoding based on gray code for minimizing the hamming distance on the transitions from one state to another
• Same challengers of branch prediction techniques!
VHDL for Low Power• Low Power for Datapaths
– Precomputation design techniques identifying a logic condition on some inputs of a combinational circuit for which the output does not vary
– Guarded evaluation is applicable to embedded combinational blocks from which outputs are in idle condition
• Insertion of transparent latches
Conclusions• Low power is one of the most important
issues for processor designers• Conflicting goals sometimes• There are previous research considering
low power on instruction encoding• Curiously, current research is focusing on
accelerators along with the datapath to power reduction