Analog Integrated Circuits and Signal Processing, 25, 235±244, 2000

Low-Power Area-Ef®cient Pipelined A/D Converter Design Using aSingle-Ended Ampli®er

DAISUKE MIYAZAKI{(STUDENT MEMBER), SHOJI KAWAHITO{ ANDYOSHIAKI TADOKORO{(MEMBERS)

Department of Information and Computer Sciences, Toyohashi University of Technology, Toyohashi-shi, 441±8580, Japan

Received June 24, 1998; Revised September 10, 1998

Abstract. This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a

single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits

has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor

mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated

cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient

design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less

than 12 mW at 20 MSample/s.

Key Words: pipelined A/D converter, single-ended amplifier, low power design, portable video device

1. Introduction

Reduction of power dissipation in high-speed A/D

converters is a major design issue in many applica-

tions such as portable video devices. Advanced

CMOS technology allows us to reduce the power

dissipation of high-speed A/D converters [1]. Future

trend of battery-powered portable devices demands

further reduction of the power dissipation. A

pipelined A/D converter is one of promising

candidates to meet the requirements on low power,

high speed and high resolution. For example, a 10 b

20 Msps 35 mW A/D converter has been reported [2].

Differential schemes are commonly used in the

design of pipelined A/D converters, because of the

easiness of realizing both addition and subtraction of

a reference voltage in each pipeline stage and noise

immunity. The power consumed in the pipelined A/D

converter is mainly due to the DC bias current of

differential ampli®ers. The capacitor mismatch is the

dominant error source of capacitor-based pipelined

A/D converters, and this limits the minimum power

and the maximum speed, as well as the actual

resolution. These facts suggest us the possibility of a

new type of a low-power pipelined A/D converter

with a reduced bias current and a low capacitor

mismatch sensitivity.

This paper proposes a low-power high-speed A/D

converter using a single-ended pipeline scheme. The

proposed new single-ended pipeline algorithm

reduces the capacitor mismatch sensitivity compared

to a straightforward single-ended design. Fully

differential schemes provide better power supply

rejection and tolerance to crosstalk noise from digital

circuits. This property allows us to realize high

precision A/D converters of more than 12 b. Despite

of the large sensitivity to the crosstalk noise, single-

ended schemes are sometimes used in 8±10 b high-

speed A/D converters such as two-step ¯ash A/D

converters, where chopper-type single-ended com-

parators are major components. The proposed single-

ended A/D converter is intended to realize medium

resolution of 8±10 b. The designed single-ended

ampli®er using a dynamic-biased regulated cascode

scheme has a small bias current with high gain, high

output swing, and high switching speed. These

properties allow us to design a low-power high-

speed pipelined A/D converters. Total power dissipa-

tion can be greatly reduced compared with the

conventional differential pipelined A/D converters.

Copyright, 1999, IEICE, reprinted with permission from IEICE Transaction.

2. Architectures of CMOS Pipelined A/DConverters

A block diagram of a typical pipelined A/D converter

is shown in Fig. 1 [3]. This 1-b-per-stage pipelined A/

D conversion scheme is based on a reference non-

restoring algorithm [4]. The pipeline begins with a

sample-hold ampli®er (SHA) and is then followed by

multiply-by-two (MBT) stages. Each MBT stage

consists of a multiply-by-two ampli®er with refer-

ence addition/subtraction and a comparator to

determine the respective output bits. The SHA and

the MBT stages are designed using switched

capacitor con®gurations.

The analog input voltage is ®rst sampled and held

at the S/H section. The input Vin is limited to the

range between ÿVref and Vref . First the sampled input

signal is compared with 0, and the MSB (most

signi®cant bit), D0 is determined. Namely if Vin � 0,

D0 � 1, and otherwise D0 � 0. In the subsequent

each stage or ith stage �i� 1, . . . , Nÿ 1� for an N-bit

converter, the operation is given by

Vout �26Vin ÿ Vref �if Diÿ 1 � 1�26Vin � Vref �if Diÿ 1 � 0�

��1�

where Diÿ1 is the bit output of the previous stage. The

relation between Vout and Vin is illustrated in Fig. 2.

For ÿVref � Vin � Vref , the condition, ÿVref �Vout � Vref , is always met so that the same module

and the same reference voltage can be used in each

pipeline stage. The bit output is determined simply

as

Di � 0 �if Vout50�1 �if Vout � 0�

��2�

In the pipelined A/D converter, the total perfor-

mance is dominated by the multiply-by-two

ampli®er, rather than the comparator. The power

dissipation and the switching speed greatly depend on

the choice of a unit capacitance used for the multiply-

by-two ampli®er. The unit capacitance has to be

chosen to meet the requirements on the non-linearity

error dominated by the capacitor mismatch error.

In the following subsections, two types of pipeline

stage designs using a differential and a single-ended

schemes are compared with respect to the sensitivity

to the capacitor mismatch error.

2.1. Differential Pipeline Stage

Fully differential switched capacitor circuits are

commonly used for the pipelined A/D converters.

The operation of a typical differential multiply-by-

two ampli®er used in the pipeline stage is shown in

Fig. 3. In the sampling phase, the input is sampled at

the bottom plates of all capacitors as shown in Fig.

3(a). In the next ampli®cation phase, two capacitors

are connected to the op-amp feedback paths, and the

other two capacitors are connected to the reference

voltage as shown in Fig. 3(b). At this time, the

reference voltage can be either Vref or ÿVref

depending on the previous bit output. The relation-

ship between the input and the output is given by

Vout � 1� 1

2�ad1 � ad2�

� �Vin

+1

2�ad1 � ad2�

� �Vref �3�

where ad1 � C1=C2 and ad2 � C3=C4 are the capa-

citor ratios which contain capacitor mismatch errors.

The choice of addition or subtraction of Vref follows

the same rule as equation (1). Ideally ad1 � ad2 � 1,Fig. 1. Block diagram of a typical pipelined A/D converter.

Fig. 2. Transfer characteristic of the pipelined A/D converter.

236 D. Miyazaki, S. Kawahito and Y. Tadokoro

so that the ideal transfer characteristic is given by

equation (1). The change of polarity of Vref to

perform both addition and subtraction can easily be

done by changing the connection to the differential

ampli®er. This is one of merits of the fully

differential scheme in pipelined A/D converters.

The capacitor mismatch causes the deviation of the

output from the ideal value. Because of the correla-

tion between the coef®cients of the Vin and Vref , this

scheme has low sensitivity to the capacitor mismatch.

For instance, if Vin � Vref , the effect of the capacitor

mismatch is completely cancelled out. The maximum

capacitor mismatch deviation occurs when Vin^0.

In this scheme, the output is independent of the

offset deviation of the ampli®er used. This is another

merit of this pipeline stage algorithm.

2.2. Straightforward Single-Ended Pipeline Stage

The power dissipation of the pipelined A/D converter

is greatly dependent on those of the ampli®er used in

the multiply-by-two stage due to the DC bias current.

In order to reduce the DC bias current, a single-ended

SC technique using a cascode ampli®er is useful. To

do both addition and subtraction of the reference, a

typical technique in single-ended SC circuits is to use

two different charge transfer modes in SC circuits;

inverting and non-inverting. Fig. 4 shows the straight

forward design of a single-ended multiply-by-two

stage. To perform the reference subtraction, the

capacitor C3 is ®rst connected to a common voltage,

Vcom, by setting f4 � 1 during f1 � 1, and then

connected to Vref by setting f3 � 1 during f2 � 1.

The reference addition is performed by ®rst con-

necting C3 to Vref during f1 � 1 and then connecting

C3 to Vcom during f2 � 1. The multiply-by-two

ampli®cation is performed simply by the capacitor

ratio of ��C1 � C2�=C0�. Hence the transfer char-

acteristic is given by

Vout ÿ Vs2 ��as1 � as2��Vin ÿ Vs1�+as3�Vref ÿ Vcom� �4�

where as1 � C1=C0, as2 � C2=C0 and as3 � C3=C0

are capacitor ratios, Vs1 is the short-circuit output of

the previous pipeline stage, and Vs2 is the short-

circuit output of own pipeline stage. Since this

multiply-by-two stage acts as a correlated double

sampling scheme, the offset deviation of the ampli®er

is cancelled out as clearly seen from equation (4). In

the ideal situation without capacitor mismatch,

as1 � as2 � as3 � 1, and the transfer characteristic

corresponds to equation (1).

This single-ended scheme has a large capacitor

mismatch sensitivity due to no correlation between

coef®cients given by the capacitor ratio. Because of

this property, a larger capacitance has to be used to

obtain the same precision as the differential type.

Despite of the simple single-ended scheme, therefore,

we can only expect a marginal reduction of power

dissipation.

Fig. 4. Straightforward single-ended multiply-by-two stage.

Fig. 3. Operation of the differential multiply-by-two stage.

Low-Power Area-Ef®cient Pipelined A/D Converter 237

3. A/D Converter Design Using an ImprovedSingle-Ended Pipeline Scheme

3.1. Multiply-by-Two Ampli®er

Fig. 5 shows a single-ended multiply-by-two pipeline

stage with an reduced capacitor mismatch sensitivity.

The timing diagram is shown in Fig. 6. In the case

Diÿ 1 � 1, the capacitors, C0 and C1 are charged by

Vin during f1 � 1, and then the input of C1 is

connected to Vref and C0 is connected in the ampli®er

feedback path during f2 � 1. In this case the output

is given by

Vout � �1� as1�Vin ÿ as1Vref �5�where as1 � C1=C0 is the capacitor ratio. Hence the

reference subtraction can be easily realized in the

single-ended scheme. In this situation, the output has

the same capacitor mismatch sensitivity as that of the

differential type. To perform a reference addition, a

special consideration is necessary. The transfer

characteristic of the single-ended pipeline stage is

shown in Fig. 7. For the input range of 2Vcom ÿ Vref

to Vref , the output is retained in the same range as of

the input. In this biased transfer characteristic, the

reference addition in the differential scheme corre-

sponds to the subtraction of 2Vcom ÿ Vref . In the case

Diÿ 1 � 0, therefore, the capacitors, C0 and C1 are

charged by Vin and C2 is charged by Vref during

f1 � 1. Then C1 and C2 are connected Vcom, and C0

is connected to the feedback path of the ampli®er.

This switching operation gives a transfer character-

istic of

Vout � �1� as1�Vin ÿ �as1 � as2�Vcom � as2Vref �6�

where as2 � C2=C0 is the capacitor ratio. Compared

with the straightforward single-ended type, the

capacitor mismatch sensitivity is largely reduced.

The detailed analysis is given in Section 4.

3.2. Single-Ended Dynamic-Biased RegulatedCascode Ampli®er

A key element to implement the high-speed low-

power pipelined A/D converter is a single-ended

ampli®er. The core ampli®er used in this A/D

converter design is shown in Fig. 8. The ®nite

open-loop DC gain limits the resolution of the

pipelined A/D converter. With a ®nite DC gain of

A0, the switched capacitor multiply-by-two stage

suffers from a gain error of ÿ 2=A0, and furthermore

an additional gain error of ÿ�Cin=C0�=A0, where Cin

is the parasitic capacitance of the ampli®er input, and

C0 is the feedback path capacitance used [9]. In order

Fig. 7. Transfer characteristic of the improved single-ended

pipeline stage.

Fig. 5. Single-ended multiply-by-two stage with a reduced

capacitor mismatch sensitivity.

Fig. 6. Timing diagram of the improved single-ended pipeline

stage.

238 D. Miyazaki, S. Kawahito and Y. Tadokoro

to achieve high open-loop gain, a regulated cascode

ampli®er is employed [6]. However, in the usual

regulated cascode scheme, the voltage swing of the

output is reduced by stacking two transistors, because

the gate bias voltage of the stacked transistor is

shifted by the threshold voltage of the MOS

transistor. This cause a dif®culty to use low supply

voltage. To avoid this problem, a dynamic biasing

technique is used. In half cycle of the pipeline clock

period, the input of the ampli®er is connected to the

output to cancel the offset deviation of the ampli®er.

In this phase, the switches S1 and S2 are turned on,

and the gates of the stacked transistors, M2 and M4 is

biased to the best condition to have the highest swing

at the ampli®er output. The channel width of the

transistors, M5 and M7 are chosen as one-fourth of

that of M2 and M4 [7], respectively. When switches

are turned off, the closed-loop coupled with a

capacitor constitutes a regulated cascode ampli®er,

with maintaining high voltage swing at the output.

The dominant pole of this ampli®er is at the output,

and this ampli®er act as a single pole ampli®er, and

circuits for the regulation of bias voltage is not

sensitive to the frequency response. Therefore, the

bias current for the regulator ampli®er constituted

with M5, M6, M7 and M8 can be set to suf®ciently

small value compared to that of the cascode ampli®er

body.

Table 1 shows the simulated performance of the

designed regulated cascode ampli®er for two supply

voltages, 3 and 2.5 V. The device parameters used in

the simulation is of an assumed 0.35 mm CMOS

implementation. The load capacitance is 0.5 pF. The

pull up drive current of the output is limited by a

constant current given by a pMOS current source,

denoted as I0. The pull down drive current of the

output depends on the mutual conductance of the

nMOS driver transistor. Therefore, the single-ended

ampli®er has an excellent pull down drivability. The

bias current of the bias regulation ampli®er is chosen

as one fourth of that of the ampli®er body.

Therefore, the total DC bias current of the ampli®er

is 1:5 I0. For 2.5 V power supply, the output voltage

swing of 1.6 V obtained is suf®cient for video

applications. The unity gain frequency of about

180 MHz and the phase margin of more than 70

degree are suf®cient to have a tolerable settling time

required for a video-band sampling frequency of

20 Msps.

For comparison, a fully differential, or a folded

cascode op-amp is also designed using the similar

dynamic-biased regulated cascode scheme as shown

in Fig. 9. In this ampli®er, both the pull up and the

pull down drive currents of the output are limited by

the same amount of constant current of I0. To obtain

this drivability, the total bias current of the fully

differential op-amp is 5I0 if �1=4�I0 bias current is set

for each bias regulation ampli®er.

Table 1. Performance of the designed regulated cascode ampli®er.

Supply Voltage

Parameter 3 V 2.5 V

Open-loop gain 86.8 dB 84.9 dB

Unity-gain frequency 185 MHz 179 MHz

Phase margin 70.5 � 70.9 �

Voltage swing 2.1 Vpÿp 1.6 Vpÿp

Total bias current 300mA 300mA

Fig. 9. High-gain folded cascode ampli®er using the dynamic-

biased regulated cascode technique.

Fig. 8. Single-ended dynamic-biased regulated cascode ampli®er.

Low-Power Area-Ef®cient Pipelined A/D Converter 239

3.3. Comparator

In the designed single-ended A/D converter, a simple

chopper-type comparator shown in Fig. 10 can be

used. This type of comparator is often used for

CMOS high-speed A/D converters such as two-step

¯ash A/D converters because of its high switching

speed and simple circuit con®guration [5]. Actually a

10 b 20 Msps A/D converter using the chopper-type

comparators has been reported [1]. This A/D

converter utilizes an averaging technique to reduce

the charge injection which is the dominant error of

the comparator. The averaging technique reduces the

DNL error to 0.25 LSB, while the DNL error

becomes 1 LSB without the averaging technique.

The capacitance used in the comparator is 0.1 pF in

0.8 mm CMOS technology. From this result, we can

estimate the minimum capacitance of the compara-

tors in the designed single-ended pipeline A/D

converter. The parasitic capacitance of a CMOS

switch is halved using 0.35 mm CMOS technology,

because of the scaling of transistor sizes and gate

oxide thickness. To obtain the DNL error of less than

0.25 LSB, the capacitance of the comparator should

be larger than 0.2 pF. The chopper-type comparator

shown in Fig. 10 is simulated to estimate the power

dissipation. Using the capacitance of 0.2 pF and

2.5 V supply, the power dissipation was 0.3 mW/

stage at 20 Msps operation and with the error of

0.25 LSB.

3.4. Total Operation

In order to check the total behavior of the designed

pipeline A/D converter, circuit simulation is carried

out using 0.35 mm CMOS technology parameters.

Fig. 11 shows the simulated waveforms of an

example of the 4 b single-ended pipelined A/D

converter at 20 Msps. This result is just to demon-

strate the total behavior of the proposed scheme. For

the demonstration of the total performance, espe-

cially on the nonlinearity and SNR, the LSI

implementation will be necessary, which is a near

future subject.

4. Capacitor Mismatch Sensitivity

The capacitor mismatch is one of inevitable error

sources in pipelined A/D converters. Although a

cancellation technique of capacitor mismatch error

exists, the cancellation requires two more clock

cycles to perform a unit pipeline operation [4].

Therefore, the pipelined A/D converter algorithm

should have a suf®ciently low capacitor mismatch

sensitivity.

The differential pipelined A/D converter shown in

Fig. 3 has the lowest sensitivity to the capacitor

mismatch among aforementioned three types. From

equation (3), if the input, Vin, equals to Vref or ÿVref ,

the capacitor mismatch is canceled out. In the case

Vin � 0, the in¯uence of capacitor mismatch

becomes maximum. The errors due to capacitor

mismatch are accumulated by passing through pipe-

line stages, and cause the integral nonlinearity of the

A/D converter. Using a statistical calculation and an

approximation, the variance of the integral non-Fig. 10. Comparator.

Fig. 11. Simulated waveforms of an example of the 4-b single-

ended pipelined A/D converter at 20 Msps.

240 D. Miyazaki, S. Kawahito and Y. Tadokoro

linearity of the A/D converter when Vin is around 0

can be obtained as

s2INL �

1

22N

XNÿ1

i� 1

�4i ÿ 1�2( )

V2refs

2C

^1

3V2

refs2C �for N 4 1� �7�

where N, Vref and s2C are the number of bits, the

reference voltage and the variance of the capacitor

ratio due to mismatch, respectively. From equation

(3), the source of the capacitor mismatch error in the

differential pipeline ADC stage is only due to a single

capacitor ratio.

In the straightforward type of the single-ended

pipeline ADC stage, there are three error sources,

C1=C0, C2=C0, and C3=C0 from equation (4). The

worst case error appears when Vin is around +Vref .

The variance of the integral nonlinearity of the A/D

converter in this worst case is similarly obtained as

s2INL^V2

refs2C �for N 4 1� �8�

In the improved version of the single-ended

pipeline ADC stage, the sensitivity to the capacitor

mismatch is minimized when Vin is around Vref

because, in this case, the operation for Diÿ 1 � 1

(equation (5)) is always used and the effect of the

capacitor mismatch is cancelled out. The worst case

error appears for the case that Vin is 2Vcom ÿ Vref , or

the operation for Diÿ 1 � 0 (equation (6)) is always

used in each pipeline stage. The variance of the

integral nonlinearity in the worst case is calculated

similarly as

s2INL^

2

3V2

refs2C �for N 4 1� �9�

The capacitor mismatch sensitivity of these three

types of pipelined A/D converters are examined by

stochastic computer simulation under the assumption

that the capacitor mismatch error follows a Gaussian

distribution. Fig. 12 shows the distribution of the

standard deviation of the integral nonlinearity error

over the whole range of 8-b pipelined A/D con-

verters. The integral nonlinearity is normalized by

1 LSB, or Vref =256. The standard deviation of the

capacitor ratio is assumed to be 10ÿ3, or 0.1%. As

predicted by the above analysis, the standard

deviation of the error of the differential type becomes

maximum around the center of the ADC code which

correspond to the condition Vin ^ 0, and minimum

around the edges which corresponds to the conditions

Vin ^Vref or Vin ^ ÿ Vref . In contrast, the standard

deviation of the error of the straightforward single-

ended type becomes maximum around the edges, and

minimum around the center. In the improved version

of the single-ended pipelined ADC, the standard

deviation of the error takes maximum at the zero-side

edge which corresponds to the condition

Vin ^ 2Vcom ÿ Vref . For the digital code larger 128,

or Vin � Vcom, the distribution is almost the same as

that of the differential type, because each pipeline

stage has a similar capacitor sensitivity as predicted

by equations (3) and (5).

Table 2 shows the comparison of the theoretical

values and the simulation results for the worst case of

three types of pipeline A/D converters. Each

theoretical value approximately agrees with the

respective simulation result.

The capacitor mismatch error is a function of the

area of the capacitor plate. In the well examined LSI

layout of capacitors using common centroid geome-

tries, the capacitor mismatch error is determined by a

local edge variation of the capacitor plate, or an oxide

thickness variation, depending on the size of the

Fig. 12. Standard deviation of integral nonlinearity of 8b

pipelined A/D converters as a function of the output digital code.

Table 2. Theoretical values and simulation results of sINL (unit of

LSB) of 8 b pipelined A/D converters for the worst case.

A/D Converter Theoretical Simulation

Differential 0.074 0.061

Single-ended (improved) 0.105 0.084

Single-ended (straightforward) 0.128 0.138

Low-Power Area-Ef®cient Pipelined A/D Converter 241

plate. The capacitor ratio deviation is proportional to

either 1=C3=4 for the edge variation dominant region

or 1=C1=2 for the oxide variation dominant region [8].

According to the simulation results of Table 2, the

straightforward type and the improved type single-

ended schemes, respectively, have 2.26 and 1.38

times larger mismatch sensitivity compared to that of

the differential scheme. If we assume that the oxide

thickness variation is the dominant effect of the

capacitor mismatch error, the straightforward and the

improved single-ended designs have to use 5.1 and

1.9 times larger capacitance, respectively, than that of

the differential design in order to obtain the same

maximum nonlinearity error.

5. Power and Area Estimation

5.1. Power Dissipation

Power dissipation of the pipelined A/D converter is

dominated by the power consumed by the DC bias

current of the ampli®ers, PA, which is given by

PA � N6kb6I06VDD �10�where N is the number of bits, I0 is the unit bias

current as described in Section 3.2, kb is the ratio of

total bias current of the ampli®er to I0, and VDD is the

power supply voltage. In high-speed A/D converters,

the settling time of the ampli®er used have to be less

than half of the sampling period. In the CMOS

implementation of the ampli®er, the settling time is a

function of the output current drivability and the

capacitance used for the multiply-by-two ampli®er.

The capacitance have to be chosen to meet the

requirement of the capacitor mismatch error. For

instance, in a 10 b pipelined A/D converter [2] using

differential scheme, the unit capacitance of about

0.4 pF is used. This capacitance of 0.4 pF is assumed

to use in the differential pipelined A/D converter

design. To have the same integral nonlinearity error,

the improved single-ended design should use (0.084/

0.061)2 times larger capacitance compared to the

differential scheme if the oxide thickness variation is

assumed to be the dominant factor of the capacitor

mismatch. The resulting capacitance is 0.76 pF. In the

case of straightforward single-ended design, the

capacitance is 2.08 pF based on similar calculation.

Fig. 13 shows the simulated results of the relationship

between the unit bias current, I0, of the ampli®er and

the settling time of three types of multiply-by-two

ampli®er designs; the differential and the single-

ended designs. The settling time is de®ned when the

settling error becomes 0.1%. The unit capacitance

used are 0.4, 0.76 and 2.08 pF for the differential, the

improved single-ended and the straightforward

single-ended schemes, respectively. For 20 Msps

operation, the settling time should be less than

23 ns with an unoverlap clock margin of 2 ns. In

this condition, the unit bias current should be larger

than 440, 220 and 1500 mA, respectively, for the

differential, the improved single-ended and straight-

forward single-ended designs. Because of the simple

source common cascode scheme and the use of

nMOS transistor as the input device, the improved

single-ended design requires even less drive current

despite of the use of larger capacitance.

The calculated power dissipation of the 10b

pipelined A/D converter consumed by the DC bias

current of the multiply-by-two ampli®er is shown in

Fig. 13. The simulated results of the relationship between the

unit bias current and the settling time.

Table 3. Estimated power dissipation of the differential and the

single-ended pipelined A/D converters (10 b, 20 Msps, 2.5 V).

A/D Converter kb

Capacitance

[pF]

I0

[mA]

PA[mW]

Differential 5.0 0.4 440 55

Single-ended

(improved)

1.5 0.76 220 8.3

Single-ended

(straightforward)

1.5 2.08 1500 56

242 D. Miyazaki, S. Kawahito and Y. Tadokoro

Table 3. The proposed single-ended pipelined A/D

converter is very effective to reduce the power

dissipation compared to the conventional differential

type pipelined A/D converters.

The total power has to take the comparator power

into account. As described in Section 3.3, the

designed comparator consumes 0.3 mW/stage and

the power contribution of comparators in 10 b A/D

converter is 3 mW. The total power including that of

comparators is still considered to be low power.

5.2. Area

Another merit of the single-ended pipelined A/D

converter is in saving silicon area because of its

simplicity of the circuits. In Table 4, the number of

components are compared between the differential

and the single-ended designs. Although the number

of components does not directly mean the silicon area

occupation, the clear difference between two types

suggests the advantage of the single-ended pipelined

A/D converter in area saving.

6. Conclusions

In this paper, a low-power area-ef®cient design

method of a high-speed pipelined A/D converter

has been presented. The key techniques are a single-

ended switched capacitor pipeline stage with a

reduced capacitor mismatch and a cascode ampli®er

with the reduced DC bias current and the excellent

switching behavior. The low-power pipelined A/D

converter is particularly useful for battery-powered

portable video devices. The practical implementation

of the designed A/D converter is left as a future

subject.

Application of a power optimization technique

further reduces the power of the proposed pipelined

A/D converter using the single-ended ampli®er [10].

References

1. K. Kusumoto, A. Matsuzawa, and K. Murata, ``A 10-b 20 MHz

30 mW pipelined interpolating CMOS ADC.'' IEEE J. Solid-State Circuits 28(12), pp. 1200±1206, 1993.

2. T. B. Cho and P. R. Gray, ``A 10 b, 20 Msample/s 35 mW

pipeline A/D converter.'' IEEE J. Solid-State Circuits 30(3),

1995.

3. A. N. Karanicolas, H. S. Lee, and K. L. Bacrania, ``A 15-b

1-Msample/s digitally self-calibrated pipeline ADC.'' IEEEJ. Solid-State Circuits 28(12), pp. 1207±1215, 1993.

4. B. S. Song, M. F. Tompsett, and K. R. Lakshmikumar, ``A 12-

bit 1-Msample/s capacitor error-averaging pipelined A/D

converter.'' IEEE J. Solid-State Circuits 23(6), pp. 1324±

1333, 1988.

5. R. Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 1994.

6. E. Sackinger and W. Guggenbuhl, ``A high-swing, high-

impedance, MOS cascode circuit.'' IEEE J. Solid-StateCircuits 25(1), pp. 289±298, 1990.

7. E. Bruun and P. Shah, ``Dynamic range of low-voltage cascode

current mirrors.'' Proc. IEEE Int. Symp. Circuits Systems,

pp. 1328±1331, 1995.

8. J. B. Shyu, G. T. Temes, and F. Krummenacher, ``Random error

effects in matchied MOS capacitors and current sources.''

IEEE J. Solid-State Circuits 19(6), pp. 948±955, 1994.

9. W. C. Song, H. W. Choi, S. U. Kwak, and B.S. Song, ``A 10-b

20-Msample/s low-power CMOS ADC.'' IEEE J. Solid StateCircuits 30(5), pp. 514±521, 1995.

10. D. W. Cline and P. R. Gray, ``A power optimized 13-b

5 Msample/s pipelined analog-to-digital converter in 1.2 mm

CMOS.'' IEEE J. Solid-State Circuits 31(3), pp. 294±303,

1996.

Daisuke Miyazaki received a B.E. degree in

information and computer sciences from Toyohashi

University of Technology, Toyohashi, Japan, in 1997.

He is currently a graduate student of information and

computer sciences at Toyohashi University of

Technology. His research interest is in low-power

A/D converter design.

Table 4. Comparison of device counts.

Transistor

A/D Converter Ampli®er Switch Capacitor

Differential 19 19 10

Single-ended

(improved)

8 10 5

Single-ended

(straightforward)

8 3 6

Low-Power Area-Ef®cient Pipelined A/D Converter 243

Shoji Kawahito received his B.E. and M.E.

degrees in electrical and electronic engineering from

Toyohashi University of Technology, Toyohashi,

Japan, in 1983 and 1985, respectively, and a D.E.

degree from Tohoku University, Sendai, Japan, in

1988. He is currently an Associate Professor with the

Department of Information and Computer Sciences,

Toyohashi University of Technology. From 1996 to

1997, he was a Visiting Professor at ETH Zurich. His

research interests include integrated smart sensors and

mixed analog/digital LSI circuits. Dr. Kawahito

received the Outstanding Paper Award at the 1987

IEEE International Symposium on Multiple-Valued

Logic. He is a member of the Institute of Image

Information and Television Engineers of Japan.

Yoshiaki Tadokoro received B.E., M.E., and D.E.

degrees in electronic engineering from Tohoku

University, in 1967, 1969, and 1976, respectively.

From 1969 to 1978 he was an Instructor in the

Department of Electronic Engineering, Tohoku

University. From 1978 to 1986 he was an Assistant

and Associate Professor, and he is currently a

Professor in Toyohashi University of Technology.

His recent interests have centered on digital signal

processing and its applications to the communica-

tions and visual substitution system for the blind. Dr.

Tadokoro is a member of the Institute of Electrical

Engineers of Japan, the Society of Instrument and

Control Engineers of Japan, and the Information

Processing Society of Japan.

244 D. Miyazaki, S. Kawahito and Y. Tadokoro