low power and high speed lms algorithm using … · 2018-11-03 · low power and high speed lms...

LOW POWER AND HIGH SPEED LMS ALGORITHM USING

REVERSIBLE LOGIC GATES

Dr.J L Mazher Iqbal

Professor, ECE Department

Madanapalle Institute of Technology and

Science Madnapalle, India

[email protected]

Momin Nikhath

M.Tech Student, ECE Department

Madanapalle Institute of Technology and

Science Madnapalle, India

[email protected]

Abstract: Least Mean Square (LMS) algorithm is a class of adaptive filter. LMS algorithm is used in many applications related to adaptive signal and processing. In order to design this algorithm which can be able to satisfy to meet the requirements such as low complexity, high speed and low power is a great challenge. In

the present scenario, high speed, low power and low area products make an important contribution in modern VLSI design. In this paper, we design a LMS algorithm using reversible logic gates which offer many advantages like low power, less area and high speed. The proposed LMS algorithm uses carry save adder using reversible logic gates in order to reduce the power consumption, also the carry save adder used in this work reduce the delay. Thus performance of the proposed LMS algorithm with carry save adder and reversible logic gates is high when compared to conventional LMS algorithm. The proposed LMS algorithm can be applied in many applications in the field of Digital Signal Processing (DSP). The algorithm is developed using Verilog Hardware Descriptive Language and implemented using Xilinx software.

Keywords: LMS algorithm, Reversible Logic Gates, Carry Save Adder.

1. INTRODUCTION

In Digital Signal processing (DSP) application such as noise cancellation, echo cancellation, system

identification, channel estimation, adaptive filters are very essential. The simplest adaptive filter is the tapped-

delay-line Finite Impulse Response (FIR). Every filter has weights, so the weights in the tapped-delay-line

Finite Impulse Response are updated by the very popular Widrow-Hoff Least mean square algorithm. Least

Mean Square (LMS) algorithm is a class of adaptive filter. It was developed by Stanford University Professor

named as Bernard Widrow along with the help of first Ph.D student named as Ted Hoff. The LMS adaptive

filter is used in many DSP applications because of low complexity. Apart from this it has features like stability

and satisfactory performance. Efficient implementation of the LMS adaptive filter is still moderately important,

because of the constraints on area, time and power consumption complication. LMS algorithm has to update the weights of the filter during each sampling period by utilizing the estimated error, which shows the difference

between existing filter output and the required response. In VLSI design, one of the major concerns of any

design is the power dissipation. Due to enhancement in the characteristics of the VLSI product the components

on a chip are increasing, when the components are more the area will be more and hence the power dissipation

will be more. In order to reduce the power consumption, reversible logic gates play a vital role. Reversible

computing is one of the excellent methods in low power dissipating circuit design for cryptography; thermo

dynamics as it decrease the power dissipation by eliminating information loss. The addition of binary digits can

be possible by using adder, which is a digital circuit. Adder is one of the basic components used in applications

like Microprocessor, DSP Processor, ARM Processor etc. There are various types of adders such as Ripple carry

adder (RCA), Carry look ahead adder (CLA), Carry Save Adder (CSA), Carry Skip Adder etc. The RCA is the

basic adder whose operation depends on carry in and carries out. Here, the carry out of each full adder is the carry-in to the subsequently significant full adder. In the existing system, the LMS algorithm is designed by

instantiating the carry save adder. By using this method, the delay will increase, hence the speed is low. In this

paper, we have proposed a design for the implementation of LMS algorithm using reversible logic gates in such

a way that the proposed design not only reduces the delay but also reduce the power consumption. This is

possible by designing LMS algorithm using carry save adder with reversible logic gates and instantiating the

carry save adder in the LMS algorithm to reduce the delay and power.

This article is organized as follows. In section 2, the proposed method is presented, experimental results are

discussed in section 3, discussion is given in section 4 and finally conclusion is given in section 5.

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 1 (2017) © Research India Publications. http://www.ripublication.com

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2. PROPOSED METHOD

The proposed LMS algorithm using carry save adder with reversible logic gates is shown in Fig .1.

Fig. 1 The proposed LMS algorithm using Reversible Logic Gates.

The building blocks used in the proposed LMS algorithm are FIR filter block, reversible carry save adder,

weight update block. The input sample xn is applied to the FIR filter; the weight update block will update the

new weights and gives the filter output. The filter output is then compared with the desired signal. The

difference between the filter output and the desired signal is called error signal. The error signal is passed to the weight update block through reversible carry save adder which is designed using reversible logic gates. The

proposed design performs addition operation based on the requirement. So that the delay can be reduced and

power is reduced as well.

2.1 Finite Response Filter Block

In signal processing, a Finite Impulse Response (FIR) is of finite duration and it settles to zero in finite time,

which may have internal feedback and may continue to respond indefinitely through infinite impulse response.

In Nth order discrete time FIR lasts exactly N+1 sample then settles to Zero. FIR filters can be analog or digital

(continuous time or discrete time). The internal block of FIR filter is shown in Fig.2.

2.2 Reversible Carry Save Adder

Reversible logic gates are those gates in which the inputs and outputs are same. There must be a one to one correspondence between input and output. Garbage output is nothing but additional outputs that are added in

order to make both the inputs and outputs same. If the output is not used then we call it as garbage output. In

reversible gates constant inputs plays a very important role. Constant inputs are nothing but maintaining

constant value either 0 or 1 in order to obtain the correct logic. Addition is the basic operation used in many

applications such microprocessor, DSP processor etc. Adders are of so many types like ripple carry adder, carry

skip adder, carry save adder etc. Normally, the function of CSA reduces the addition of three numbers to the

addition of two numbers. The propagation delay corresponding to the carry save adder is three gates irrespective

of number of gates. In the normal convention carry save adder, full adders and half adders are used. But, here

the carry save adder is developed with the help of only reversible gates. There are various reversible logic gates

available such as Peres Gate and HNG gates; these are used in designing Carry save adder. Peres Gate is a three

inputs and three outputs gate. The quantum cost of the Peres gate is four. The circuit diagram is shown below.

XOR gate, AND gate, OR gate can be realized using Peres Gate.

FIR Filter

block

Weight update

block Reversible

Carry save

adder

Mean

Difference

(mD)

+

Input sample, xn Filter Output, yn

New weights

Desired Signal

Dn

Error, en

Mean

Difference (mD)


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Fig.2. Internal block of FIR filter

Fig.3. Peres Gate

Fig.3. HNG Gate

HNG gate is a four inputs and four outputs gate. The quantum cost of the HNG gate is six. It is mainly use to

implement adders such as Ripple Carry Adder, Carry Save Adder. It will produce sum and carry in the same

output by reducing the garbage and gate counts. Reversible logic gates have many advantages. Reversible Gates

uses Low Power when compared to the conventional logic gates. If a circuit is designed by using reversible

Logic gates the information loss is zero. The dissipation of heat is negligible and delay is less by using

Reversible Logic Gates. The logic diagram of the HNG gate is shown below.

The proposed carry save adder design using HNG gates and Peres Gates is shown in Fig.4. The proposed LMS

algorithm design uses carry save adder using HNG gates and Peres Gates.

2.3 Weight Update Block

Every filter is having some weights. The weight update block update the weights of the filter and give the

updated weights to the FIR block which will produce the output. Tap weight vector can be represented as W (n).

The input vector and the desired output is denoted as x (n) and d (n). Tap Weight vector update can be denoted

as W (n+1). The filtering, error and tap-weight vector adaptation is given by the formulas shown below:

Filtering: Y(n) =W T (n) x (n) (1) Error: e(n) = d(n)-y(n) (2)

∑ ∑ ∑

X[n]

b0

Y[n]

b 1 b2

b3

Peres Gate

A

B

C

A

A®B

AB®C

A

B

C

HNG Gate

A

B

A®B®C

(A®B)C®AB®D D


174

Tap-Weight Vector adaptation: W (n+1) = W (n)+ 2µe(n)x (n) (3)

In the LMS algorithm the Step Size parameter should satisfy the following equation

0 < µ < 2

λmax (4)

Fig.4. Carry Save Adder using Reversible Logic Gates

3. EXPERIMENTAL RESULTS

The experimental results of the proposed LMS design using CSA with reversible logic gates are shown in Fig.6,

Fig.7, Fig.8, Table.1 and Table.2. The schematic diagram of the LMS algorithm with conventional Gates and

CSA using reversible logic gates are shown in Fig.5 and Fig.7. The RTL schematic of LMS algorithm with

conversional gates and CSA using reversible logic gates are shown in Fig.6 and Fig.8. RTL stands for Register

Transfer Level. The main use of RTL schematic is to produce High level representation of a circuit from which

low level circuit can be extracted and then finally actual wiring can be derived. RTL Schematic can be generated

by the synthesis tool at the previous stage of the synthesis process. The synthesis tool will generate the RTL

schematic before the technology mapping. Table.1 and Table2 shows the synthesis results of the LMS algorithm

with conventional gates and CSA using reversible logic gates.

Fig.5. Schematic diagram of the LMS algorithm with conventional Gates


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Fig.6. RTL Schematic diagram of the LMS algorithm with conventional Gates

Table.1. Device Utilization Summary of the LMS algorithm with conventional Gates


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Fig.7. Schematic diagram of the proposed LMS algorithm with CSA using reversible logic gates

Fig.8. RTL Schematic diagram of the LMS algorithm with CSA using reversible logic gates

Table.2. Device Utilization Summary of the LMS algorithm with CSA using reversible logic gates

4. DISCUSSION

The proposed method use reversible logic gates in the design in order to reduce the power consumption as well

as delay. Addition is the basic arithmetic operation that can be performed in many applications. So, carry save

adder is designed with the help of Reversible Logic Gates. The new CSA using reversible logic is used to

implement LMS adaptive filter. This approach minimizes power dissipation of digital circuits by minimizing the

switching activity. In the proposed method using reversible logic gates, the LMS algorithm will have a delay of

14.295ns. As the delay decreases the speed increases, also the power dissipation is less by using Reversible

Gate.

5. CONCLUSION

The proposed design using CSA and reversible logic gates is an area-delay-power efficient adaptive LMS

architecture for the implementation of the fixed point adaptive filter. Carry Save Adder in the proposed design


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uses reversible logic gates. The proposed algorithm is executed using Xilinx software. Reversible Logic Gates is

a technique where the information loss is less and with less heat generation. LMS algorithm using reversible

adders are logically verified in Xilinx using Verilog Hardware Descriptive Language (Verilog HDL). Thus the

proposed design reduces the delay which in turn increases the speed. Modern VLSI circuits needs very less

power so by using reversible gates the power consumption also reduced.

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low power and high speed lms algorithm using … · 2018-11-03 · low power and high speed lms...

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