LOW POWER ANALOG CMOS FOR CARDIAC PACEMAKERS

THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE

ANALOG CIRCUITS AND SIGNAL PROCESSING Consulting Editor: Mohammed Ismail. Ohio State University

ReiiJted Titles:

MIXED-SIGNAL LAYOUT GENERATION CONCEPTS Lin, van Roermund, Leenaerts ISBN: 1-4020-7598-7

mGH-FREQUENCY OSCILLATOR DESIGN FOR INTEGRATED TRANSCEIVERS Vander Tang, Kasperkovitz and van Roermund ISBN: 1-4020-7564-2

CMOS INTEGRATION OF ANALOG CIRCUITS FOR mGH DATA RATE TRANSMITTERS DeRanter and Steyaert ISBN: 1-4020-7545-6

SYSTEMATIC DESIGN OF ANALOG IP BLOCKS V andenbussche and Gielen ISBN: 1-4020-7471-9

SYSTEMATIC DESIGN OF ANALOG 1P BLOCKS Cheung & Luong ISBN: 1-4020-7466-2

LOW-VOLTAGE CMOS LOG COMPANDING ANALOG DESIGN Serra-Graells, Rueda & Huertas ISBN: 1-4020-7445-X

CIRCUIT DESIGN FOR WIRELESS COMMUNICATIONS Pun, Franca & Lerne ISBN: 1-4020-7415-8

DESIGN OF LOW-PHASE CMOS FRACTIONAL-N SYNTHESIZERS DeMuer & Steyaert ISBN: 1-4020-7387-9

MODULAR LOW-POWER, HIGH SPEED CMOS ANALOG-TO-DIGITAL CONVERTER FOR EMBEDDED SYSTEMS

Lin, Kernna & Hosticka ISBN: 1-4020-7380-1

DESIGN CRITERIA FOR LOW DISTORTION IN FEEDBACK OPAMP CIRCUITE Hernes & Saether ISBN: 1-4020-7356-9

CIRCUIT TECHNIQUES FOR LOW-VOLTAGE AND mGH-SPEED AID CONVERTERS Walteri ISBN: 1-4020-7244-9

DESIGN OF mGH-PERFORMANCE CMOS VOLTAGE CONTROLLED OSCILLATORS Dai and Harjani ISBN: 1-4020-7238-4

CMOS CIRCUIT DESIGN FOR RF SENSORS Gudnason and Bruun ISBN: 1-4020-7127-2

ARCmTECTURES FOR RF FREQUENCY SYNTHESIZERS Vaucher ISBN: 1-4020-7120-5

THE PIEZOJUNCTION EFFECT IN SILICON INTEGRA TED CIRCUITS AND SENSORS Pruett and Meijer ISBN: 1-4020-7053-5

CMOS CURRENT AMPLIFIERS; SPEED VERSUS NONLINEARITY Koli and Halonen ISBN: 1-4020-7045-4

MULTI-STANDARD CMOS WIRELESS RECEIVERS Li and Ismail ISBN: 1-4020-7032-2

LOW POWER ANALOG CMOS FOR CARDIAC PACEMAKERS

Design and Optimization in Bulk and SOl Technologies

by

Fernando Silveira Universidad de la Republica and CCC S.A.,

Montevideo, Uruguay

and

Denis Flandre Universite catholique de Louvain,

Louvain-la-Neuve, Belgium

SPRINGER SCIENCE+BUSINESS MEDIA, LLC

A c.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN 978-1-4419-5419-0 ISBN 978-1-4757-5683-8 (eBook) DOI 10.1007/978-1-4757-5683-8

Printed an acid-free paper

AII Rights Reserved © 2004 Springer Science+Business Media New York

Original1y published by Kluwer Academic Publishers, Boston in 2004

No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording

or otherwise, without written permis sion from the Publisher, with the exception of any material supplied specifically for the purpose of being entered

and executed on a computer system, for exclusive use by the purchaser of the work.

Contents

Acknowledgements Vll

Preface ix

1. Implantable Cardiac Pacemakers 1

2. Industrial Implementation of Pacemaker Integrated Circuit in Bulk CMOS Technology 25

3. Potential of SOl Technology for Low-Voltage Micropower Biomedical Applications 51

4. Power Optimization in Operational Amplifier Design 85

5. Class AB Micropower Operational Amplifiers 123

6. Implementation of Pacemaker Sense Circuits 159

Appendix 1. Integration of Large Time Constants 17 5

Appendix 2. Design of Accelerometer Signal Conditioning Circuit of Industrial Pacemaker IC in Bulk CMOS Technology 179

Bibliography 199

Index 207

v

Acknowledgements

This book and the work that is presented in it would not have been possible without the technical, practical, financial and encouraging support that was provided by many individuals and institutions.

We are deeply grateful to Prof. Paul Jespers, who is at the origin of the relationship of Fernando Silveira with the Universite catholique de Louvain (UCL) and who sowed the seed for one of the mainstays of this work, the gn/lo method.

We want to thank the members of our labs: the lnstituto de lngenierfa Electrica at Universidad de la Republica (UR) and the Microelectronics Laboratory at UCL, for making them very enjoyable places of work.

At UCL, we must particularly point out the helping hand of the following people: Anne Adant, Xavier Baie, Jian Chen, Andre Crahay, Laurent Demeils, Vincent Dessard, Carlos Dualibe, Brigitte Dupont, Jean-Paul Eggermont, Luiz Ferreira, Bernard Gentinne, Benjamin Ifiiguez, Bernard Herent, Pierre Loumaye and Alberto Viviani.

At UR we want to thank all the members of the Microelectronics Group, who worked with F. Silveira on the design and test of the industrial pacemaker chip: Alfredo Arnaud, Marcelo Barn, Oscar de Oliveira, Pablo Mazzara, Gonzalo Picun, Conrado Rossi and the late Hugo V aldenegro. We specially acknowledge the key participation of some members of the group in other works that are part of this book: the contribution of Alfredo Arnaud in the development of the model of the sample and hold presented in Appendix 2; the participation of Oscar de Oliveira and Conrado Rossi in, respectively, the initial development of the switched capacitor sense channel and its layout, and the participation of Linder Reyes in the test of this circuit. We also thank the students Leonardo Dfaz and Ricardo Clavijo for their

Vll

viii Acknowledgements

work on the layout and simulation of the amplifier A4 presented in Chapter 5. F. Silveira is indebted to Facultad de Ingenierfa and the Instituto de Ingenierfa Electrica (liE) for supporting the development of his thesis, particularly the head of his department, Prof. Rafael Canetti and the head of the liE, Prof. Gregory Randall.

The development of the central subject of this book was possible due to the collaboration with CCC del Uruguay S.A. F. Silveira is thankful to those that took the decision of working with UR in this area; Julio Arzuaga, Fernando Brum, Alicia Fiandra and Orestes Fiandra. He is also very grateful to Julio Arzuaga, Pedro Arzuaga and the rest of the members of CCC for their technical guidance in the field of pacemakers and medical implants, and for sharing their solid and wise approach to engineering problems.

We also wish to acknowledge the financial support of the Secretariat a la Cooperation Intemationale at UCL, and the always warm and effective assistance of Mrs. Louise Baeyens, as well as financial support of the CSIC of UR and Conicyt of Uruguay in various projects related to this work.

We thank the members of the PhD thesis jury that contributed with valuable suggestions that helped to improve the thesis text that is the basis for this book: Profs. Jose Luis Huertas, Jean Didier Legat, Damien Macq and Michel Verleysen

We thank Marfa del Carmen Aguado, for her help in checking and improving the language of this text and Laura Landing for her help in the formatting of the text.

Finally, and specially from our hearts, we are grateful to our families and friends, who endured our dedication to this work.

Preface

Power reduction is a central pnonty in battery-powered medical implantable devices, particularly pacemakers, to either increase battery lifetime or decrease size using a smaller battery. This book proposes new techniques for the reduction of power consumption in analog integrated circuits applied in pacemakers. Its main case of study is the pacemaker sense channel, which is representative of a broader class of biomedical circuits aimed at qualitatively detecting biological signals.

The book is expected to be useful for researchers, postgraduate students and designers in both the areas of analog integrated circuits and implantable medical devices.

The basis of this text was written as a Ph.D. thesis at the Universite Catholique de Louvain, Louvain-la-Neuve, Belgium. Part of the work was developed at the lnstituto de Ingenierfa Electrica, Universidad de la Republica, Montevideo, Uruguay. Concurrently with the development of the thesis, an industrial integrated circuit for pacemakers was designed for CCC S.A, Uruguay, a pacemaker factory. In this and subsequent projects with CCC S.A. the pacemaker appeared as an example of choice for the analysis of the impact of application of SOl technology and power-aware design techniques.

The book contains six chapters. The first and second chapters are a tutorial presentation on implantable medical devices and pacemakers from the circuit designer point of view. This is illustrated by the requirements and solutions applied in our implementation of an industrial IC for pacemakers. Therefrom, the book discusses the means for reduction of power consumption at three levels: integration technology, power-oriented analytical synthesis procedures and circuit architecture.

ix

X Preface

At the technology level, we analyze the impact that the application of the fully depleted silicon-on-insulator (FD SOl) CMOS technology has on this kind of analog circuits. The basic building block level as well as the system level (pacemaker sense channel) are considered.

Concerning the design technique, we apply a methodology, based on the transconductance to current ratio, that exploits all regions of inversion of the MOS transistor. Various performance aspects of analog building blocks are modeled and a power optimization synthesis of OTAs for a given total settling time (including the slewing and linear regions) is proposed.

At the circuit level, we present a new design approach of a class AB output stage suitable for rnicropower application. In our design approach, the usual advantages of the application of a class AB output stage are enhanced by the application of a transconductance multiplication effect.

These techniques are tested in experimental prototypes of amplifiers and complete pacemaker sense channel implementations in SOl and standard bulk CMOS technologies.

A ultra low consumption of 110 nA (0.3 JlW) is achieved in a FD SOl sense channel implementation.

Though primarily addressed to the pacemaker system, the techniques proposed are shown to have application in other contexts where power reduction is a main concern.

Next, we present an outline of the content of each chapter.

Chapter 1 Implantable Cardiac Pacemakers.

The first chapter provides the reader with the main framework set by the target application and the general specifications that this application imposes on the circuits studied in this work.

The chapter is organized in three parts. In the first part, we introduce a brief view of the operation and functionality of modem implantable cardiac pacemakers at the system level. The second part describes the circuit blocks that are comprised in these devices and the requirements imposed on some of these circuit blocks, while reviewing the prior published work on implantable pacemaker circuit design. Finally, in the third part, we show, by the analysis of other medical devices and functions, that the essential requirements of the pacemaker sense amplifier are common to several devices, allowing the conclusions of our study to have wider application.

Chapter 2 Industrial Implementation of Pacemaker Integrated Circuit in Bulk CMOS Technology.

Xl

The second chapter discusses the architectural alternatives, trade-offs, actual design and results of circuits we have implemented in Bulk CMOS technology, for a pacemaker's analog processing functions. Particularly we focused on two main analog modules of a pacemaker: the sense channel and the activity sense block.

The analysis of this industrial design provides us with detailed specifications and performance data that will be later applied to design and to evaluate alternative architectures and technology (SOl). In addition, the methods applied to meet the challenges of operation of analog circuits at low-voltage (2V) power supply in a standard Bulk CMOS process are described.

Regarding the design of the sense channel, the selection of the overall architecture and the main design characteristics of the basic building blocks are presented. In particular the compromise between the use of external components and the implementation of a fully integrated solution is discussed. A review of the alternatives for integrated implementation of large time constants is presented in the Appendix 1 of the book.

As an additional example of micropower analog block of the pacemaker, the design of an accelerometer signal conditioning circuit for activity sensing is presented in the Appendix 2 of the book.

Chapter 3. Potential of SO/ Technology for Low-Voltage Micropower Biomedical Applications.

The goal of the third chapter is to introduce the reader to the characteristics of Fully-Depleted (FD) SOl technology and to evaluate its potential impact in biomedical applications that require analog blocks under low-voltage operation and micropower consumption.

The chapter starts by briefly reviewing the features of the FD SOl technology. Then, we analyze the improvements that can be obtained for the operation of basic components such as analog switches, current mirrors and operational transconductance amplifiers (OTAs). These analyses devote particular attention to those blocks and performance aspects that are central to the proposed implementation of our study vehicle, the sense channel, as well as to the implementation of other pacemaker analog blocks. This is the case of the speed and precision of current mirrors, which are essential elements in the class AB stage proposed in Chapter 5, and of OTA characteristics such as the power - bandwidth trade-off, noise and offset.

xu Preface

Chapter 4. Power optimization in operational amplifier design.

The fourth chapter is aiming at shedding light on the ultimate reasons that condition power consumption in amplifier design. An analysis of the factors that determine power consumption leads us on to the selection of the most effective ways to reduce it. The results are then applied to the power optimization of a Miller operational transconductance amplifier (OTA).

In the first part, we present a brief review of existing results about theoretical limits of power consumption of analog circuits. These results suggest the essential mechanisms to get closer to these limits; they serve as comparison reference and they identify the criteria on the formulation of figures of merit for comparison between actual circuit implementations. The first part ends with a review of the practical limits and the introduction of a general scheme of the factors that determine power consumption in operational amplifiers. The results presented in this first part, besides its interest from the general point of view of low-power analog design, provide elements required in order to perform a fair comparison of the results of our amplifiers and the pacemaker sense channel with other published amplifiers and filters.

The second part formulates a "power oriented" synthesis of the Miller OT A. We introduce a new procedure to handle the trade-off between linear settling time (associated to the gain-bandwidth product) and slew rate, which applies a novel, joint optimization of these two aspects to achieve minimum power consumption. The proposed design procedure, which can be extended to other OT A architectures, makes it possible to determine numerically the best combination of the input and output stage gn/10 ratio and simultaneously provides insight on the underlying reasons that lead to this optimum.

Chapter 5. Class AB Micropower Operational Amplifiers.

The fifth chapter presents a novel design approach for a class AB output stage, as required to save quiescent power in the pacemaker sense channel.

The chapter is organized as follows. First, we introduce the general characteristics of class AB stages and review the main structures found in the literature. Then, we describe the selected architecture and the method applied to synthesize it for minimum power consumption. Next, the experimental results on the fabricated prototypes and comparisons with reported amplifiers of similar characteristic are presented. Finally, improvements to the basic circuit structure and design method are discussed.

xiii

Chapter 6. Implementation of pacemaker sense circuits.

The last chapter describes the application of various techniques and ideas developed in the book to the design of pacemaker sense circuits. First we present a switched capacitor (SC) design of a sense channel filter I amplifier in 0.81J.m Bulk technology. Next, we describe a continuous time implementation of the sense channel in FD SOl technology that achieves a ultra low consumption of only llOnA, applying the general architecture described in Chapter 2.

Finally, the main conclusions and future research lines are summarized.