978-1-4799-7678-2/15/31.00 ©2015 IEEE

DESIGN AND IMPLEMENTATION OF 4 BIT FLASH ADC USING LOW POWER LOW

OFFSET DYNAMIC COMPARATOR Suman Biswas

School of Electronics Engineering KIIT UNIVERSITY Bhubaneswar, India

sumanbiswas392@gmail.com

Jitendra Kumar Das School Of Electronics Engineering

KIIT UNIVERSITY Bhubaneswar , India jkdas12@gmail.com

Rajendra Prasad School Of Electronics Engineering

KIIT UNIVERSITY Bhubaneswar , India

rajen.rajan@gmail.com

Abstract—Flash architecture are well known for it's speed during Analog to Digital conversion. A 4bit Flash type analog to digital converter has been presented in this paper. A low power low offset dynamic comparator having a average power consumption of 54uw has been implemented in the given architecture. Different types of thermometer to binary encoders are employed in this paper and they are analyzed in terms of delay and power comparison. By transient analysis the functionality of this Flash ADC is verified. The main aim is to design Flash ADC with low power comparator so that the overall power consumption can be reduced. As Flash type ADC are power hungry devices so the aim is to use a low power comparator in odor to reduce the power consumption of the device as it uses 2n-1 number of comparator. The flash ADC is simulated in 180nm technology using cadence virtuoso design environment simulation.

Keywords—analog to digital converters; comparators;encoders.

I. INTRODUCTION Larger portion of the electronic industry is dominated by the MOS market during last few years. Between Analog to Digital signals the ADC plays a vital role despite of having a high power consumption and large chip area the Flash ADC is the fastest and simplest among all other architecture. A n bit Flash ADC has 2n-1 comparators which in turns generate a thermometer code in the combination of ones and zeroes series[6]. In Fig. 2 the Flash architecture is shown . The three blocks that are used in Flash ADC are namely : comparator , encoder and resistor string shown in Fig. 1. A series of resistor which are attached in string fashion shown in the first block are used as a voltage divider. In a n-bit Flash ADC , the 2n-1 resistor in a string creates 2n-1 voltage reference which are used as a input in the comparators[7] [11]. The input voltage which are given to the comparators are compared with the above reference voltages. Comparators that are used in the architecture are in the odor of 2n-1 . When the input voltage to the comparator is less than that of the reference voltage the output of the comparator goes low & when the input voltage is more than that of the reference voltage of the comparator the comparator goes high. The output that are generated by the comparators are comprised of thermometer code which are generally a series of zeroes and ones.

Fig. 1: Block diagram of Flash ADC The third block comprised of the thermometer to binary encoder. The encoder circuit is connected after the comparators and converts the thermometer code into binary code[14] [10]. Generally the thermometer code is converted into 1 out of n code before it is coded into binary and this code comprises of only one and rest are zeroes. The majority of the power consumption are given to the encoder as it plays a vital role in designing a high performance Flash ADC. There is only one transition delay in thermometer code i.e series of zeroes is followed by series of 1 eg. 00..0011..11.

Fig. 2: Architecture of Flash ADC

But unexpected zeroes in series of one and one in series of zeroes may arise which is generally termed as bubble error. These errors are caused by device mismatch , comparator offset . luckily these errors are overcome by the proposed

comparator used in this Flash architecture as it's having a high sensitivity as it can detect a difference of 1mv. This paper is organised as follows : it begins with introduction to comparator , design thermometer to binary code converters. section II gives a detail about the comparator design , in section III & IV different encoder are analysed. Section V presents the simulation results followed by conclusion in section VI.

II. DIFFERENTIAL COMPARATOR A comparator is the basic building block of Flash ADC which determines it's speed and accuracy . A string of silicon resistance are used to generate different reference voltages for different comparators \& the input voltage should be varied from 0.1mv to 398mV as the reference voltage has been chosen to be 400mV. The output of the comparator goes high when the input voltage is more than the reference voltage . A clocked comparator consisting of a latch and a differential amplifier circuit are used in the design in odor to sample the input signal without jitter. The latch circuit used in a comparator ensures that the output arrives at the same time so it is synchronized with the clock.

Fig. 3: Schematic of Previous architecture

A post amplifier has been connected to the comparator to ensure that it can drive a load without having a parasitic imbalance in the latch circuitry. Fig. 3 show the previous comparator architecture which generally has a high power dissipation and it suffers from a large kickback noise.

TABLE I

Comparator Simulation results of Comparator

Average Power Delay Offset Voltage

Previous architecture

72.95uW 168.04ps 39mV

Proposed architecture

32.06uW 160.81ps 20.1mV

Proposed architecture with buffer

52.02uW 210.22ps 20.1mV

Fig.4 shows the proposed comparator architecture. It consists of three stages. The first stage is comprised of a

preamplifier stage , the second stage is a latch stage and the third stage consist of post amplifier . The first two stages are fed with clock Clk1 and Clk2. The mismatch effect inside the latch circuit is being overcome by separating the input transistors [2]. At the first phase both Clk1 and Clk2 are high which discharges the output node to the ground. During the second phase the Clk1 goes low which turns on the transistor M7 and M8 and the current starts to flow and charges up the node capacitor till Clk2 goes low. As soon as Clk2 goes low transistor M12 and M13 goes off which cuts the path from the input to the cross coupled latch. This separation helps to fight back the kickback noise which is generated at the latch during decision phase. The voltage difference between the input branches and the reference differential voltage gives rise to the current Iin+ and Iin- . This process takes place during the amplification phase. During the third phase the differential voltage is boosted in the regenerative loop of the cross coupled inverter. A comparator compares the input differential voltage with reference differential voltage Vrefdiff. The output nodes Vout+ and Vout- are discharged to the ground at the beginning. The amplification starts as soon as the clock Clk1 goes low and Clk2 still remains high. The current charges the output capacitor CL so the output rises linearly over time. The transistors M7 and M8 operate in linear region which acts as a resistor to the input transistor M5 and M6.

Fig. 4 : Schematic of Proposed architecture

As the voltage at the inputs of transistor M5 and M6 is more than zero the gate source voltage is less than their drain source voltage as a result it operates in saturation region[1]. As both the transistor operates in saturation the current equation is given by: Iin5+=K5(Vin+-Vref+-Vth5)2, Iin6-=K6(Vin--Vref--Vth6)2. Where Kpx=1/2 upCox(W/L)x. Again this current charges the capacitors CL through transistor M3 and M4 which operates in the linear region and the equation are given by : Iin+=K5(((Vclk2-V1)-Vth3).(Vout+-V1))-(Vout+-V1)2/2) , Iin-=K6(((Vclk2-V2)-Vth4).(Vout--V2))-(Vout--V2)2/2) This current charges the load capacitances CL and the output voltage linearly rises over time. During the third phase the initial voltage at the output nodes are Vout+=Iin+.ta/CL and Vout-=Iin-.ta/CL.

where ta is the amplification time. As the comparator enters in the third phase the sign of Vout+ and Vout- determines in which way the comparator swings. The voltage across the capacitors is dependent upon the current received. [Vin+ - Vref+] and [Vin+- Vref-] controls the charging current. The input referred offset can be defined as the differential input voltage that establishes the condition of Vout+=Vout- .let us assume the initial voltage at the internal nodes Vout+ , Vout- are less than the threshold voltage of transistor M12 and M13. It can also be assumed that the effective voltage of the input transistors M13 and M14 is much smaller as compared with the effective voltage of M10 and M11. Therefore the charging current for the internal nodes are provided by M10 and M11. so, CL.dVout+/dt=Iin++Kp1.

Fig. 5: output waveform of proposed comparator

The node which crosses the threshold voltage Vth12,Vth13 earlier makes a logic 1 and other makes a logic 0. Power is drawn only when the circuit is latched. The body terminals are shorted to their several design are available for the Thermometer code to Binary code converter like ROM Based , Wallace tree encoder , Multiplexer based encoder. Analysis of few encoders are implemented with the proposed comparator.

III. ENCODERS Encoders plays a vital role in the conversion of

Thermometer code into Binary code [15].

A. FAT TREE TC-TO-BC ENCODER It is necessary for this device to convert TC to one -out-of-N code. XOR gate is being implemented for this design. Using fat tree encoder The one out of N code is then encoded in the binary format. The tree becomes larger as the number of input bits increases. The output bits of the fat tree encoder is given by the following equations [13]. Bit0=a7+a6+a5+a4+a3+a2+a1+a0 Bit1=b3+b2+b1+b0 Bit2=c1+c0 Bit3=d1

Fig. 6: Fat Tree Encoder

The intermediate signals are a, b ,c and d are which is shown in Fig.6 .As the inverting logic gates have low propagation delay than the non-inverting logic gates, so to increase the performance of the Fat tree encoder NAND and NOR gates are used in place of OR gates .

TABLE II : THERMOMETER TO BINARY CONVERSION Encoder input(15bit)

I15 to I0 Encoder output

Bit3 to bit0 000000000000000 0000 000000000000001 0001 000000000000011 0010 000000000000111 0011 000000000001111 0100 000000000011111 0101 000000000111111 0110 000000001111111 0111 000000011111111 1000 000000111111111 1001 000001111111111 1010 000011111111111 1011 000111111111111 1100 001111111111111 1101 011111111111111 1110 111111111111111 1111

B. Thermometer to Binary converter using Full Adder The full adder has been designed using Double pass

transistor logic. The DPL logic has high speed of operation due to its low input capacitance and high logic functionality. In Fig.8 the circuit of the full adder is shown [16]. The sum

logic circuit consist of XOR/XNOR gate a output buffer circuit and a multiplexer .

Fig. 7 : Full Adder Design using DPL logic

The carry output consist of AND/NAND gates , a multiplexer , OR/NOR gates and a CMOS output buffer. The inputs to the gates in DPL logic of the PMOS transistors are changed from A to B. In two ways this arrangement compensates for the speed degradation of CMOS pass-transistors . First, any input is connected to the gate of one MOSFET and the source of another as it is a symmetrical arrangement .It is perfectly symmetrical in the case of the XOR/XNOR. Any of the inputs A and A' , B and B' can be connected to the gates of the NMOS and PMOS and to the sources of the NMOS and PMOS. This connection in turn results in a balanced input capacitance which reduces the dependence of the delay time on data. Secondly ,it has double-transmission characteristics which can pass both the logic without having a threshold drop.

C. Improved Mux based This section will present a clear idea behind the presented multiplexer based design. From the conversion table of Thermometer to Binary shown in Table II. The input of the thermometer code is divided into two parts at each input level and one of the bits in binary output is calculated .Fig. 8a shows the Multiplexer based encoder for 4bit Flash ADC. The disadvantage that was having huge fan out is reduced in the given design using transmission gate logic design. The increase of fan out results in increase of power and delay. Multiplexer where previously decoded binary output are connected to the select line of multiplexer. The MSB-1 is then found from the chosen partial scale. The process is continued recursively until there is only a single 2x1 Mux. The final multiplexer gives the Least Significant Bit i.e b0.The encoder circuit can be easily expanded beyond 4bit due to its regular structure. The modified structure for thermometer to binary decoder is shown in Fig. 8b . It results in more regular structure than existing mux based decoder [12]. This mux based decoder has three gates delays in critical path for a 15bit Thermometer to Binary code conversion. Further the modified decoder can be configured to operate on multiple thermometer codes. It can also operate as two 7-bit thermometer to binary decoders by taking the T8 signal as logic zero and latching the intermediate outputs of the 7-bit thermometer to binary

decoder . This property is unique to the modified MUX based encoder .

Fig. 8: Multiplexer based encoders

IV. COMPARISON CHART OF THE ENCODERS

Fig. 9: Graph showing Average power dissipation and Propagation delay

of various encoders

A comparison of the average power dissipation and propagation delays of various encoders are shown in Fig. 9 from where it can be clearly seen that the Multiplexer based encoder has the least propagation delay. So this architecture has been implemented with the proposed comparator for the Flash architecture.

V. SIMULATION AND RESULT Fig.10 shows the analog input signal and the output of the encoder starting with the Most Significant Bit(MSB) bit 3 followed by the Least Significant Bit(LSB) bit0 respectively. Table II shows the simulation result for the 4bit Flash ADC. The simulation has been run on Cadence Virtuoso analog design platform and the implementation was done with 0.18um technology. A supply voltage of 1.8v has been used. The power consumption of the proposed Flash ADC is 1.53mw which is much smaller compare to the other Flash

architecture and a comparison of the architectures are shown in Table III.

TABLE III: Simulation result for 4bit Flash ADC Technology CMOS 180nm Architecture Flash

Supply 1.8V Sampling Frequency 1GHz Input dynamic range 0.5mV p-p

Number of bits 4 Vref 400mV

DNL -0.04 to 0.04 LSB INL -0.03 to 0.06 LSB

Average Power 1.53mW

Fig. 10 : The simulation result of proposed ADC with ramp input

VI. CONCLUSION

In this paper , the design and the simulation result for the 4bit Flash ADC has been shown. The maximum sampling frequency used in the proposed architecture is 1GHz and it has low INL and DNL of 0.04LSB and 0.06LSB at a supply voltage of 1.8v while it consumes 1.52mW of power. This can also be implemented to design Pipelined ADC.

Acknowledgment The authors would like to express their thanks to our colleagues for support in the design tool. They would also like to thank other faculties of KIIT University Bhubaneswar for assistance on various parts of this work.

TABLE IV : COMPARISON TABLE OF VARIOUS FLASH ARCHITECTURE This Work [3] [4] [5] [6] [7] [8] [9]

Technology 180nm 180nm 180nm 180nm 90nm 180nm 180nm 32nm Resolution 4bit 4bit 4bit 4bit 4bit 4bit 4bit 4bit

Supply Voltage

1.8v 1.8v 1.8v 1.8v 1.2v 1.8v 1.8v 1.2v

Input range 0.5Vp-p 2Vp-p 460mVp-p 0.65Vp-p 0.59Vp-p 0.5Vp-p 0.6Vp-p 0.2Vp-p Power

dissipation 1.53mW 20mW 78mW 43mW 30.2mW 450mW 42mW 24mW

INL -0.03 ~ 0.06 LSB

1.1 LSB -0.24 ~0.20LSB -0.26~ 0.24LSB 0.54 LSB 0.51 LSB -0.03～0.06 LSB

0.34LSB

DNL -0.04 ~ 0.04LSB

0.4 LSB -0.47 ~0.472LSB

-0.35 ~ 0.35 LSB

0.48LSB 0.32 LSB -0.04~0.04 LSB 0.4LSB

Fig. 11 : INL and DNL plot

Fig. 12 : Output Waveform of Proposed Flash ADC

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