low-noise analog front-end signal processing channel...
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Low-Noise Analog Front-End Signal Processing
Channel Integration for Pixelated Semiconductor
Radiation Detector
by
Ming-Cheng Lin
B. A. Sc, Simon Fraser University, 2009
Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of
Master of Applied Science
in the
School of Engineering Science
Faculty of Applied Sciences
© Ming-Cheng Lin 2012
SIMON FRASER UNIVERSITY
Spring 2012
All rights reserved. However, in accordance with the Copyright Act of Canada, this work
may be reproduced, without authorization, under the conditions for
“Fair Dealing.” Therefore, limited reproduction of this work for the purposes of private
study, research, criticism, review and news reporting is likely to be in accordance with
the law, particularly if cited appropriately.
ii
Approval
Name: Ming-Cheng Lin
Degree: Master of Applied Science
Title of Thesis: Low-Noise Analog Front-End Signal Processing
Channel Integration for Pixelated Semiconductor
Radiation Detector
Examining Committee:
Chair: Dr. Mirza Faisal Beg, P.Eng
Associate Professor, School of Engineering Science
Dr. Marek Syrzycki, P.Eng
Senior Supervisor
Professor, School of Engineering Science
Dr. Rick Hobson, P.Eng
Supervisor
Professor, School of Engineering Science
Dr. Ash M. Parameswaran, P.Eng
Examiner
Professor, School of Engineering Science
Date Defended/Approved:
January 30, 2012
Partial Copyright Licence
iii
Abstract
In the research development of the medical nuclear imaging, the low noise performance
has always been a mandatory requirement in the design of the semiconductor pixelated
radiation detector system in order to achieve the high detectability of the charge signal.
The noise-optimized analog front-end signal processing channel composed of the charge
sensitive amplifier and the pulse shaper is used extensively in processing the radiation
charge signals from the pixelated semiconductor detector. The existing noise
optimization methodology only deals with the major noise contributors such as the input
transistor in the charge sensitive amplifier. However, as CMOS technologies progress
deeper into the submicron range, the power supply voltages are decreasing and hence, the
noise contributions of the secondary noise sources such as the current source transistor in
the charge sensitive amplifier are increasing. This thesis presents a noise optimization
methodology for the current source transistors in the charge sensitive amplifier that will
complement the existing noise optimization methodology.
Using IBM 130nm CMOS technology, the proposed current source transistor noise
optimization methodology has been applied to design a noise optimized charge sensitive
amplifier. With the low single channel power consumption in the range of a few mW, the
analog front-end signal processing channel features a noise optimized charge sensitive
amplifier and a first order CR-RC pulse shaper with short peaking time. The results of the
pre-layout and the post-layout simulations make the design a very good candidate for the
low-power system integration. Future directions for this thesis are now being considered,
which include designing the additional analog-to-digital block for the signal extraction
iv
circuitry as well as developing the complete and optimized layout for the targeted 16
analog front-end signal processing channels.
Keywords: Analog front-end signal processing channel; charge sensitive amplifier
(CSA); CR-RC pulse shaper; equivalent noise charge (ENC); noise
optimization methodology; reset network (Rf); adaptive continuous reset;
pole-zero cancellation; thermal noise; flicker noise
v
Acknowledgements
I would like to thank my family for their support and patience. A special thanks to my
girlfriend, Sophie Yue, who has prayed for me almost every day and accompanied me
during my highs and lows. Thanks to our Lord, Jesus Christ, for everything.
I would like to express my deepest appreciation to my senior supervisor Dr. Marek
Syrzycki for giving me the opportunity to conduct research in the area of Analog IC
design at SFU. Dr. Syrzycki’s has provided me with the valuable guidance and advice for
this work. I truly appreciate for his encouragement, patience, and constructive criticisms
during these two years of my M.A.Sc. studies. Thanks also to my thesis committees, Dr.
Hobson and Dr. Parameswaran, for reviewing my thesis and offering their suggestions on
improvements. In addition, thanks to the chair, Dr. Beg, for holding my thesis defense.
Finally, I want to express my appreciation to my colleagues in the VLSI design lab, Eddy
Lin, Cheng Zhang, and Thomas Au for their timely support and strong input to my
research work. I am very grateful for having this journey with you guys.
vi
Table of Contents
Approval ................................................................................................................................. ii
Abstract .................................................................................................................................. iii
Acknowledgements .................................................................................................................v
Table of Contents.................................................................................................................. vi
List of Tables ......................................................................................................................... ix
List of Figures .........................................................................................................................x
List of abbreviation ............................................................................................................ xiv
Chapter 1 Introduction ......................................................................................................1
1.1 Pixelated semiconductor radiation detector .............................................................1
1.2 Radiation detector system .........................................................................................2
1.3 Motivation..................................................................................................................4
1.4 Organization of Thesis ..............................................................................................6
Chapter 2 Analog front-end signal processing channel overview...............................7
2.1 Detector modeling .....................................................................................................8
2.2 Charge sensitive amplifier ........................................................................................8
2.2.1 The output response of the charge sensitive amplifier ....................................9
2.2.2 Preamplifier structure ......................................................................................10
2.2.3 Reset network implementation .......................................................................12
vii
2.2.4 Adaptive continuous reset network ................................................................13
2.3 Pulse shaper .............................................................................................................15
2.3.1 The peaking time and the pulse amplitude of the pulse shaper ....................16
2.3.2 Pole-zero cancellation .....................................................................................17
Chapter 3 Noise optimization of the charge sensitive amplifier ...............................20
3.1 Noise measurement scheme - ENC ........................................................................21
3.2 Input transistor optimization methodology for the CSA with fast shaper ...........22
3.3 Current source transistor noise optimization methodology for CSA ...................26
Chapter 4 Design of charge sensitive amplifier ...........................................................30
4.1 Preamplifier design .................................................................................................31
4.1.1 Formulas for the mid-band gain and the frequency response of the
preamplifier .....................................................................................................................32
4.1.2 The geometries design for the preamplifier transistors .................................34
4.1.3 AC simulation of the preamplifier (open-loop) .............................................37
4.2 The reset network and the feedback capacitor design...........................................38
Chapter 5 Pulse shaper design .......................................................................................40
5.1 The output response of the pulse shaper ................................................................40
5.2 Passive component design for the pulse shaper ....................................................42
5.3 Shaper amplifier design ..........................................................................................45
Chapter 6 The simulation of the analog front-end signal processing channel ........48
viii
6.1 The power characteristics .......................................................................................49
6.2 Transient simulation ................................................................................................51
6.2.1 The charge-to-voltage conversion rate of the analog front-end signal
processing channel ..........................................................................................................51
6.2.2 High counting rate simulation.........................................................................55
6.3 Noise simulation ......................................................................................................58
Chapter 7 The layout design ...........................................................................................61
7.1 The detailed layout for component ........................................................................63
7.2 The post-layout simulation .....................................................................................66
7.2.1 The post-layout transient simulation ..............................................................66
7.2.2 Post-layout noise simulation ...........................................................................73
7.3 Performance summary ............................................................................................74
Chapter 8 Conclusion and future work ........................................................................76
References ..............................................................................................................................78
Appendix A. The test of the current source noise optimization methodology ...........82
ix
List of Tables
Table 1.1 The design specification of the analog front-end signal processing channel.......5
Table 3.1 Shaping coefficient for the semi-Gaussian shapers of different order [4] ........24
Table 4.1 MOSFET parameters of 3.3V MOSFET in IBM 130nm CMOS technology ..31
Table 4.2 Calculated optimum aspect ratios and channel length for current source
transistors M4 and M6 ...........................................................................................................35
Table 5.1 The values of the resistors and capacitors for the shaper peaking time (τp)
equivalent of 100ns ................................................................................................................42
Table 6.1 Power consumption summary for single analog front-end signal processing
channel ....................................................................................................................................51
Table 6.2 The noise contribution from each component in the analog front-end signal
processing channel .................................................................................................................59
Table 7.1 The pre-layout and post-layout performance summaries for the analog front-
end signal processing channel ...............................................................................................74
Table 7.2 Performance comparisons between this work and other related works ............74
Table 8.1 The pre-layout and post-layout performance summaries for the analog front-
end signal processing channel ...............................................................................................77
Table A.1 Theoretical and values and their simulated results for current source
transistor M4 and M6 in four preamplifiers.......................................................................85
x
List of Figures
Figure 1.1 The CZT pixelated semiconductor radiation detector [1] ...................................1
Figure 1.2 The process to create medical nuclear images ....................................................2
Figure 1.3 Medical nuclear images of human brains [4] .....................................................2
Figure 1.4 The radiation detector system with 16 anode front-end signal processing
channels .....................................................................................................................................3
Figure 2.1 Analog front-end signal processing channel .......................................................7
Figure 2.2 The equivalent model of the pixelated detector ..................................................8
Figure 2.3 A current pulse which contains 10fC of input charge (Qin) ................................8
Figure 2.4 The output response of the charge sensitive amplifier for an input current
pulse.........................................................................................................................................10
Figure 2.5 Folded cascode amplifier [9] ..............................................................................11
Figure 2.6 Dual PMOS cascode amplifier [10] ...................................................................11
Figure 2.7 The CSA reset network realized by a resistor-like MOS transistor .................12
Figure 2.8 Adaptive continuous reset implemented with the CSA [11] ............................14
Figure 2.9 The CR-(RC)n pulse shaper diagram .................................................................16
Figure 2.10 The shift of the baseline for the shaper output pulses due to the extra pole of
the reset network.....................................................................................................................17
Figure 2.11 The pole-zero cancellation circuitry implemented within the pulse shaper
[15] ..........................................................................................................................................18
Figure 2.12 The pole-zero cancellation implemented by the transistor Mpz [8] ................19
Figure 3.1 The primary noise contributors of the analog frolnt-end signal processing
channel ....................................................................................................................................20
xi
Figure 3.2 The ENC for the analog front-end signal processing channel ..........................22
Figure 3.3 The input transistor of the preamplifier that adopts dual PMOS cascode
amplifier structure [10] ..........................................................................................................23
Figure 3.4 The current source transistors for the preamplifier that adopts dual PMOS
cascode amplifier structure [10] ............................................................................................26
Figure 4.1 The targeted value of the detector capacitance (Cdet), the feedback capacitance
(Cf), and the shaper peaking time (τp) for the analog front-end signal processing channel
.................................................................................................................................................30
Figure 4.2 The preamplifier structure ..................................................................................32
Figure 4.3 Major parasitic capacitances associated with poles of the frequency
characteristics in the preamplifier .........................................................................................33
Figure 4.4 The targeted value of the biasing current and the overdrive voltages for the
core amplifier ..........................................................................................................................35
Figure 4.5 The preamplifier structure with transistors’ aspect ratios .................................36
Figure 4.6 The gain magnitude of the preamplifier.............................................................37
Figure 4.7 The phase of the preamplifier .............................................................................37
Figure 4.8 The transistor level implementation for the capacitor ......................................39
Figure 4.9 Adaptive continuous reset implemented with the reset network of the CSA ..39
Figure 5.1 The 1st order CR-RC pulse shaper design implemented with the analog front-
end signal processing channel ...............................................................................................40
Figure 5.2 The 1st order CR-RC pulse shaper design using transistor implementation for
passive components ................................................................................................................43
Figure 5.3 The shaper resistor Ri implementation ...............................................................44
Figure 5.4 The shaper amplifier design ...............................................................................46
xii
Figure 5.5 The gain magnitude of the shaper amplifier ......................................................47
Figure 5.6 The phase of the shaper amplifier ......................................................................47
Figure 6.1 The analog front-end signal processing channel integration ............................49
Figure 6.2 The sharing of the biasing circuits among 16 processing channels .................50
Figure 6.3 The input current pulse for a radiation event with input charge Qin =10fC.....52
Figure 6.4 The CSA output response for Qin = 10fC ..........................................................52
Figure 6.5 The shaper output response for Qin = 10fC........................................................53
Figure 6.6 The shaper output responses vs. the input charge .............................................54
Figure 6.7 The shaper output amplitude vs. the input charge .............................................54
Figure 6.8 The input current pulses with frequency of 100kHz .........................................55
Figure 6.9 The shaper output response for input pulse frequency of 100kHz ...................56
Figure 6.10 The input current pulses with frequency of 500kHz .......................................56
Figure 6.11 The shaper output response for input pulse frequency of 500kHz.................57
Figure 6.12 The input current pulses with frequency of 1MHz .........................................57
Figure 6.13 The shaper output response for input pulse frequency of 1MHz ...................58
Figure 6.14 The ENC for the designed signal processing channel vs. the detector
capacitances ............................................................................................................................60
Figure 7.1 The floor plan for 16 analog front-end signal processing channels .................61
Figure 7.2 The rotated layout for the single signal processing channel without the
adaptive continuous reset .......................................................................................................62
Figure 7.3 The layout division for the analog front-end signal processing channel .........63
Figure 7.4 The layout for the preamplifier and the feedback capacitor .............................64
Figure 7.5 The layout for the biasing network of the preamplifier ....................................64
xiii
Figure 7.6 The layout for the reset network, the pole-zero cancellation circuitry, and the
shaper capacitors.....................................................................................................................64
Figure 7.7 The layout for the shaper amplifier ....................................................................65
Figure 7.8 The layout module for the biasing network of the shaper amplifier ................65
Figure 7.9 The layout module for the shaper resistor .........................................................65
Figure 7.10 The layout module for the adaptive reset network ..........................................66
Figure 7.11 Input current pulse for a radiation event with input charge equal 10fC ........67
Figure 7.12 The CSA output response for Qin = 10fC ........................................................67
Figure 7.13 The shaper output response for Qin = 10fC .....................................................68
Figure 7.14 The shaper output response vs. the input charge .............................................69
Figure 7.15 The shaper output amplitude vs. the input charge...........................................70
Figure 7.16 The shaper output response for the input pulse frequency of 100kHz ..........71
Figure 7.17 The shaper output response for the input pulse frequency of 333kHz ..........71
Figure 7.18 The shaper output response for input pulse frequency of 500kHz.................72
Figure 7.19 The shaper output response for input pulse frequency of 1MHz ...................72
Figure 7.20 The ENC of the designed signal processing channel with the layout
parasitics vs. the detector capacitance ...................................................................................73
Figure A.1 Four CSAs with 4 selected current source noise scaling factors ....................82
Figure A.2 The noise optimized current source transistor geometries for M4 and M6 ....83
Figure A.3 First order CR-RC pulse shaper designed in HSPICE .....................................84
Figure A.4 Simulated ENC for four CSAs designed with current source thermal noise
scaling factor = 10% and the current source flicker noise scaling factor = 10%
to 40% .....................................................................................................................................84
xiv
List of abbreviation
CZT Cadmium zinc telluride
CSA Charge sensitive amplifier
ENC Equivalent Noise Charge
The Equivalent Noise Charge contribution from the thermal noise
of the input transistor in the CSA preamplifier
The Equivalent Noise Charge contribution from the flicker noise of
the input transistor in the CSA preamplifier
The Equivalent Noise Charge contribution from the thermal noise
of the current source transistor in the CSA preamplifier
The Equivalent Noise Charge contribution from the flicker noise of
the current source transistor in the CSA preamplifier
The shot noise from the detector leakage current
The noise from the resistors in the pulse shaper
The noise from the reset network in the CSA
The noise from the transistors in the CSA preamplifier
Qin Input charge
Cf Feedback capacitor
Rf Reset network / Feedback resistor
Cdet Detector capacitance
τp Peaking time of the pulse shaper
Ipulse The input current pulses that model the radiation events
xv
Vout(CSA) The output response of the charge sensitive amplifier
Vout(Shaper) The output response of the pulse shaper
Vsignal(out) The amplitude of the shaper output waveform
Vnoise(out) The r.m.s noise voltage at the shaper output
Kf The flicker noise coefficient of the MOSFET
Cg The gate capacitance of the MOSFET
αf The flicker noise slope coefficient of the MOSFET which is larger
than 1 for PMOS and smaller than 1 for NMOS
k The Boltzmann constant = 1.38×10-23
m2
kg s-2
K-1
T The absolute temperature
Cox The gate oxide capacitance per unit area
gm The transconductance of the MOSFET transistor
ɑw The shaping coefficients for the thermal noise
ɑf The shaping coefficients for the flicker noise
Cov The overlap capacitance per channel width of the MOSFET
The thermal noise scaling factor of the current source transistor
The flicker noise scaling factor of the current source transistor
AV The open-loop gain of the amplifier
Rout The output resistance of the amplifier
GBW The gain-bandwidth product
r.m.s Root mean square
SPECT Single-photon emission computed tomography
PET Positron emission tomography
1
Chapter 1 Introduction
1.1 Pixelated semiconductor radiation detector
Over the years, the rapid improvement for the pixelated semiconductor radiation detector
system such as the CdZnTe (CZT) detection system has led to an increase in the number
of medical nuclear imaging applications including SPECT and PET imaging [1]. CZT is
a semiconductor that can directly convert X-ray or Gamma-ray photons into electron and
hole pairs in the room temperature [2]. A strong electric field (of the order of several
hundreds of volts per centimeter) is applied to sweep the electrons and holes to the
electrodes of cathode and pixelated anodes respectively (Figure 1.1) [1]. The sweeping of
the electrons and holes induces an electrical current pulse with time duration in the order
of nanoseconds [3]. By integrating the current pulse, the signal charge that is proportional
to the absorbed gamma photon energy is obtained [3].
Figure 1.1 The CZT pixelated semiconductor radiation detector [1]
Cathode plane (-500 ~ -1000V)
Readout electronics
Incident gamma ray
Pixelated anodes (GND)
CZT detector
Strong electric field
2
The thickness of CZT detector varies according to the energy requirement in the
application. Typical crystal thickness is in the range of a few mm for low radiation
energy application and is as big as 15mm for high energy application [2].
1.2 Radiation detector system
The process of creating medical nuclear images from the radiation detector system
consists of three major steps: injection of the radioactive materials, radiation detection,
and computer analysis and image reconstruction, as shown in shown in Figure 1.2. The
patients are first injected with the radioactive material into their bodies prior to the
medical scanning. During the scanning process, the radiation detector system detects the
X-ray or Gamma-ray photons from the patients’ bodies and generates the corresponding
electrical signals [2]. A computer then processes the output electrical signals of the
radiation detectors and generates the medical images similar to those shown in Figure 1.3
[4].
Figure 1.2 The process to create medical nuclear images
Figure 1.3 Medical nuclear images of human brains [4]
Injection of the
radioactive material
Radiation
detection
Computer imaging
3
The radiation detector system consists of three major blocks: pixelated semiconductor
radiation detector, the analog front-end signal processing channel with the low noise
characteristics, and signal extraction (Figure 1.4). The pixelated detector means that
detector’s anode consist of an n × n array of pixels, while detector’s cathode is one plate
(no pixels). For example, the illustrated pixelated detector with the anode consisting of
4x4 pixel array is shown in Figure 1.4.
Preamplifier
Qin
Pulse ShaperSignal
Extraction
4x4 pixelated semiconductor
radiation detector Analog front-end signal
processing channel
(one channel per pixel)
Computer
post-processing
CSA(One per pixel)
Radiation detector system
Reset
Figure 1.4 The radiation detector system with 16 anode front-end signal processing channels
Each anode pixel (Figure 1.4) is an input to an individual readout electronics consisting
of analog front-end signal processing channel and the signal extraction block. The
radiation event creates a charge signal (Qin) on one of detector pixels (anode). The size of
the electron cloud reaching the anode is much smaller than pixel dimensions, therefore
the x-y coordinates of the pixel producing the signal charge Qin are recognized as the x-y
coordinates of the gamma photon radiation event. The low noise analog front-end signal
processing channel consisting of a charge sensitive amplifier (CSA) and a pulse shaper
produces a Gaussian-like pulse that carries the information of energy magnitude and the
timing. The signal extraction block processes the Gaussian pulse generated by the analog
front-end signal processing channel and quantize the pulse amplitude for measurement of
4
the photon energy, photon counting/integration, and the pulse peaking time for computer
post-processing [5].
1.3 Motivation
The scope of this thesis encompasses a low noise analog front-end signal processing
channel for radiation detector systems. The design includes a charge sensitive amplifier
(CSA) and a pulse shaper. The CSA amplifies the detector charge signals to the voltage
signal with a reset network and the pulse shaper filters the amplified signal before the
signal extraction step. The most important figures of merit for the analog front-end signal
processing channel are:
1. Equivalent noise charge (ENC) – the noise figure of merit that corresponds to the
noise charge of the analog front-end signal processing channel.
2. Single channel power consumption – the power consumption for the analog front-
end signal processing channel.
3. Input signal charge range – the input charge range that the signal processing
channel can process with a linear charge-to-voltage conversion gain.
4. Shaper peaking time (τp) – corresponds to the peaking time of the shaper output
pulse.
In order to achieve the high detectability of the charge signals, the low noise performance
corresponding to the low ENC is necessary for the radiation system. Targeting the high
signal-to-noise ratio of 200:1 recommended for the CZT radiation detector system [6],
the ENC is required to be less than a few hundred electrons for a typical high energy
application with the signal charge of 4fC [3]:
5
4fC200
0.02fC 125 electrons
inS Q
N ENC ENC
ENC
(1.1)
In high density pixelated detectors where tens or hundreds of pixels are integrated, low
single channel power consumption in the range of a few mW is required to minimize the
total power consumption. In the high rate application where the interval between the
radiation events is short, a short shaper peaking time (smaller than 100ns) is commonly
chosen to prevent the pulse overlap [7]. The design specifications based on the low noise,
low power, and short shaper peaking time requirements targeted in this research are given
in Table 1.1.
Table 1.1 The design specification of the analog front-end signal processing channel
ENC
(in electrons)
Power per
channel
Input charge
range
Shaper
peaking time
This work <200 <6mW Up to 50fC 100ns
The objectives of this thesis include:
To investigate the major noise contributors in the analog front-end signal
processing channel
To develop a methodology that optimizes the major noise sources in the charge
sensitive amplifier
To design and implement the low-noise analog front-end signal processing
channel with a short peaking time using the IBM 0.13μm CMOS technology
The major contributions of this thesis have been the development of a methodology to
optimize the primary and the secondary transistor noise sources in the charge sensitive
6
amplifier to enhance the overall low noise performance, and the evaluation of the
performance degradation due to physical integration in the deep-submicron (DSM)
CMOS technology.
1.4 Organization of Thesis
This thesis is divided into following chapters: Chapter 2 will introduce each component
in the analog front-end signal processing channel. Chapter 3 will discuss the noise
optimization methodology developed for the charge sensitive amplifier. In Chapter 4 the
design procedure of the charge sensitive amplifiers is covered. The design details of the
pulse shaper are to be presented in Chapter 5. The timing and noise simulation of the
designed analog front-end processing channel are presented in Chapter 6. In Chapter 7
the CMOS transistor layout for the analog front-end signal processing channel is
presented with the post-layout simulation results. Chapter 8 concludes the work of this
thesis and discusses the future research.
7
Chapter 2 Analog front-end signal processing
channel architecture
When a radiation event occurs, a weak charge signal (Qin) proportional to the radiation
energy is generated in the pixelated semiconductor radiation detector (Figure 2.1). This
weak charge pulse is integrated onto the feedback capacitance (Cf) of the charge sensitive
amplifier to create a voltage pulse with the magnitude equal to the ratio of the input
charge (Qin) to the feedback capacitance (Cf). The reset network (Rf) is used for
preventing the CSA from saturation by discharging its output. The pulse shaper, which is
used to improve the signal to noise ratio, takes the voltage pulse and creates a Gaussian-
like pulse with peaking time equal τp. This Gaussian-like pulse which carries the time and
energy information will later be extracted in signal extraction circuitry.
Figure 2.1 Analog front-end signal processing channel
8
2.1 Detector modeling
During the radiation event, the electrons and holes are swept into the electrodes and give
rise to a current pulse (Ipulse) with time duration in the order of nanoseconds, as discussed
in Section 1.1 [3]. The equivalent detector circuit is shown in Figure 2.2 where the
semiconductor detector pixel is modeled as a capacitor (Cdet) in parallel with the current
pulse (Ipulse) [3].
DetectorCdet
Radiation
event Ipulse
Figure 2.2 The equivalent model of the pixelated detector
The accumulated charge (Qin) that is proportional to the absorbed gamma photon energy
is equivalent of the integration for one current pulse (Ipulse) [3]. An example for one
radiation event equivalent to the charge of 10fC is shown in Figure 2.3.
10ns
1μA
Ipulse
Figure 2.3 A current pulse which contains 10fC of input charge (Qin)
2.2 Charge sensitive amplifier
Charge sensitive amplifiers (CSA) are essential components in the analog front-end
signal processing channel (Figure 2.1). The charge sensitive amplifier includes a
preamplifier, feedback capacitor (Cf), and the reset network (Rf). A CSA senses the
9
electric charge collected in the pixelated semiconductor detector (Cdet) and converts its
charge into analog voltage domain signal through feedback capacitor (Cf). As a result of a
series of charge pulses reaching the CSA input, the total charge accumulated by the
feedback capacitor (Cf) may lead to the amplifier saturation. In order to discharge the
accumulated charge, a straightforward solution is to use a feedback resistor (Rf) parallel
to the feedback capacitor (Cf) [8].
2.2.1 The output response of the charge sensitive amplifier
The CSA output response to an input current pulse carrying charge Qin is in the complex
frequency domain equal [8]:
By using the inverse Laplace transform of the function we can derive the CSA output
response to an input charge in the time domain [8]:
where τf is the discharging time of the CSA output and is equal to the product of Cf and
Rf. The charge-to-voltage conversion gain is equal to the inverse value of the feedback
capacitor (Cf). As illustrated in Figure 2.4, for a CSA with feedback capacitance (Cf)
equal 100fF, feedback resistor (Rf) equal 50MΩ, and the input charge (Qin) equivalent of
10fC, the CSA output response is a voltage pulse with the amplitude equivalent of
( )( )
1
f
out CSA in
f f
RV s Q
sR C
(2.1)
( )( ) f
t
inout CSA
f
QV t e
C
(2.2)
10
100mV and the discharging time for 5μs. The charge-to-voltage gain of the CSA is equal
to 10mV/fC.
Figure 2.4 The output response of the charge sensitive amplifier for an input current pulse
2.2.2 Preamplifier structure
The major design requirements for the preamplifier are the low noise performance and
the high mid-band gain. Since the noise of the preamplifier is usually dominated by its
input transistor, the task of the noise optimization is focused on the input transistor
design. In CMOS technology, there are P-type and N-type MOS transistors available. P-
type MOS transistor is characterized by a lower flicker noise than its NMOS counterpart.
Thus, PMOS input transistor is usually chosen for the preamplifier to achieve the better
noise performance. In order to create the high mid-band gain, two amplifier structure are
usually considered: folded cascode amplifier structure (Figure 2.5) and dual PMOS
cascode amplifier structure (Figure 2.6).
11
M1
M6
M5
M3
M2
M4
Out
In
Vb3
Vb5
Vb6
Vb2
Vb4
VDD
Id1=Id4-Id6 Id6
Id4
Figure 2.5 Folded cascode amplifier [9]
M1
M6
M5
M3
M2
M4Out
In
Vb3
Vb5
Vb6
Vb2
Vb4
VDD
Id1=Id4+Id6
Id6Id4
Dual PMOS
Figure 2.6 Dual PMOS cascode amplifier [10]
The bias currents of the input transistor M1 and the current source transistors M4 and M6
for the two amplifier structures are given as:
12
Based on the comparison between Eq.(2.3) and Eq.(2.4), the bias current of the input
transistor (Id1) is bigger in the dual PMOS cascode amplifier structure given that both
amplifier consume the same amount of power. Therefore, the dual PMOS cascode
amplifier structure has the advantage of maximizing the transconductance (gm) of the
input transistor to achieve the higher mid-band gain.
2.2.3 Reset network implementation
In order to meet the low noise performance required for the front-end detection channel,
the feedback resistance (Rf) needs to be set in the Mega or Giga ohm range depending on
the amount of detector leakage current [5]. However, such high resistance is hard to
realize in the CMOS technology. Therefore, most CSA designers have used the MOSFET
transistor (Mf) to create the high value reset resistance [11] (Figure 2.7).
Preamplifier
Cdet
Cf
Qin
VG
To ShaperIpulse
Mf
Vout(CSA)
Figure 2.7 The CSA reset network realized by a resistor-like MOS transistor
The feedback resistance Rf seen between the drain and the source terminal of the MOS
transistor working in the linear region is calculated as [11]:
1 4 6- for folded cascode structured d dI I I (2.3)
1 4 6 for dual PMOS cascode structured d dI I I (2.4)
13
where μ is the mobility of the charge carriers in MOS transistors, Cox is the oxide
capacitance, (Wf /Lf) is the aspect ratio of the feedback transistor, VGS(f) is the gate-to-
source voltage, and the VT(f) is the threshold voltage. To achieve a high value resistance,
the MOS transistor usually has long channel length and short channel width to minimize
the (W/L) ratio in Eq.(2.5).
2.2.4 Adaptive continuous reset network
The feedback resistance formula shown in Eq.(2.5) depends on the gate-to-source voltage
VGS(f) and threshold voltage (VT(f)). These two voltage terms of the MOS transistors may
differ from chip to chip due to the process variations. In order to compensate the process
variation, the adaptive continuous reset network has been proposed [11]. An example
implementation of the adaptive continuous reset network is shown in Figure 4.9 where
the preamplifier adopts the dual PMOS cascode amplifier structure. The level shifter is
usually implemented at the output of the amplifier in order to restore the DC potential of
the CSA output (Vout(CSA)) to be equal to the CSA input (Vin(CSA)):
The aspect ratio for the transistor Mf0 is the multiple of that for the feedback transistor Mf
by the factor of n. Since the transistor M1R is the exact copy of the input transistor M1
and since they are also biased with the same amount of current, their gate-to-source
voltage should be closely matched and hence, the source voltage of the transistor Mf0 and
that of the transistor Mf are the same:
( ) ( )
1
( / )( )f
ox f f GS f T f
RC W L V V
(2.5)
( ) ( )out CSA in CSAV V (2.6)
14
M1
M6
M5
M3
M2
M4
Vb3
Vb5
Vb6
Vb2
Vb4
Id1 Cdet
Qin
Cf
Level
shifter
Mf
Mf0=(Mf)n
M1R=M1
Id1R
= Id1If
Adaptive continuous reset
Vout(CSA)
Vin(CSA)
V1R
Figure 2.8 Adaptive continuous reset implemented with the CSA [11]
From Eq.(2.5) and Eq.(2.6), the gate-to-source voltages of the feedback transistor Mf and
the transistor Mf0 are equal:
Given that the threshold voltage for the feedback transistor Mf and the transistor Mf0 are
closely matched, Eq.(2.8) is rearranged to be equivalent of the overdrive voltage (Vov) for
the transistor Mf0 [11]:
( ) 1in CSA RV V (2.7)
( ) ( 0)GS f GS fV V (2.8)
( ) ( ) ( 0) ( 0)
( 0)
0 0
2 2
( / ) ( / )
GS f T f GS f T f
ov f
f f
ox f f ox f f
V V V V
V
I I
C W L C n W L
(2.9)
15
Substituting Eq.(2.9) to Eq.(2.5), a new expression for the feedback resistance (Rf) that is
independent of the gate-to-source voltage VGS(f) and the threshold voltage (VT(f)) for the
feedback transistor Mf is derived [11]:
2.3 Pulse shaper
The pulse shaper takes the output of the CSA and transforms the narrow current pulse
from the detector (Figure 2.3) into a broader pulse with the peaking time equal τp (Figure
2.9), aiming to achieve two advantages [3]:
The broader pulse generated by the pulse shaper improves the signal-to-noise
ratio of the analog front-end processing channel
The broader pulse facilitates the measurement of the pulse amplitude (Vsignal(out))
with a gradually rounded maximum at the peaking time equal τp.
The pulse shaper consists of two stages: 1st stage CR differentiator and 2
nd stage RC
integrator (Figure 2.9). As the voltage pulse corresponding to a radiation event is
generated at the output of the CSA, a Gaussian-like pulse (Vout(Shaper)) carrying the timing
and energy information is formed at the shaper output. More than one RC integrator is
adopted if the more symmetrical pulse is desired for certain applications [3].
( ) ( )
1
( / )( )
2 ( / )
f
ox f f GS f T f
f ox f f
RC W L V V
n
I C W L
(2.10)
16
1st
Stage:
CR-Differentiator
2nd
Stage:
RC-Integrator (n integrators)
Vout(CSA) Vout(Shaper)
Cd
Rd Ci
Ri Ri
Ci Ci
Ri
1st 2ndnth
= Qin/Cf
Vout(CSA)
Time
Vout(Shaper)
Time
τp
τf
Design condition:
RdCd = RiCi
From the charge
sensitive amplifier
n
insignal(out) n
f
Q nV =
C n!e
Figure 2.9 The CR-(RC)
n pulse shaper diagram
2.3.1 The peaking time and the pulse amplitude of the pulse shaper
The transfer function of the shaper is given as [12]:
where n is the number of the integrators that corresponds to the order of the shaper and τ
is the time constant of the differentiator and integrator given as:
The peaking time of the pulse (Figure 2.9), τp, is related to the time constant:
The amplitude of the shaper output pulse (Vsignal(out)) is given as [13]:
( )
( )
( ) 1( )
( ) 1 1
n
out Shaper
out CSA
V s sH s
V s s s
(2.11)
d d i iR C RC (2.12)
p n nRC (2.13)
( )!
n
insignal out n
f
Q nV
C n e (2.14)
17
Increasing the order of the shaper will result in a more symmetrical output pulse but with
larger peaking time (τp). For a high counting rate radiation detector system where the
interval between the times of arrival for the two continuous input current pulses (Ipulse)
can be short, the peaking time (τp) must be limited to avoid overlapping the pulses.
Therefore, a fast shaper (peaking time (τp) < 100ns) is usually adopted for the high rate
application. The important design requirements of the pulse shaper include:
Low power consumption compared to the CSA
Low noise performance
Smaller layout area
2.3.2 Pole-zero cancellation
As shown in Eq.(2.1), the reset network that is used for discharging the CSA output
generates an extra pole, equivalent of the product of the feedback capacitor (Cf) and
feedback resistor (Rf). This extra pole from the reset network causes a shift on the
baseline of the shaper output pulse that may lead to the loss of resolution [14] (Figure
2.10).
Vout(Shaper)
Time
Shift in baseline
Loss in resolution
Figure 2.10 The shift of the baseline for the shaper output pulses due to the extra pole of the reset network
18
In order to stabilize the baseline for the shaper pulse, the pole-zero cancellation circuitry
is implemented within the pulse shaper [14] (Figure 2.11). The idea of the pole-zero
cancellation is to implement an extra zero in the CR-Differentiator stage by adding a
resistor (Rpz) in parallel with the capacitor (Cd) such that it will nullify the reset network
pole [14]:
1st
Stage:
CR-Differentiator
2nd
Stage:
RC-Integrator (n integrators)
Vout(Shaper)
Cd
RdCi
Ri
1st 2ndnth
Preamplifier
Cdet
Cf
Qin
Rpz
Reset (Rf) Pole-zero
cancellation
Ri Ri
Ci Ci
Extra pole
Vout(CSA)Ipulse
Vout(Shaper)
Time
Ipulse
Time
Figure 2.11 The pole-zero cancellation circuitry implemented within the pulse shaper [15]
In order to fulfill Eq.(2.14), the pole-zero cancellation resistor Rpz can be implemented by
the transistor Mpz (Figure 2.12) such that its aspect ratio and the value of the capacitor
(Cd) are related to the aspect ratio of the feedback transistor (Mf) and the value of the
feedback capacitor (Cf) by [5] :
pz f
W WN
L L
(2.16)
f f pz dR C R C (2.15)
19
d fC N C (2.17)
where N is an integer with its value greater than one.
1st
Stage:
CR-Differentiator
2nd
Stage:
RC-Integrator (n integrators)
Vout(Shaper)
Cd
= NxCf RdCi
Ri
1st 2ndnth
Preamplifier
Cdet
Cf
Qin
Pole-zero
cancellation
Ri Ri
Ci Ci
Vout(CSA)Ipulse
Mf
Mpz=
NxMf
Adaptive continuous reset
Figure 2.12 The pole-zero cancellation implemented by the transistor Mpz [8]
20
Chapter 3 Noise optimization of the charge sensitive
amplifier
Low-noise behavior is necessary for the analog front-end signal processing channel, in
order for the radiation detector to achieve high resolution detectability, and hence
minimizing the dosage of the radioactive exposure to the patients. The noise sources in
the analog front-end signal processing channel include the transistors of the preamplifier
, the detector leakage current
, the reset network , and the
resistors in the shaper ( ) (Figure 3.1).
Figure 3.1 The primary noise contributors of the analog frolnt-end signal processing channel
In order to minimize the total noise of the analog front-end signal processing channel,
these mentioned major noise contributors have to be optimized. However, the noise
contribution from the detector leakage current and the shaper resistor
( ) are fixed by the type of the detector used and the required peaking time (τp)
21
of the target application. Therefore, more works are focused on optimizing the other two
major noise sources: the transistors in the preamplifier and the reset
network . The existing input transistor optimization methodology for the
charge sensitive amplifier will be discussed. In addition, our proposed current source
transistor optimization methodology that compliments the input transistor optimization
methodology will be presented.
3.1 Noise measurement scheme - ENC
The noise of the front-end signal processing channel is usually expressed in the form of
Equivalent Noise Charge (ENC). Equivalent noise charge is defined as the input noise
charge of the front-end signal processing channel [3].
The noise simulation in HSPICE is able to find the r.m.s noise voltage at the shaper
output (Vnoise(rms)) (Figure 3.2). In order to calculate the ENC using HSPICE simulation,
Eq.(3.1) needs to be rearranged to include the r.m.s noise voltage (Vnoise(rms)). The
rearrangement is done by first considering the S/N ratio of the analog front-end signal
processing channel:
( )
( )
signal out in in
noise rms noise
VS Q Q
N V Q ENC (3.2)
where Vsignal(out) is the peak signal amplitude at the shaper output and Qin is the input
signal charge (Figure 3.2).
noiseENC Q (3.1)
22
Figure 3.2 The ENC for the analog front-end signal processing channel
Rearranging Eq.(3.1) with Eq.(3.2), the ENC measurement scheme for the analog front-
end signal processing channel can be derived as follows [16].
For example, for an input charge signal Qin = 10.2fC, Vsignal(out) = 36mV, and Vnoise(rms) =
33μV, ENC is equal to:
3.2 Input transistor optimization methodology for the CSA
with fast shaper
The goal of input transistor optimization methodology is to find the optimum geometry of
the input MOSFET for the preamplifier (Figure 3.3) which results in the lowest noise
contribution for the analog front-end signal processing channel. This methodology is
( )
( )
[electrons]noise rms in
noise
signal out
V QENC Q
V q (3.3)
19
33μV 10.2fC58 [r.m.s electrons]
33mV 1.6 10 CENC
(3.4)
23
based on the assumption that the input MOSFET noise is the most dominant noise source
in the preamplifier of the CSA.
Preamplifier
Cf
Qin
Pulse Shaper
H(s), τ
M1
M6
M5
M3
M2
M4
Vb3
Vb5
Vb6
Vb2
Vb4
Input
TransistorIn
Out
CdetIpulse
Reset(Rf)
Id(in)
Figure 3.3 The input transistor of the preamplifier that adopts dual PMOS cascode amplifier structure [10]
The noise components within the input MOSFET are thermal noise and flicker (also
called 1/f) noise and their respective ENC contributions for the analog front-end signal
processing channel is represented by [5]:
2
det2
( ) 2
( ) 4Thermal noise :
f g
in th w
m p
C C C kTENC a n
q g
(3.5)
2
det2
(1/ ) 12
( ) (2 )Flicker noise :
f
f
f g f
in f f
ox p
C C C KENC a
q C WL
(3.6)
where:
- n is the sub-threshold slope coefficient of the MOSFET with a typical value of 1.25
24
- γ is a dimensionless coefficient of the MOSFET that is equal to (1/2) in weak
inversion and (2/3) in strong inversion
- αf is the flicker noise slope coefficient of the MOSFET which is larger than 1 for
PMOS and smaller than 1 for NMOS
- k is the Boltzmann constant
- T is the absolute temperature
- Cox is gate oxide capacitance per unit area
- Kf is the technology dependent flicker noise coefficient of the MOSFET
- gm is the transconductance of the MOSFET transistor
- ɑw and ɑf, are the shaping coefficients for the thermal noise and flicker noise
respectively. Their values corresponding to the shaper order are presented in Table
3.1.
Table 3.1 Shaping coefficient for the semi-Gaussian shapers of different order [5]
Shaper order ɑw ɑf
1 0.92 0.59
2 0.82 0.54
3 0.85 0.53
4 0.89 0.52
5 0.92 0.52
6 0.94 0.51
The gate capacitance of input MOSFET (Cg) is approximated by Eq.(3.7) [17]:
2
23
g ov oxC C W C WL (3.7)
25
where Cov is overlap capacitance per unit width for drain and source. For a charge
sensitive amplifier followed by a fast shaper (shaping time τp usually smaller than 100ns)
and due to the fact that the input transistor is usually p-MOS, in which the flicker noise
component is much smaller than in an equivalent n-MOS, thermal noise contribution will
dominate over the flicker noise contribution for the input transistor [17]:
Hence, the total noise contribution from input transistor ( can be simplified as
equal to the thermal noise of the input transistor :
The optimum input transistor geometry that corresponds to the minimum input transistor
noise ( ) can be derived by differentiating its thermal noise contribution (
)
with respect to the input transistor channel width (W) [17]:
2
( ) det
min
06 2
in th f
ov ox
ENC C CW
W C C L
(3.10)
Note that the minimal channel length Lmin must be used in Eq.(3.10) also for the purpose
of minimizing the input transistor thermal noise contribution ) in Eq.(3.5) by
maximizing its transconductance (gm) [13]. Once the optimized input transistor geometry
is derived from Eq.(3.10), the corresponding bias current of the input transistor (I(in)) is
determined by defining the value of its overdrive voltage (Vov):
( )2
( / )
in
ov
ox
IV
C W L (3.11)
2 2
( ) (1/ )in th in fENC ENC (3.8)
2 2 2 2
( ) (1/ ) ( )in in th in f in thENC ENC ENC ENC (3.9)
26
By rearranging Eq.(3.11), the bias current of the input transistor (I(in)) is related to its
overdrive voltage (Vov) by:
2
( )2
oxin ov
C WI V
L
(3.12)
3.3 Current source transistor noise optimization methodology
for CSA
The input transistor has been usually seen as the most dominant noise source in the
preamplifier of the CSA, and the methodology to optimize its geometry for minimum
noise has been well established [13]. This methodology treats the noise coming from the
current source transistors (Figure 3.4) that bias the CSA input stage as secondary.
However, in a deep submicron CMOS processes that use low supply voltages, the noise
coming from other CSA components, especially from current source transistors, becomes
significant [18], and in extreme cases may dominate CSA noise characteristics. In order
to optimize the current source transistor noise, the noise optimization methodology that
ensures its noise contribution to be a small fraction of the input transistor noise is
proposed.
M1
M6
M5
M3
M2
M4Out
In
Vb3
Vb5
Vb6
Vb2
Vb4
VDD
Current source
transistor Current source
transistor
input
transistor
Figure 3.4 The current source transistors for the preamplifier that adopts dual PMOS cascode amplifier
structure [10]
27
The proposed current source MOSFET optimization methodology aims to find the
optimum current source transistor aspect ratios such that their noise contribution becomes
a small fraction of the input transistor MOSFET noise contribution. The ENC
contributions for the thermal and flicker noise of the current source transistor noise are
[9]:
2
det ( )2
( ) 2
( ) ( )
( ) 8
3
f g m cs
cs th w
m in p m in
C C C gkTENC a n
q g g
(3.13)
( )
1 ( )
22
det ( ) ( )2
(1/ ) 2
( ) ( ) ( )
( ) (2 ) f
f
cs
cs
f f g f cs m cs
cs f
ox cs cs m inp
a C C C K gENC
q C W L g
(3.14)
where the subscript (in) corresponds to the parameters for input transistor and the
subscript (cs) corresponds to those for current source transistor. In order to optimize the
current source transistor noise such that its noise contribution is a small fraction of the
input transistor noise, the current source noise scaling factor is defined as the ratio of
the current source transistor noise to the input transistor noise:
2
( )
2
( )
cs th
th
in th
ENC
ENC (3.15)
2
(1/ )
1/ 2
( )
cs f
f
in th
ENC
ENC (3.16)
where the thermal noise of the input transistor ( ) is chosen as the common
denominator for approximating the total input transistor noise ( ) in the case of
short shaper peaking time. is the thermal noise scaling factor and is the flicker
28
noise scaling factor for the current source transistor. The current source transistor
optimization aims to make a current source noise contribution as small as possible
fraction of the input transistor noise, i.e.
Rearranging Eq.(3.15) and Eq.(3.16) by using Eqs.(3.5), (3.13), and (3.14), and assume
that the input transistor operates in strong inversion, the formulas for the noise-optimized
geometry of the current source transistors have been derived:
( ) ( ) ( ) ( )2
( ) ( ) ( ) ( )
cs in in d in
th
cs cs in d cs
W W I
L L I
(3.18)
( )
( )
( ) ( ) ( ) ( )
( )
1/ ( ) ( ) ( )
31 (2 )
4 2
f CS
f CS
f cs cs d cs inf
cs
f w in ox in d in
K I LaL
a kT C W I
(3.19)
The following steps show how to apply the current source optimization methodology in
the CSA designs:
1. Based on the defined value of the detector capacitance (Cdet) and feedback
capacitance (Cf), apply the input transistor optimization methodology using
Eq.(3.10) to find out the optimal input transistor geometry.
2. Determine the input transistor biasing current (Id(in)) with Eq.(3.12) by defining its
targeted overdrive voltage (Vov).
3. Determine the current source transistor biasing current (Id(cs)) by the requirement
of the open-loop gain for the preamplifier.
4. Choose the target values for and less than 1.
1/1 and 1th f (3.17)
29
5. Substitute the values for , , and the bias currents into Eq.(3.18) and
Eq.(3.19) to calculate the corresponding noise optimized current source transistor
geometry .
30
Chapter 4 Design of charge sensitive amplifier
In this chapter the design procedure of the charge sensitive amplifier (CSA) is presented.
The major components in the charge sensitive amplifier are the preamplifier and the reset
network (Figure 4.1). The targeted low capacitance semiconductor detector (Cdet) has
been 1pF with the feedback capacitance (Cf) equivalent of 100fF. In order to process high
counting rate event, the short peaking time (τp) equal 100ns has been chosen for a first
order CR-RC pulse shaper.
Preamplifier
Cf
QinCR-RC Shaper
τp = 100ns
CSA
Reset (Rf)
CdetIpulse
Vout(CSA) Vout(shaper)
1pF
100fF
Figure 4.1 The targeted value of the detector capacitance (Cdet), the feedback capacitance (Cf), and the
shaper peaking time (τp) for the analog front-end signal processing channel
The analog front-end signal processing channel has been designed using the 3.3V MOS
transistors provided in the IBM CMOS 130nm technology. The minimum channel length
of the 3.3V MOS transistors is 400nm. The technology parameters derived from the
HSPICE simulation are summarized in Table 4.1.
31
Table 4.1 MOSFET parameters of 3.3V MOSFET in IBM 130nm CMOS technology
Parameters Specification
Process transconductance parameter of PMOS (Kp=μpCox) 75 μA/V2
Process transconductance parameter of NMOS (Kn=μnCox) 268 μA/V2
Gate capacitance per unit area (Cox) 3.75 fF/μm2
Overlap capacitance (Cov) 0.4 fF/μm
Flicker noise coefficient Kf(NMOS) (L=0.4μm) 1.38×10-24
Flicker noise coefficient Kf(PMOS) (L=0.4μm) 1.3×10-24
Flicker noise slope coefficient αf(NMOS) 0.87
Flicker noise slope coefficient αf(PMOS) 1.15
4.1 Preamplifier design
The preamplifier consists of the core amplifier and the level shifter (Figure 4.2). The core
amplifier adopts the dual PMOS cascode structure for its advantage in higher
transconductance (gm) and lower input transistor flicker noise. The level shifter
implemented by the PMOS source follower configuration is used for restoring the DC
potential at the output of the amplifier and decreasing the output impedance when driving
the next stage[19]. The mid-band gain of the level shifter is approximately equal to unity.
The biasing work has been implemented with an ideal current source (Ibias) to bias six
transistors (M2 to M7) in the preamplifier. The power supply voltage (VDD) for the
analog front-end signal processing channel has been 3.3V.
32
M1
M6
M5
M3
M2
M4
Vb3
Vb5
Vb6
Vb2
Vb4
VDD
Id1
Id6Id4
M7
M8
Vb7
VDD
Vout(CSA)
Id8
Core amplifier Level shifter
M9
Ibias
Vb7
VDD
M11
Vb6
VDD
Vb2
M12
M13
VDD
M14
Vb4
M15
VDD
Vb3
M16
M17
VDD
M10
M19
M18
Vb5
Biasing network for the preampifier
Vb3 Vb4 Vb5 Vb6 Vb7Vb2
Preamplifier
Vin(CSA)
Vout(core)
Figure 4.2 The preamplifier structure
4.1.1 Formulas for the mid-band gain and the frequency response of
the preamplifier
By approximating mid-band gain of level shifter equivalent of one, the mid-band gain of
the preamplifier is mostly contributed by the gain of the core amplifier:
1v m outA g R (4.1)
where the output resistance (Rout) is equal:
33
5 3
5 6 3 4
m mout
ds ds ds ds
g gR
g g g g (4.2)
In order to achieve high mid-band gain of the preamplifier, the transconductance of the
input transistor (gm1) has to be maximized based on Eq.(4.1) and the bias current of its
folded output branch (Id6) has to be made small to result in the high output resistance
(Rout). As far as the frequency response is concerned, there are two poles in the
preamplifier: One is the non-dominant pole (p1) and the other one is the dominant pole
(p2). These two poles are associated with the nodes (A and Vout(core)) of the preamplifier
shown in Figure 4.3.
M1
M6
M5
M3
M2
M4
Vb3
Vb5
Vb6
Vb2
Vb4
VDD
M7
M8
Vb7
VDD
Vout(CSA)C1
C2
Vin(CSA)
Vout(core)
A
Figure 4.3 Major parasitic capacitances associated with poles of the frequency characteristics in the
preamplifier
These two poles are given as [9]:
1 1
11
2p
R C
(4.3)
2
12
2 out
pR C
(4.4)
34
where:
1
4
1
m
Rg
(4.5)
1 2 3 4 2 3 4gd gs gd bd bd bdC C C C C C C (4.6)
2 3 5 8 8 3 5gd gd gs gd bd bdC C C C C C C (4.7)
In order to prevent the non-dominant pole (p1) from affecting the circuit performance, the
areas of M2, M3, and M4 transistors have to be kept small in order to minimize their
contributions to the capacitance C1. The gain-bandwidth product (GBW) is given as:
12
22
mv
gGBW A p
C (4.8)
4.1.2 The geometries design for the preamplifier transistors
With the detector capacitance and feedback capacitance defined in Figure 4.1, the input
transistor noise optimization methodology from Eq.(3.10) has been applied to calculate
the optimal input transistor M1 aspect ratio for the minimum channel length of 0.4μm:
The overdrive voltage (Vov) for the input transistor in the preamplifier is defined for the
corresponding output voltage swing of the core amplifier within 0.5 to 2.8V (Figure 4.4).
1
200μm
0.4μm
W
L
(4.9)
35
M1
M6
M5
M3
M2
M4
Vb3
Vb5
Vb6
Vb2
Vb4
VDD
Vout(core)
Vov1=0.2VOutput range =
0.5V ~ 2.8VId1
(800μA)
Id4
(720μA)
Id4
(80μA)
Vov2+ Vov3 =
0.3V
Vov5+Vov6
=0.5V
Vin(CSA)
Figure 4.4 The targeted value of the biasing current and the overdrive voltages for the core amplifier
From Eq.(3.12), the bias current for the input transistor M1 (Id1) is approximately 800μA
corresponding to its overdrive voltage (Vov1) of 0.2V. In order to achieve the high mid-
band gain for the core amplifier, the bias current of its output branch (Id6) has to be made
small to result in the high output resistance (Rout). The bias current (Id6) of 80μA has been
chosen for the output branch (Figure 4.4). The current source transistor noise
optimization methodology has been applied to find the optimal geometry of the current
source transistors M4 and M6. The details of this optimization process are shown in the
Appendix A. The targeted current source thermal noise scaling factor ( has been
chosen as 10% and the current source flicker noise scaling factor ( as 10%. The
noise optimized geometries of the current source transistors M4 and M6 have been
calculated from Eq.(3.18) and Eq.(3.19) and are presented in Table 4.2.
Table 4.2 Calculated optimum aspect ratios and channel length for current source transistors M4 and M6
Noise scaling factor M4
(μm/μm)
M6
(μm/μm)
(W/L) L (W/L) L
10% 10% 1.8 6.0 16.3 2.0
36
The rest of the transistors in the core amplifier (transistors M2, M3, and M5) have been
designed based on the output swing range and their biasing currents specified in Figure
4.4. The biasing network for the preamplifier uses ideal current source of 200μA that in a
final version may be tunable to achieve a uniform performance between individual chips.
The level shifter has been implemented with the help of the HSPICE simulator in order to
restore the output DC potential of the core amplifier (Vout(core) = 2V from simulation) to
the input DC potential (Vin(CSA) = 2.75V from simulation). The preamplifier structure with
all the transistors’ aspect ratio and their biasing currents is shown in Figure 4.5.
M1
M6
M5
M3
M2
M4
Vb3
Vb5
Vb6
Vb2
Vb4
VDD
M7
M8
Vb7
VDD
5/0.4
n=50
5/0.4
n=50
5.5/6
n=26/0.4
n=1
5/0.4
n=8
6.8/2
n=5
3.5/0.4
n=1
6.8/0.4
n=5
M9
200μA
Vb7
VDD
M11
Vb6
VDD
Vb2
M12
M13
VDD
M14
M15
VDD
Vb3
M16
M17
VDD
M10
M19
M18
Vb5
5/1
n=9
5/4
n=4
5/4
n=4
5/2
n=12
7.7/1
n=1
5/2
n=12
5/2
n=175/2
n=17
4.87/1
n=10
4/2
n=8
5/2
n=17
Biasing network for preamplifier
Preamplifier
Vb3 Vb4 Vb5 Vb6 Vb7Vb2
800μA
100μA
207μA 211μA 202μA
331μA
Vout(CSA)
720μA 80μA
Vb4
Vin(CSA)
Figure 4.5 The preamplifier structure with transistors’ aspect ratios
37
4.1.3 AC simulation of the preamplifier (open-loop)
The AC simulation has been done in HSPICE within the frequency range from 1Hz to
10GHz. The open-loop simulations for the gain magnitude and phase are presented in
Figure 4.6 and Figure 4.7. The preamplifier’s mid-band gain has been 78dB, and its gain-
bandwidth product (GBW) has been 1.72GHz.
Figure 4.6 The gain magnitude of the preamplifier
Figure 4.7 The phase of the preamplifier
0
10
20
30
40
50
60
70
80
90
1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10
Ga
in (
dB
)
Frequency (Hz)
0
20
40
60
80
100
120
140
160
180
200
1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10
Ph
ase
(d
eg)
Frequency (Hz)
38
4.2 The reset network and the feedback capacitor design
For the purpose of meeting the low noise performance, the resistance value of the reset
network (Rf) needs to be set in the Mega or Giga ohm range [5]. Such a big resistance
value is hard to realize in the submicron CMOS technology. Thus, this high feedback
resistance is usually achieved by the MOSFET transistors that behave as the resistors
(Figure 4.9). Additionally, the adaptive continuous reset system (Figure 4.9) is
implemented to compensate the process variations [11]. The geometry of the feedback
transistor Mf has been: (W/L)f = 0.5μm/50μm. The transistor M1R is the copy of the input
transistor M1 and is biased by the same amount of current. In order to create the high
feedback resistance, the aspect ratio for the transistor Mf0 has been designed to be 420
times of that for the feedback transistor Mf:
The ideal current source (If) that biases the transistor Mf0 is 1μA and the feedback
resistance Rf has been approximated by Eq.(2.12):
2
2 ( / )
42016MΩ
2 1μA 75 μA/V (0.5μm / 5μm)
f
f ox f f
nR
I C W L
(4.11)
The feedback capacitor (Cf) has been designed using a PMOS transistor by which the
source, the drain, and the body terminals are connected together (Figure 4.8).
0
210μm420
50μmf f
W W
L L
(4.10)
39
Figure 4.8 The transistor level implementation for the capacitor
The geometry of the transistor that behaves like capacitor has been designed (Figure 4.9)
to generate the feedback capacitance (Cf) of 100fF approximated by Eq.(3.7):
22
3
22 0.4(fF/μm) 18μm 3.75(fF/μm)(18μm)(2μm)
3
100fF
f ov oxC C W C WL
(4.12)
Cdet
(1pF)
Qin
To shaper
Mf
Mf0
M1R
Id1R
(801μA)If
(1μA)
Adaptive continuous reset
0.5/50
3/50
n=70
5/0.4
n=50
M9
200μA
Vb7
VDD
M11
Vb6
VDD
Vb2
M12
M13
VDD
M14
Vb4
M15
VDD
Vb3
M16
M17
VDD
M10
M19
M18
Vb5
5/1
n=9
5/4
n=4
5/4
n=4
5/2
n=12
7.7/1
n=1
5/2
n=12
5/2
n=175/2
n=17
4.87/1
n=10
4/2
n=8
5/2
n=17
Biasing network
Vb3 Vb4 Vb5 Vb6 Vb7Vb2
VDD
M1
M6
M5
M3
M2
M4
Vb3
Vb5
Vb6
Vb2
Vb4
VDD
M7
M8
Vb7
VDD
Vout(CSA)
5/0.4
n=40
5/0.4
n=40
5.5/6
n=26/0.4
n=1
5/0.4
n=8
6.8/2
n=5
3.5/0.4
n=1
6.8/0.4
n=5
Preamplifier
Cf (100fF)
I1
(800μA)
6/2
n=3
Figure 4.9 Adaptive continuous reset implemented with the reset network of the CSA
40
Chapter 5 Pulse shaper design
In the high-counting rate application in the range of hundreds of KHz, the time of arrival
between the two adjacent radiation events can be short. In order to minimize the
possibility of pulse overlapping at the shaper output, a fast shaper (with short peaking
time) is required. In this thesis, a simple first order CR-RC pulse shaper structure with
peaking time (τp) equal 100ns has been designed (Figure 5.1). It has been integrated with
the pole-zero cancellation circuitry to stabilize the baseline.
Ri
Ci
Cd
Rpz
Shaper
amplifier
Vout(Shaper)
Vout(CSA)
Ri-A
Ci
Pole-zero
cancellation
Preamplifier
Cdet
Cf
Qin
Reset (Rf)
Ipulse
1st
order CR-RC pulse shaper
Figure 5.1 The 1st order CR-RC pulse shaper design implemented with the analog front-end signal
processing channel
5.1 The output response of the pulse shaper
The transfer function of the 1st order CR-RC pulse shaper (Figure 5.1) is given as:
( )
2
( )
( ) 1
( ) (1 )
out Shaper pz d i
out CSA pz i i
V s sR C R
V s R sR C
(5.1)
41
The CSA output response (Vout(CSA)(s)) given in Eq.(2.1) is substituted into Eq.(5.1) to
derive the shaper output response:
In order to eliminate the extra pole generated by the reset network, the pole-zero
cancellation circuitry composed of the resistor (Rpz) and the capacitor (Cd) is
characterized as [14]:
The equation Eq.(5.1) is used to simplify Eq.(5.2) by canceling the pole of the reset
network:
The first term in Eq.(5.2) is the CSA output step response to an input charge of Qin. The
second term is the typical transfer function of the 1st order CR-RC pulse shaper:
( ) ( )2
2
1( ) ( )
(1 )
1
(1 ) 1
pz d iout shaper out CSA
pz i i
pz d fiin
pz i i f f
sR C RV s V s
R sR C
sR C RRQ
R sR C sR C
(5.2)
pz d f fR C R C (5.3)
( ) 2
2
2
( )(1 )
(1 )
(1 )
f iout Shaper in
pz i i
d iin
f i i
in i d
f i i
R RV s Q
R sR C
C RQ
C sR C
Q sR C
sC sR C
(5.4)
21 order shaper
( )(1 )
st
p
p
sH s
s
(5.5)
42
where the peaking time τp is equivalent of:
Based on Eq.(5.6), the values of the capacitors (Ci and Cd) and resistors (Ri) for the pulse
shaper have been specified to generate the peaking time (τp) equivalent of 100ns (Table
5.1).
Table 5.1 The values of the resistors and capacitors for the shaper peaking time (τp) equivalent of 100ns
Parameters Value
Ri 50kΩ
Ci 2pF
Cd 2pF
5.2 Passive component design for the pulse shaper
The transistor level implementation for the shaper capacitors Cd and Ci (Table 5.1) is
similar with the design for the feedback capacitor (Cf) in the CSA. They are designed by
using the PMOS transistor such that its drain, body, and source terminals are shorted
together (Figure 4.8). In order to create the 2pF capacitor, Eq.(3.7) is used to approximate
the corresponding transistor geometry: (W/L) = (350 μm/2 μm) such that
The calculated geometries for the capacitor Cd and Ci from Eq.(5.7) are tested in HSPICE
for adjustment. Their geometries after the adjustment are shown in Figure 5.2 for
p i i i dRC RC (5.6)
22
3
22 0.4(fF/μm) 350μm 3.75(fF/μm)(350μm)(2μm)
3
2pF
d i ov oxC C C W C WL
(5.7)
43
capacitors marked as Cd, Ci and Ci2. Since the value for the capacitor (Cd) is specified to
be 20 times of the value for the feedback capacitor (Cf), the aspect ratio for the transistor
(Mpz) needs to be 20 times of that for the feedback transistor (Mf), for properly canceling
the pole of the reset network (Eq.(2.18) and Eq.(2.19)):
Ri
(50KΩ)
Ci
Shaper
amplifier
Vout(Shaper)
Vout(CSA)
-A
Pole-zero
cancellation
PreamplifierCdet
(1pF)
6/2
n=3Qin
Ipulse
Mf
Mpz
Adaptive continuous reset
Ri2
(50KΩ)
Cd
0.5/50
2.5/50
n=4
Cf
6/2
n=80
5/2
n=70
Ci2
5/2
n=35
Figure 5.2 The 1st order CR-RC pulse shaper design using transistor implementation for passive
components
The resistor (Ri) that defines the shaping time of the pulse shaper adopts the structure
shown in Figure 5.3. The parallel transistors M42 and M43 are operating in the linear
region in order to model the resistor behavior. As discussed in [20], this structure has the
advantage in more stable resistance by minimizing the second order effects of the drain-
to-source current. Transistors M39, M41, and M44 with the same aspect ratios form the
current mirror network that will bias transistor M38 and M40 with an ideal current source
(IRi). Transistor M38 and M40 with the same aspect ratio generate the same gate-to-
source voltage VC:
20
0.5μm 10μm20
50μm 50μm
pz f
W W
L L
(5.8)
44
where VT38 and VT40 are the threshold voltage of the transistor M38 and M40 respectively.
The parallel transistors M42 and M43 having the same aspect ratios generates the resistor
value Ri give as [20]:
42 42 42
1
2 ( / )( )i
ox C T
RC W L V V
(5.10)
An ideal current source (IRi) of 70μA has been used to design the transistors’ geometries
shown in Figure 5.3 for generating the desired resistance value (Ri) of 50kΩ (Table 5.1).
VDD
M44
IRi
(70μA)
2/0.4
n=1
Shaper resistor
biasing network
M41
M40
VDDVDD
M39
M38
M42
M43
+ +
- -
VC VC
2/0.4
n=1
1/2
1/2
2/0.4
n=1
2/0.4
n=1
2/0.4
n=1
Shaper resistor Ri
78μA 78μA
Figure 5.3 The shaper resistor Ri implementation
38
38
38
40 40
40
2
( / )
2
( / )
C GS
RiT
ox
RiT GS
ox
V V
IV
C W L
IV V
C W L
(5.9)
45
5.3 Shaper amplifier design
The amplifier’s structure for the pulse shaper adopts the same structure of the
preamplifier in the CSA (Figure 5.4). The designed shaper amplifier is the scaled down
version of the preamplifier in the CSA in terms of the transistors’ geometries and the
power consumption. The level shifter has been also implemented at the output of the
shaper amplifier to restore its DC potential. The total current drawn for the shaper
amplifier has been scaled down to approximately one quarter of that for the preamplifier
(Figure 5.4). Therefore, the transistors’ sizes in the shaper amplifier have also been scaled
down to approximately one quarter of the transistors’ sizes in the preamplifier in order to
preserve the same output swing range within 0.5V to 2.8V (Figure 4.4 ). The aspect ratios
and the biasing currents for each transistor in the shaper amplifier are shown in Figure 5.4.
46
M20
M25
M24
M23
M21
M22
Vb23
Vb24
Vb25
Vb21
Vb22
VDD
M26
M27
Vb26
VDD
5/0.4
n=10
5/0.4
n=10
5/3
n=32/0.4
n=1
5/0.4
n=4
5/2
n=2
2.4/0.4
n=1
4.5/0.4
n=5
M28
50μA
Vb26
VDD
M30
Vb25
VDD
Vb21
M31
M32
VDD
M33
Vb22
M34
VDD
Vb23
M35
M36
VDD
M29
M37
Vb24
5.02/1
n=20
5.2/2
n=5
5/2
n=5
5.4/2
n=1
5/2
n=5
5/2
n=55/2
n=5
5.6/2
n=5
8/1
n=2
5/2
n=5
Biasing network for shaper
Shaper amplifier
Vb22 Vb23 Vb24 Vb25 Vb26Vb21
53μA 53μA 50μA 46μA
200μA
50μA
In
Vout(Shaper)
180μA
20μA
Figure 5.4 The shaper amplifier design
The AC simulation of the shaper amplifier in open-loop configuration is processed using
HSPICE simulator in frequency range within 1Hz to 10GHz. The gain magnitude and the
phase of the shaper amplifier are presented (Figure 5.5 and Figure 5.6).
47
Figure 5.5 The gain magnitude of the shaper amplifier
Figure 5.6 The phase of the shaper amplifier
Measured from the AC simulation results, the mid-band gain (Av) of the shaper amplifier
has been 64dB and the gain-bandwidth product (GBW) has been 1.85GHz.
0
10
20
30
40
50
60
70
1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10
Gain
(d
B)
Frequency (Hz)
-200
-150
-100
-50
0
50
100
150
200
1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10
Ph
ase
(d
eg)
Frequency (Hz)
48
Chapter 6 The simulation of the analog front-end
signal processing channel
In this chapter, all the designed components including the charge sensitive amplifier and
the pulse shaper will be integrated together to form the analog front-end signal processing
channel (Figure 6.1). The integrated processing channel is simulated in HSPICE with the
detector capacitance (Cdet) equal 1pF and with no detector leakage current noise ( .
The power characteristic for one single analog front-end signal processing channel has
been analyzed by assuming that a 16-channel radiation detector (Figure 1.3) is to be
integrated.
49
M1
M6
M5
M3
M2
M4
Vb3
Vb5
Vb6
Vb2
Vb4
VDD
M7
M8
Vb7
VDD
Vout(CSA)
5/0.4
n=50
5/0.4
n=50
5.5/6
n=2
6/0.4
n=1
5/0.4
n=8
6.8/2
n=5
3.5/0.4
n=1
6.8/0.4
n=5
M9
200μA
Vb7
VDD
M11
Vb6
VDD
Vb2
M12
M13
VDD
M14
M15
VDD
Vb3
M16
M17
VDD
M10
M19
M18
Vb5
5/1
n=9
5/4
n=4
5/4
n=4
5/2
n=12
7.7/1
n=1
5/2
n=12
5/2
n=17
5/2
n=17
4.87/1
n=10
4/2
n=8
5/2
n=17
Biasing network for preamplifier
Preamplifier
Vb3 Vb4 Vb5 Vb6 Vb7Vb2
Cdet
(1pF)
Qin
Ipulse
Cf
(100fF)
Mf
0.5/50
Pole-zero
cancellation
Mpz
Cd
(2pF)
2.5/50
n=4
M20
M25
M24
M23
M21
M22
Vb23
Vb24
Vb25
Vb21
Vb22
VDD
M26
M27
Vb26
VDD
5/0.4
n=10
5/0.4
n=10
5/3
n=3
2/0.4
n=1
5/0.4
n=4
5/2
n=2
2.4/0.4
n=1
4.5/0.4
n=5
M28
50μA
Vb26
VDD
M30
Vb25
VDD
Vb21
M31
M32
VDD
M33
Vb22
M34
VDD
Vb23
M35
M36
VDD
M29
M37
Vb24
5.02/1
n=20
5.2/2
n=5
5/2
n=5
5.4/2
n=1
5/2
n=5
5/2
n=55/2
n=5
5.6/2
n=58/1
n=2
5/2
n=5
Biasing network for shaper
Shaper amplifier
Vb22 Vb23 Vb24 Vb25 Vb26Vb21
Ci
(2pF)
Mf0
M1R
Id1R
(801μA)
If (1μA)
Adaptive continuous reset
5/0.4
n=50
VDD
Vout(Shaper)
6/2
n=3
6/2
n=80
M41
M40
VDDVDD
M39
M38
M42
M43
+ +
- -
VC VC
2/0.4
n=1
1/2
1/2
2/0.4
n=1
2/0.4
n=12/0.4
n=1
Shaper resistor Ri (50kΩ)
M48
M47
VDDVDD
M46
M45
M49
M50
+ +
- -
VC VC
2/0.4
n=1
1/2
1/2
2/0.4
n=1
2/0.4
n=12/0.4
n=1
VDD
M44
IRi
(70μA)
2/0.4
n=1
Shaper resistor biasing
network
5/2
n=70
Ci2
(2pF)
5/2
n=35
3/50
n=70
800μA
100μA
207μA 211μA 202μA
331μA
53μA 53μA 50μA 46μA
200μA
50μA
78μA 78μA
78μA 78μA
Shaper resistor Ri2 (50kΩ)
Figure 6.1 The analog front-end signal processing channel integration
6.1 The power characteristics
The current drawn for each transistor in the analog front-end processing channel have
been simulated and presented in Figure 6.1. Note that for the components including the
50
biasing circuit for the preamplifier, the biasing circuit for the shaper amplifier, adaptive
continuous reset, and the biasing circuit for the shaper resistor will be shared among the
total 16 channels of the analog front-end circuits (Figure 6.2).
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 9
Channel 10
Channel 11
Channel 12
Channel 13
Channel 14
Channel 15
Channel 16
Analog front-end signal processing channel
Mf0
M1R
Id1R
(801μA)
If (1μA)
Adaptive continuous reset
5/0.4
n=50
VDDVDD
M44
IRi
(70μA)
2/0.4
n=1
Shaper resistor
biasing network
Vb2 ~ Vb7
Vb21 ~ Vb26
3/50
n=70
M9
200μA
Vb7
VDD
M11
Vb6
VDD
Vb2
M12
M13
VDD
M14
M15
VDD
Vb3
M16
M17
VDD
M10
M19
M18
Vb5
5/1
n=9
5/4
n=4
5/4
n=4
5/2
n=12
7.7/1
n=1
5/2
n=12
5/2
n=17
5/2
n=17
4.87/1
n=10
4/2
n=8
5/2
n=17
Biasing network for preamplifier
207μA 211μA 202μA
331μA
M28
50μA
Vb26
VDD
M30
Vb25
VDD
Vb21
M31
M32
VDD
M33
Vb22
M34
VDD
Vb23
M35
M36
VDD
M29
M37
Vb24
5.02/1
n=20
5.2/2
n=5
5/2
n=5
5.4/2
n=1
5/2
n=5
5/2
n=55/2
n=5
5.6/2
n=58/1
n=2
5/2
n=5
Biasing network for shaper
53μA 53μA 50μA 46μA
Figure 6.2 The sharing of the biasing circuits among 16 processing channels
In order to derive the overall power consumption per one single processing channel, the
power consumptions for the mentioned four circuitries (Figure 6.2) are approximated by
dividing their power consumptions with the number of channels. The power consumption
for each component in a 16-channel radiation detector is summarized in Table 6.1. The
overall power consumption per single processing channel is equal 5.76mW.
51
Table 6.1 Power consumption summary for single analog front-end signal processing channel
Component Details Current (μA) Power (mW) % Total power
CSA
Preamplifier 900 2.97 51.5 %
Biasing circuit 71 0.23 3.9 %
Adaptive
continuous reset
50 0.17 2.9 %
Shaper
Shaper amplifier 250 0.83 14.4 %
Biasing circuit 16 0.52 9 %
Shaper resistor 316 1.04 18.0 %
Total analog front-end 1724 5.76
6.2 Transient simulation
The HSPICE transient simulation analyzes the timing performance for the designed
analog front-end signal processing channel. The high counting rate simulation performed
by rapid succession of the input current pulses (Ipulse) tests the shaper output response of
the designed signal processing channel.
6.2.1 The charge-to-voltage conversion rate of the analog front-end
signal processing channel
The transient analysis has been used to simulate the output response for the CSA and the
shaper from 0 to 3μs. Corresponding to a radiation event taking place 1μs with an input
charge of 10fC (Figure 6.3), the CSA and shaper output responses are presented in Figure
6.4 and Figure 6.5.
52
Figure 6.3 The input current pulse for a radiation event with input charge Qin =10fC
Figure 6.4 The CSA output response for Qin = 10fC
0
0.2
0.4
0.6
0.8
1
1.2
0 0.5 1 1.5 2 2.5 3
I pu
lse (μ
A)
Time (μs)
Pulse width = 10ns
2.74
2.76
2.78
2.8
2.82
2.84
2.86
2.88
0 0.5 1 1.5 2 2.5 3
Vou
t(C
SA
) (V
)
Time (μs)
53
Figure 6.5 The shaper output response for Qin = 10fC
The amplitude of the shaper output waveform, which is equal to the difference between
the baseline and the peak of the waveform, is measured using Figure 6.5. The amplitude
measured is equal to 30mV for input charge of 10fC. Hence, the charge-to-voltage
conversion of the analog signal processing channel is equal:
The peak of the shaper output waveform takes place at 103ns after the radiation event,
which is close to the targeted shaper peaking time (τp) of 100ns. The shaper output
responses (Vout(Shaper)) corresponding to input charges (Qin) ranging from 1fC to 100fC are
simulated (Figure 6.6).
2.715
2.72
2.725
2.73
2.735
2.74
2.745
2.75
2.755
0 0.5 1 1.5 2 2.5 3
Vo
ut(
Sh
ap
er)
(V
)
Time (μs)
Vsignal(out) = 30mV
τp= 103ns Baseline = 2.75V
( ) 30
3( / )10
signal out
in
V mVmV fC
Q fC (5.11)
54
Figure 6.6 The shaper output responses vs. the input charge
Based on Figure 6.6, the relationship between the shaper output amplitude (Vsignal(out)) and
the input charge (Qin) is plotted (Figure 6.7).
Figure 6.7 The shaper output amplitude vs. the input charge
2.5
2.55
2.6
2.65
2.7
2.75
2.8
0 0.5 1 1.5 2 2.5 3
Vo
ut(
Sh
ap
er)
(V
)
Time (μs)
Qin=1fC
Qin=5fC
Qin=10fC
Qin=20fC
Qin=30fC
Qin=40fC
Qin=50fC
Qin=60fC
Qin=70fC
Qin=80fC
Qin=90fC
Qin=100fC
0
0.05
0.1
0.15
0.2
0.25
0 20 40 60 80 100
Sh
ap
er
ou
tpu
t am
pli
tud
e (
Vsi
gn
al(
ou
t) )
(V
)
Input Charge (fC)
Linear charge-to-voltage conversion
Slope = 3 mV/fC
Qin
Qin
Qin
Qin
Qin
Qin
Qin
Qin
Qin
Qin
Qin
Qin
55
The simulation results presented in Figure 6.7 reveal a linear charge-to-voltage
conversion taking place up to 50fC (equivalent of 312500 electrons). This is the
acceptable input charge range which will result in a proper charge-to-voltage conversion
gain of approximately 3mV/fC.
6.2.2 High counting rate simulation
The high counting rate simulation tests the shaper output response in the case for the
rapid succession of the input current pulses (Ipulse) from 100kHz to 1MHz. Three different
rates of the input current pulses (Ipulse) are presented: 100kHz (Figure 6.8), 500kHz
(Figure 6.10), and 1MHz (Figure 6.12). Their corresponding output responses are shown
in Figure 6.9, Figure 6.11, and Figure 6.13 respectively.
Figure 6.8 The input current pulses with frequency of 100kHz
0
0.2
0.4
0.6
0.8
1
1.2
0 5 10 15 20 25 30 35 40 45 50
I pu
lse (μ
A)
Time (μs)
10ns
56
Figure 6.9 The shaper output response for input pulse frequency of 100kHz
Figure 6.10 The input current pulses with frequency of 500kHz
2.715
2.72
2.725
2.73
2.735
2.74
2.745
2.75
2.755
0 5 10 15 20 25 30 35 40 45 50
Vo
ut(
Sh
ap
er)
(V
)
Time (μs)
0
0.2
0.4
0.6
0.8
1
1.2
0 5 10 15 20 25 30 35 40 45 50
I pu
lse (μ
A)
Time (μs)
No shift in baseline
57
Figure 6.11 The shaper output response for input pulse frequency of 500kHz
Figure 6.12 The input current pulses with frequency of 1MHz
2.715
2.72
2.725
2.73
2.735
2.74
2.745
2.75
2.755
0 5 10 15 20 25 30 35 40 45 50
Vo
ut(
Sh
ap
er)
(V
)
Time (μs)
0
0.2
0.4
0.6
0.8
1
1.2
0 5 10 15 20 25 30 35 40 45 50
I pu
lse
(μA
)
Time (μs)
Baseline shift = 1mV
58
Figure 6.13 The shaper output response for input pulse frequency of 1MHz
In the case of the 100kHz input frequency, there is no shift in the baseline at the shaper
output (Figure 6.9). However, 1mV shift of the baseline after 50μs is measured for the
case of 500kHz input frequency (Figure 6.11). For an even higher input frequency equal
1MHz, 2mV shift of the baseline is measured after 50μs (Figure 6.13). Therefore, in
order to minimize the loss of the resolution to 1mV, the input frequency up to 500kHz is
acceptable for our designed analog front-end signal processing channel.
6.3 Noise simulation
The analog front-end processing channel is simulated in the HSPICE for its noise
characteristic. The HSPICE noise simulation calculates the root mean square (r.m.s) noise
voltage at the shaper output (Vnoise(rms)) for the analog front-end processing channel. The
total r.m.s noise voltage of the entire channel has been 78 from the simulation.
Using the ENC formula given in Eq. (3.3) and the charge-to-voltage conversion rate
2.715
2.72
2.725
2.73
2.735
2.74
2.745
2.75
2.755
0 5 10 15 20 25 30 35 40 45 50
Vo
ut(
Sh
ap
er)
(V
)
Time (μs)
Baseline shift = 2mV
59
given in Figure 6.7, the ENC for the analog front-end signal processing channel is
calculated as:
The HSPICE noise simulation also shows the r.m.s noise voltage at the shaper output
(Vnoise(rms)) for each circuit component in the analog front-end processing channel (Table
6.2). Also calculated by Eq.(3.3), the corresponding ENC contributions from each circuit
component are presented (Table 6.2).
Table 6.2 The noise contribution from each component in the analog front-end signal processing channel
Block Component Vnoise(rms)
( )
ENC
(r.m.s electrons)
CSA preamplifier
Input transistor M1 16.1 34
Current source transistor M4 7.3 15
Current source transistor M6 8 17
CSA’s biasing network 24 50
CSA reset network Feedback transistor Mf 25.7 53
Shaper amplifier
Input transistor M20 11 23
Current source transistor M22 10 20
Current source transistor M24 4.4 9
Shaper’s biasing network 15.9 33
Shaper resistor Resistor Ri, Ri2 59.4 123
Pole-zero cancellation Pole-zero transistor Mpz 7 15
Total 78 163
Table 6.2 shows that the major noise contributors are the CSA input transistor M1, the
biasing network for the CSA, the CSA feedback transistor Mf, and the shaper resistors. For
the secondary noise sources such as the current source transistors M4 and M6, their noise
contributions are both a small fraction of the input transistor noise M1 noise contribution:
( )
( )
19
78(μV 1163 r.m.s electrons
3(mV/fC) 1.6 10 C
/ Hz)
noise rms intotal
signal out
V QENC
V q
(5.12)
60
Extra noise simulations to investigate the validity of the proposed current source transistor
optimization methodology are presented in Appendix A. In addition, the noise simulation for
the detector capacitance (Cdet) ranging from 1pF to 10pF is presented (Figure 6.14).
Figure 6.14 The ENC for the designed signal processing channel vs. the detector capacitances
0
100
200
300
400
500
600
0 2 4 6 8 10 12
EN
C (
r.m
.s e
lectr
on
s)
Detector capacitance (pF)
Slope ≈ 37 [r.m.s electrons/pF]
ENC ≈ 37∙Cdet + 120 [r.m.s electrons]
2 2
4
2 2
1
1519%
34
M
M
ENC
ENC (5.13)
2 2
6
2 2
1
1725%
34
M
M
ENC
ENC (5.14)
61
Chapter 7 The layout design
The layout design for the single analog front-end signal processing channel (Figure 6.1)
has been developed using the IBM 130nm CMOS technology by the Cadence Virtuoso
Layout tool. The layout design is presented with the floor plan for the other 15 channels
(Figure 7.1).
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 9
Channel 10
Channel 11
Channel 12
Channel 13
Channel 14
Channel 15
Channel 16
Adaptive
continuous
reset
Figure 7.1 The floor plan for 16 analog front-end signal processing channels
62
The layout for the single signal processing channel without the layout for the adaptive
continuous reset is presented (Figure 7.2).
Preamplifier +
feedback
capacitor (Cf)
Biasing network for
the preamplifier
Reset network (Rf) +
pole-zero cancellation
Shaper resistors(Ri, Ri2)
Shaper
amplifier
Biasing network for
the shaper amlifier
Shaper
capacitors
(Ci, Ci2)
Figure 7.2 The rotated layout for the single signal processing channel without the adaptive continuous reset
63
7.1 The detailed layout for component
The complete layout design has been divided into 7 sub-blocks (Figure 7.3) for
presenting the layout in greater details.
Vout(CSA)
Vb3 Vb4 Vb5 Vb6 Vb7Vb2
Cdet
(1pF)
Qin
Ipulse
Cf
(100fF)
Mf
0.5/50
Mpz
Cd
(2pF)
2.5/50
n=4
Vb22 Vb23 Vb24 Vb25 Vb26Vb21
Ci
(2pF)
Mf0
M1R
Id1R
(801μA)
If (1μA)
5/0.4
n=50
VDD
Vout(Shaper)
6/2
n=3
6/2
n=80
Shaper resistor (Fig.7.9)
VDD
M44
IRi
(70μA)
2/0.4
n=1
5/2
n=70
Ci2
5/2
n=35
3/50
n=70
Pole-zero
cancellation
+ reset network
+ shaper capacitors
(Figure 7.6)
Preamplifier + feedback capacitor
(Fig.7.4)
Biasing network for preamplifier (Fig.7.5) Biasing network for shaper (Fig.7.8)
Shaper amplifier (Fig.7.7)
Adaptive continuous reset
(Fig.7.10)
M9
200μA
Vb7
VDD
M11
Vb6
VDD
Vb2
M12
M13
VDD
M14
M15
VDD
Vb3
M16
M17
VDD
M10
M19
M18
Vb5
5/1
n=9
5/4
n=4
5/4
n=4
5/2
n=12
7.7/1
n=1
5/2
n=12
5/2
n=17
5/2
n=17
4.87/1
n=10
4/2
n=8
5/2
n=17
M28
50μA
Vb26
VDD
M30
Vb25
VDD
Vb21
M31
M32
VDD
M33
Vb22
M34
VDD
Vb23
M35
M36
VDD
M29
M37
Vb24
5.02/1
n=20
5.2/2
n=5
5/2
n=5
5.4/2
n=1
5/2
n=5
5/2
n=55/2
n=5
5.6/2
n=58/1
n=2
5/2
n=5
M1
M6
M5
M3
M2
M4
Vb3
Vb5
Vb6
Vb2
Vb4
VDD
M7
M8
Vb7
VDD
5/0.4
n=50
5/0.4
n=50
5.5/6
n=2
6/0.4
n=1
5/0.4
n=8
6.8/2
n=5
3.5/0.4
n=1
6.8/0.4
n=5
M41
M40
VDDVDD
M39
M38
M42
M43
+ +
- -
VC VC
2/0.4
n=1
1/2
1/2
2/0.4
n=1
2/0.4
n=12/0.4
n=1
M48
M47
VDDVDD
M46
M45
M49
M50
+ +
- -
VC VC
2/0.4
n=1
1/2
1/2
2/0.4
n=1
2/0.4
n=12/0.4
n=1
M20
M25
M24
M23
M21
M22
Vb23
Vb24
Vb25
Vb21
Vb22
VDD
M26
M27
Vb26
VDD
5/0.4
n=10
5/0.4
n=10
5/3
n=3
2/0.4
n=1
5/0.4
n=4
5/2
n=2
2.4/0.4
n=1
Figure 7.3 The layout division for the analog front-end signal processing channel
64
The layouts for each sub-block in Figure 7.3 are presented from Figure 7.4 to Figure 7.10
with the transistor number clearly marked. All the transistors in the design are of the
multi-fingers layout type, with the width of the finger smaller than 7μm.
M1 M2 M3 M8 M7
Cf M4 M6 M5
VDD
gnd
Figure 7.4 The layout for the preamplifier and the feedback capacitor
M10 M14 M9 M12 M16
M19 M18 M15 M11 M13 M17
VDD
gnd
Figure 7.5 The layout for the biasing network of the preamplifier
Mf Mpz
CdCi2
Ci
Figure 7.6 The layout for the reset network, the pole-zero cancellation circuitry, and the shaper capacitors
65
M20 M21 M23 M27 M26
M22 M25
M24
VDD
gnd
Figure 7.7 The layout for the shaper amplifier
M37
M29 M33 M28 M31 M35
M34 M30 M32 M36
VDD
gnd
Figure 7.8 The layout module for the biasing network of the shaper amplifier
M45 M47M46 M48
M49
M50
M44
VDD
gnd
M43
M42
M40M41M39M38
Figure 7.9 The layout module for the shaper resistor
66
Mf0
M1R
Figure 7.10 The layout module for the adaptive reset network
7.2 The post-layout simulation
To proceed with the post-layout simulation, the parasitics of the low noise amplifiers for
the CSA and the shaper are extracted and then simulated.
7.2.1 The post-layout transient simulation
The CSA and the shaper output responses from the post-layout simulation corresponding
to an input charge (Qin) equivalent of 10fC (Figure 7.11) are shown in Figure 7.12 and
67
Figure 7.13 respectively. The radiation event takes place at 1μs and the simulation is
presented from 0 to 3μs.
Figure 7.11 Input current pulse for a radiation event with input charge equal 10fC
Figure 7.12 The CSA output response for Qin = 10fC
0
0.2
0.4
0.6
0.8
1
1.2
0 0.5 1 1.5 2 2.5 3
I pu
lse (μ
A)
Time (μs)
Pulse width = 10ns
2.72
2.74
2.76
2.78
2.8
2.82
2.84
2.86
0 0.5 1 1.5 2 2.5 3
Vou
t(C
SA
) (V
)
Time (μs)
68
Figure 7.13 The shaper output response for Qin = 10fC
From Figure 7.13 the simulated amplitude of the shaper output response (Vsignal(out)) is
equal 27mV for the input charge (Qin) of 10fC. This corresponds to the charge-to-voltage
conversion rate equal 2.7mV/fC. The increasing shaper peaking time (τp) of 150ns has
been measured. The baseline of the shaper output pulse has changed from 2.75V for the
pre-layout simulation to 2.732 for the post-layout simulation. The difference of the
baseline and the shaper peaking could result from the parasitic extracted from the layout.
The shaper output responses for input charge ranging from 1fC to 100fC are shown in
Figure 7.14.
2.7
2.705
2.71
2.715
2.72
2.725
2.73
2.735
0 0.5 1 1.5 2 2.5 3
Vo
ut(
Sh
ap
er)
(V
)
Time (μs)
Vsignal(out)= 27mV
τp= 150ns Baseline = 2.732V
69
Figure 7.14 The shaper output response vs. the input charge
Based on the shaper output waveforms shown in Figure 7.14, the relationship between
the shaper output amplitude (Vsignal(out)) and the input charge (Qin) is plotted (Figure 7.15).
The linear charge-to-voltage conversion takes place up to 50fC, which matches the pre-
layout simulation result. The charge-to-voltage conversion gain has been 2.7mV/fC,
approximately 10% smaller than for the pre-layout circuit.
2.45
2.5
2.55
2.6
2.65
2.7
2.75
0 0.5 1 1.5 2 2.5 3
Vo
ut(
Sh
ap
er)
(V
)
Time (μs)
Qin=1fC
Qin=5fC
Qin=10fC
Qin=20fC
Qin=30fC
Qin=40fC
Qin=50fC
Qin=60fC
Qin=70fC
Qin=80fC
Qin=90fC
Qin=100fC
Qin
Qin
Qin
Qin
Qin
Qin
Qin
Qin
Qin
Qin
Qin
Qin
70
Figure 7.15 The shaper output amplitude vs. the input charge
The high counting rate simulation test the shaper output response in the case of the high
rate input current pulses (Ipulse) from 100KHz to 1MHz. The shaper output responses for
input pulse frequency equal 100KHz, 333KHz, 500KHz, and 1MHz are presented in
Figure 7.16, Figure 7.17, Figure 7.18, and Figure 7.19 respectively.
0
0.05
0.1
0.15
0.2
0.25
0 20 40 60 80 100
Sh
ap
er
ou
tpu
t am
pli
tud
e (
Vsi
gn
al(
ou
t) )
(V
)
Input Charge (fC)
Linear charge-to-voltage
Slope ≈ 2.7 mV/fC
71
Figure 7.16 The shaper output response for the input pulse frequency of 100kHz
Figure 7.17 The shaper output response for the input pulse frequency of 333kHz
2.7
2.705
2.71
2.715
2.72
2.725
2.73
2.735
0 5 10 15 20 25 30 35 40 45 50
Vo
ut(
Sh
ap
er)
(V
)
Time (μs)
2.7
2.705
2.71
2.715
2.72
2.725
2.73
2.735
0 5 10 15 20 25 30 35 40 45 50
Vou
t(S
haper)
(V
)
Time (μs)
No baseline shift
Baseline shift = 1mV
72
Figure 7.18 The shaper output response for input pulse frequency of 500kHz
Figure 7.19 The shaper output response for input pulse frequency of 1MHz
In the case of the 100kHz input pulse rate, there is no shift in the baseline at the shaper
output (Figure 7.16). However, 1mV shift of the baseline after 50μs is measured for the
case of input pulse frequency equal 333kHz (Figure 7.18). For the 500kHz and the 1MHz
input pulse rate, 3mV and 6mV shift of the baseline are measured after 50μs respectively
2.7
2.705
2.71
2.715
2.72
2.725
2.73
2.735
0 5 10 15 20 25 30 35 40 45 50
Vou
t(S
haper)
(V
)
Time (μs)
2.695
2.7
2.705
2.71
2.715
2.72
2.725
2.73
2.735
0 5 10 15 20 25 30 35 40 45 50
Vou
t(S
haper)
(V
)
Time (μs)
Baseline shift = 3mV
Baseline shift = 6mV
73
(Figure 7.19). Therefore, in order to minimize the loss of the resolution to 1mV, the input
frequency up to 333kHz is acceptable for the designed analog front-end signal processing
channel with the extracted parasitics.
7.2.2 Post-layout noise simulation
The total noise of the post-layout design has been simulated and measured at the shaper
output. The ENC equivalent of 277 r.m.s electrons has been achieved for a detector
capacitance (Cdet) of 1pF. Extra noise simulations have been done by increasing the
detector capacitance (Cdet) from 1pF to 10pF (Figure 7.20).
Figure 7.20 The ENC of the designed signal processing channel with the layout parasitics vs. the detector
capacitance
0
100
200
300
400
500
600
700
800
900
0 2 4 6 8 10 12
EN
C (
r.m
.s e
lectr
on
s)
Detector capacitance (pF)
Slope ≈ 57 [r.m.s electrons/pF]
ENC ≈ 57∙Cdet + 200 [r.m.s electrons]
74
7.3 Performance summary
The simulation results of the analog front-end signal processing channel for the pre-
layout and post-layout system are summarized in Table 7.1.
Table 7.1 The pre-layout and post-layout performance summaries for the analog front-end signal
processing channel
Category Pre-layout Post-layout
Shaper peaking time (τp) 103ns 150ns
DC potential of the shaper baseline 2.75V 2.731V
ENC for Cdet = 1pF 170 r.m.s electrons 277 r.m.s electrons
ENC vs. Cdet in pF
[r.m.s electrons]
37∙Cdet + 120
57∙Cdet + 200
Charge-to-voltage conversion 3mV/fC 2.7mV/fC
Input charge range Up to 50fC Up to 50fC
Maximum input pulse frequency for the
baseline shift smaller than 1mV
500kHz 333kHz
As a result of the parasitic extraction, the post-layout simulation has shown a small
decrease in performance for the noise characteristics and for the shaper peaking time.
Based on the post-layout simulation results, the designed analog front-end signal
processing channel has been compared to other related work (Table 7.2).
Table 7.2 Performance comparisons between this work and other related works
work Ref. [19] Ref. [21] This work
Technology 0.8μm 0.35μm 0.13μm
Power supply 4V 3.3V 3.3V
Shaper order 1st
order 2nd
order 1st order
Peaking time 45ns 195ns 150ns
Charge-to-voltage
conversion gain
20mV/fC 18mV/fC 2.7mV/fC
Cf N/A 100fF 100fF
Power per channel 1mW 13mW 5.76mW
ENC vs. Cdet in pF
[r.m.s electrons]
44∙Cdet+450
10∙Cdet+275
57∙Cdet+200
Input charge range N/A < 70fC < 50fC
75
Table 7.2 shows that the total noise for this work in terms of the ENC corresponding to
the 1pF detector capacitance has been smaller than the total noise for the other two
related works. In addition, the channel power consumption is approximately half of that
reported in [21]. This comparison shows that this work has achieved the low noise
performance with respect to the low capacitance pixelated semiconductor detector by a
relatively efficient power usage.
76
Chapter 8 Conclusion and future work
In this thesis, the low noise analog front-end detector signal processing channel for the
application in the low capacitance pixelated semiconductor detector system has been
designed and analyzed using the IBM 130nm CMOS technology. The designed signal
processing channel features a noise optimized charge sensitive amplifier (CSA) and a fast
first order CR-RC pulse shaper. The noise contribution of the CSA preamplifier that
adopts the dual PMOS cascode amplifier structure has been well optimized by applying
the proposed current source transistor noise optimization methodology. The high
feedback resistance (Rf) of CSA in the mega-ohm range has been achieved with the
implementation of the adaptive continuous reset circuitry. In order to stabilize the
baseline shift due to the extra pole generated by the reset network, the pole-zero
cancellation circuitry has been designed and integrated with the CR-RC pulse shaper.
The CMOS transistor layout design for one single signal processing channel has been
generated and simulated with the extraction of the parasitics. Corresponding to the low
detector capacitance (Cdet) of 1pF, the HSPICE simulation shows that the low Equivalent
Noise Charge (ENC) of 277 r.m.s electrons has been achieved for the shaper peaking time
(τp) equivalent of 150ns and the channel power consumption of 5.76mW. The charge-to-
voltage conversion has been 2.7mV/fC for the input charge range (Qin) within 50fC. The
post-layout simulation has shown a small decrease in performance for the noise
77
characteristics and the shaper peaking time (τp). The performance comparison between
the pre-layout and the post-layout simulation is summarized in Table 8.1.
Table 8.1 The pre-layout and post-layout performance summaries for the analog front-end signal
processing channel
Category Pre-layout Post-layout
Power supply (VDD) 3.3V 3.3V
Shaper peaking time (τp) 103ns 150ns
ENC for Cdet = 1pF 170 r.m.s electrons 277 r.m.s electrons
ENC vs. Cdet in pF
[r.m.s electrons]
37∙Cdet +120
57∙Cdet+200
Charge-to-voltage conversion 3mV/fC 2.7mV/fC
Input charge range Up to 50fC Up to 50fC
The performance of the designed analog front-end signal processing channel based on the
post-layout simulation has also been compared with other related works. The comparison
shows that this work has achieved the low noise performance with respect to the low
capacitance pixelated semiconductor detector by a relatively efficient power usage.
For future work considerations, a complete and optimized layout which includes the
entire 16 analog front-end signal processing channels is targeted. Additionally, the
smaller voltage supply will be considered for achieving the lower single channel power
consumption. Lastly, we would like to wrap up the complete IC design of the pixelated
semiconductor radiation detector by implementing the additional signal extraction block
that includes the Analog-to-Digital signal processing circuitry.
78
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Appendix A. The test of the current source noise
optimization methodology
In this section the validity of the proposed current source transistor noise optimization
methodology is examined [22]. The methodology is applied to design four preamplifiers
in the CSA such that:
The four preamplifiers are designed with the same amplifier structure (Figure
4.2), bias condition (Figure 4.4), and the system parameters (Figure 4.1).
The four preamplifiers are designed with different current source thermal noise
scaling factor and current source flicker noise scaling factor (Figure
A.1).
Figure A.1 Four CSAs with 4 selected current source noise scaling factors
The input transistor optimization methodology is first applied to find the optimal
geometry of the input transistor M1 for all four preamplifiers is: (W/L)1=200μm/0.4μm.
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As a next step, the current source optimization methodology is applied to design the
current source transistors M4 and M6 in all four preamplifiers using Eq.(3.18) and
Eq.(3.19). The optimized current source transistors’ geometries are presented in Figure
A.2.
Figure A.2 The noise optimized current source transistor geometries for M4 and M6
The four designed preamplifiers will be simulated together with the first order CR-RC
shaper of shaping time (τp) equal 100ns. The shaper is designed using the macromodel
op-amp and the passive components in HSPICE (Figure A.3).
84
Ri (100kΩ)
Ci (1pF)
Cd
(1pF)
Rd
(100kΩ)
Op-amp
macromodel
Vout(CSA) Vout(Shaper)
Figure A.3 First order CR-RC pulse shaper designed in HSPICE
During the HSPICE noise simulation, the noise contributions from the detector, reset
network, and the shaper are ignored. The thermal and the flicker noise contribution of the
input transistor M1 and the current source transistor M4 and M6 for the four
preamplifiers are presented in Figure A.4.
Figure A.4 Simulated ENC for four CSAs designed with current source thermal noise scaling factor =
10% and the current source flicker noise scaling factor = 10% to 40%
85
Based on the noise simulation result in Figure A.4, the simulated noise scaling factors
and are compared with their theoretical values (Table A.1)
Table A.1 Theoretical and values and their simulated results for current source transistor M4 and
M6 in four preamplifiers
Preamplifier
Analytical model Simulation result
M4 M6
(1) 10% 10% 20.9% 11.9% 23.0% 4.0%
(2) 10% 20% 20.3% 21.0% 23.1% 9.9%
(3) 10% 30% 20.3% 30.0% 22.5% 14.0%
(4) 10% 40% 20.5% 39.15% 21.9% 16.54%
The HSPICE noise simulation result shows that the simulated values for current
source transistors M4 and M6 are approximately 10% higher than the theoretical
results. On the other hand, the analytical model for is very close to the simulation
results for the current source transistor M4, but it is only about one-half of the theoretical
for the current source transistor M6. These discrepancies is expected since the
simple formulas for gm in the strong inversion and for the Cg formula in Eq.(3.7) are not
sufficiently accurate to describe the MOSFET electrical behavior for deep submicron
technology. Other factor that contributed to these discrepancies is the flicker noise
coefficient of the MOSFET Kf that is varied by the biasing condition and the channel
length. In all simulation cases, thermal and flicker noise contribution of current source
transistors M4 and M6 were a fraction of the thermal noise of the input transistor M1.
Thus, the proposed current source transistor noise optimization technology can be served
as a reference guide for CSA designers especially for CSAs and MOSFETs operating at
even smaller power supplies.